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AI Engine-ML v2 Intrinsics User Guide
v2025.1
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8x8_8x8 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_8x8_8x8_conf (v64uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_8x8_8x8_conf (v64uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_8x8_8x8_conf (v64int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_8x8_8x8_conf (v64int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_8x8_8x8_conf (v64float8 a, v64float8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64float8 a, v64float8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64float8 a, v64float8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64float8 a, v64float8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_8x8_8x8_conf (v64float8 a, v64bfloat8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64float8 a, v64bfloat8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64float8 a, v64bfloat8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64float8 a, v64bfloat8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_8x8_8x8_conf (v64bfloat8 a, v64float8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64bfloat8 a, v64float8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64bfloat8 a, v64float8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64bfloat8 a, v64float8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_8x8_8x8_conf (v64bfloat8 a, v64bfloat8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64bfloat8 a, v64bfloat8 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64bfloat8 a, v64bfloat8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64bfloat8 a, v64bfloat8 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
8x8_8x8 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_8x8_8x8_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x8_8x8_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x8_8x8_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_8x8_8x8_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x8_8x8_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x8_8x8_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_8x8_8x8_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x8_8x8_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x8_8x8_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_8x8_8x8_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x8_8x8_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x8_8x8_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x8_8x8_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x8_8x8_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x8_8x8_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_8x8_8x8_conf (v64float8 a, int sgn_x, v64float8 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_8x8_8x8_conf (v64float8 a, int sgn_x, v64float8 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_8x8_8x8_conf (v64float8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64float8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64float8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64float8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_8x8_8x8_conf (v64float8 a, int sgn_x, v64bfloat8 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_8x8_8x8_conf (v64float8 a, int sgn_x, v64bfloat8 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_8x8_8x8_conf (v64float8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64float8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64float8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64float8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64float8 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64float8 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64float8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64bfloat8 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64bfloat8 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_8x8_8x8_conf (v64bfloat8 a, int sgn_x, v64bfloat8 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
elem_64 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_elem_64_conf (v64uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, unsigned char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, unsigned char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, unsigned char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, unsigned char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, signed char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, signed char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, signed char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, signed char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int8 a, unsigned char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, unsigned char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, unsigned char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, unsigned char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int8 a, signed char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, signed char b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, signed char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, signed char b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, unsigned short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, unsigned short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, unsigned short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, unsigned short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, signed short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, signed short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, signed short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, signed short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int16 a, unsigned short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, unsigned short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, unsigned short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, unsigned short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int16 a, signed short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, signed short b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, signed short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, signed short b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, v64bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, v64bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, v64bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, v64bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, v64float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, v64float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, v64float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, v64float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64float16 a, v64bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, v64bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, v64bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, v64bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64float16 a, v64float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, v64float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, v64float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, v64float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64float16 a, bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, bfloat16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, bfloat16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mac_elem_64_conf (v64float16 a, float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, float16 b, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, float16 b, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
elem_64 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_elem_64_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint8 a, int sgn_x, unsigned char b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint8 a, int sgn_x, unsigned char b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint8 a, int sgn_x, signed char b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint8 a, int sgn_x, signed char b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int8 a, int sgn_x, unsigned char b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int8 a, int sgn_x, unsigned char b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, int sgn_x, unsigned char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int8 a, int sgn_x, signed char b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int8 a, int sgn_x, signed char b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int8 a, int sgn_x, signed char b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, int sgn_x, unsigned short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, int sgn_x, signed short b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64bfloat16 a, int sgn_x, v64bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64bfloat16 a, int sgn_x, v64bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64bfloat16 a, int sgn_x, v64float16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64bfloat16 a, int sgn_x, v64float16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64float16 a, int sgn_x, v64bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64float16 a, int sgn_x, v64bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64float16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, int sgn_x, v64bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64float16 a, int sgn_x, v64float16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64float16 a, int sgn_x, v64float16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64float16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, int sgn_x, v64float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64bfloat16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64bfloat16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64bfloat16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64bfloat16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64bfloat16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64bfloat16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64float16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64float16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64float16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, int sgn_x, bfloat16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | mul_elem_64_conf (v64float16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v64accfloat | negmul_elem_64_conf (v64float16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v64accfloat | mac_elem_64_conf (v64float16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | msc_elem_64_conf (v64float16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v64accfloat | addmac_elem_64_conf (v64float16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v64accfloat | addmsc_elem_64_conf (v64float16 a, int sgn_x, float16 b, int sgn_y, v64accfloat acc1, v64accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
elem_64_2 with dynamic negation of multiplication result | |
| v64acc32 | mul_elem_64_2_conf (v128uint8 a, v128uint8 b, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128uint8 a, v128uint8 b, int sub_mul) |
| v64acc32 | mul_elem_64_2_conf (v128uint8 a, v128int8 b, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128uint8 a, v128int8 b, int sub_mul) |
| v64acc32 | mul_elem_64_2_conf (v128int8 a, v128uint8 b, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128int8 a, v128uint8 b, int sub_mul) |
| v64acc32 | mul_elem_64_2_conf (v128int8 a, v128int8 b, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128int8 a, v128int8 b, int sub_mul) |
elem_64_2 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_elem_64_2_conf (v128uint8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128uint8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128uint8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128uint8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_2_conf (v128uint8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128uint8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128uint8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128uint8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_2_conf (v128int8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128int8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128int8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128int8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_2_conf (v128int8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128int8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128int8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128int8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_64_2 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_elem_64_2_conf (v128uint8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128uint8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_2_conf (v128uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_2_conf (v128uint8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128uint8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_2_conf (v128uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_2_conf (v128int8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128int8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_2_conf (v128int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_2_conf (v128int8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_2_conf (v128int8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_2_conf (v128int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_2_conf (v128int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_2_conf (v128int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_2_conf (v128int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_8x8_8ch with dynamic negation of multiplication result | |
| v64acc32 | mul_conv_8x8_8ch_conf (v128uint8 a, v64uint8 b, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128uint8 a, v64uint8 b, int sub_mul) |
| v64acc32 | mul_conv_8x8_8ch_conf (v128uint8 a, v64int8 b, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128uint8 a, v64int8 b, int sub_mul) |
| v64acc32 | mul_conv_8x8_8ch_conf (v128int8 a, v64uint8 b, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128int8 a, v64uint8 b, int sub_mul) |
| v64acc32 | mul_conv_8x8_8ch_conf (v128int8 a, v64int8 b, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128int8 a, v64int8 b, int sub_mul) |
conv_8x8_8ch with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_conv_8x8_8ch_conf (v128uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_8x8_8ch with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_8x8_8ch_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_64x8 with dynamic negation of multiplication result | |
| v64acc32 | mul_conv_64x8_conf (v128uint8 a, v64uint8 b, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128uint8 a, v64uint8 b, int sub_mul) |
| v64acc32 | mul_conv_64x8_conf (v128uint8 a, v64int8 b, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128uint8 a, v64int8 b, int sub_mul) |
| v64acc32 | mul_conv_64x8_conf (v128int8 a, v64uint8 b, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128int8 a, v64uint8 b, int sub_mul) |
| v64acc32 | mul_conv_64x8_conf (v128int8 a, v64int8 b, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128int8 a, v64int8 b, int sub_mul) |
conv_64x8 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_conv_64x8_conf (v128uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128uint8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128uint8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_conv_64x8_conf (v128uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128uint8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128uint8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_conv_64x8_conf (v128int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128int8 a, v64uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128int8 a, v64uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_conv_64x8_conf (v128int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128int8 a, v64int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128int8 a, v64int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_64x8 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_conv_64x8_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_64x8_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128uint8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_conv_64x8_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_64x8_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128uint8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_conv_64x8_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_64x8_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128int8 a, int sgn_x, v64uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_conv_64x8_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_conv_64x8_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_conv_64x8_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_conv_64x8_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_conv_64x8_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_conv_64x8_conf (v128int8 a, int sgn_x, v64int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
4x8_8x16 with dynamic negation of multiplication result | |
| v64acc32 | mul_4x8_8x16_conf (v64uint8 a, v128uint8 b, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64uint8 a, v128uint8 b, int sub_mul) |
| v64acc32 | mul_4x8_8x16_conf (v64uint8 a, v128int8 b, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64uint8 a, v128int8 b, int sub_mul) |
| v64acc32 | mul_4x8_8x16_conf (v64int8 a, v128uint8 b, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64int8 a, v128uint8 b, int sub_mul) |
| v64acc32 | mul_4x8_8x16_conf (v64int8 a, v128int8 b, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64int8 a, v128int8 b, int sub_mul) |
4x8_8x16 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_4x8_8x16_conf (v64uint8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64uint8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64uint8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64uint8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_4x8_8x16_conf (v64uint8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64uint8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64uint8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64uint8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_4x8_8x16_conf (v64int8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64int8 a, v128uint8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64int8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64int8 a, v128uint8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_4x8_8x16_conf (v64int8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64int8 a, v128int8 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64int8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64int8 a, v128int8 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
4x8_8x16 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_4x8_8x16_conf (v64uint8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64uint8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_4x8_8x16_conf (v64uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64uint8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_4x8_8x16_conf (v64uint8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64uint8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_4x8_8x16_conf (v64uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64uint8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_4x8_8x16_conf (v64int8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64int8 a, int sgn_x, v128uint8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_4x8_8x16_conf (v64int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64int8 a, int sgn_x, v128uint8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_4x8_8x16_conf (v64int8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_4x8_8x16_conf (v64int8 a, int sgn_x, v128int8 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_4x8_8x16_conf (v64int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_4x8_8x16_conf (v64int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_4x8_8x16_conf (v64int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_4x8_8x16_conf (v64int8 a, int sgn_x, v128int8 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 addmac_4x8_8x16 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_4x8_8x16 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_4x8_8x16 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_4x8_8x16 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_4x8_8x16_conf | ( | v64uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_8x8_8x8 | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64acc32 addmac_8x8_8x8 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x8_8x8 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x8_8x8 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x8_8x8 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_8x8_8x8_conf | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x8_8x8_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_64x8 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_64x8 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_64x8 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_64x8_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_8x8_8ch | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_8x8_8ch | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_8x8_8ch | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmac_elem_64 | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64_2 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64_2 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64_2 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64_2 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_2_conf | ( | v128uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmac_elem_64_conf | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| signed short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| signed char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| signed short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| signed char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_4x8_8x16 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_4x8_8x16 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_4x8_8x16 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_4x8_8x16_conf | ( | v64uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_8x8_8x8 | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64acc32 addmsc_8x8_8x8 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x8_8x8 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x8_8x8 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x8_8x8 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_8x8_8x8_conf | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x8_8x8_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_64x8 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_64x8 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_64x8 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_64x8_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64accfloat addmsc_elem_64 | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64_2 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64_2 | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64_2 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64_2 | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_2_conf | ( | v128uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64accfloat addmsc_elem_64_conf | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc1, | ||
| v64accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| signed short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| signed char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| signed short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| signed char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_4x8_8x16_conf | ( | v64uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8 | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_8x8_8x8_conf | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x8_8x8_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_64x8_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat mac_elem_64 | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc ) |
| v64acc32 mac_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_2_conf | ( | v128uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mac_elem_64_conf | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| signed short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| signed char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| signed short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| signed char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_4x8_8x16_conf | ( | v64uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8 | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_8x8_8x8_conf | ( | v64float8 | a, |
| v64float8 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x8_8x8_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_64x8_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_conv_8x8_8ch_conf | ( | v128uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc ) |
| v64accfloat msc_elem_64 | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc ) |
| v64acc32 msc_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128int8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128int8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128int8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128uint8 | a, |
| int | sgn_x, | ||
| v128uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128uint8 | a, |
| v128int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_2_conf | ( | v128uint8 | a, |
| v128uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat msc_elem_64_conf | ( | v64float16 | a, |
| v64float16 | b, | ||
| v64accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| signed short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| signed char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| signed short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| unsigned short | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| signed char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| unsigned char | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64int8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| int | sgn_x, | ||
| v64uint8 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| signed char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| unsigned char | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| v64int8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint8 | a, |
| v64uint8 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64accfloat mul_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_8x8_8x8 | ( | v64bfloat8 | a, |
| v64bfloat8 | b ) |
| v64accfloat mul_8x8_8x8 | ( | v64bfloat8 | a, |
| v64float8 | b ) |
| v64accfloat mul_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_8x8_8x8 | ( | v64float8 | a, |
| v64bfloat8 | b ) |
| v64accfloat mul_8x8_8x8 | ( | v64float8 | a, |
| v64float8 | b ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_8x8_8x8_conf | ( | v64float8 | a, |
| v64float8 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| bfloat16 | b ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| float16 | b ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| v64bfloat16 | b ) |
| v64accfloat mul_elem_64 | ( | v64bfloat16 | a, |
| v64float16 | b ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| bfloat16 | b ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| float16 | b ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| v64bfloat16 | b ) |
| v64accfloat mul_elem_64 | ( | v64float16 | a, |
| v64float16 | b ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat mul_elem_64_conf | ( | v64float16 | a, |
| v64float16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_8x8_8x8 | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_8x8_8x8 | ( | v64bfloat8 | a, |
| v64bfloat8 | b ) |
| v64accfloat negmul_8x8_8x8 | ( | v64bfloat8 | a, |
| v64float8 | b ) |
| v64accfloat negmul_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_8x8_8x8 | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_8x8_8x8 | ( | v64float8 | a, |
| v64bfloat8 | b ) |
| v64accfloat negmul_8x8_8x8 | ( | v64float8 | a, |
| v64float8 | b ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64bfloat8 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64bfloat8 | a, |
| v64float8 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64bfloat8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64float8 | a, |
| int | sgn_x, | ||
| v64float8 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64float8 | a, |
| v64bfloat8 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_8x8_8x8_conf | ( | v64float8 | a, |
| v64float8 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| bfloat16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| float16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| v64bfloat16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64bfloat16 | a, |
| v64float16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| bfloat16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| float16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| v64bfloat16 | b ) |
| v64accfloat negmul_elem_64 | ( | v64float16 | a, |
| v64float16 | b ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| v64bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64bfloat16 | a, |
| v64float16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| int | sgn_x, | ||
| v64float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| v64bfloat16 | b, | ||
| int | sub_mul ) |
| v64accfloat negmul_elem_64_conf | ( | v64float16 | a, |
| v64float16 | b, | ||
| int | sub_mul ) |