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AI Engine-ML v2 Intrinsics User Guide
v2025.1
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8x2_2x8 with dynamic negation of multiplication result | |
| v64acc32 | mul_8x2_2x8_conf (v32uint16 a, v32uint16 b, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32uint16 a, v32uint16 b, int sub_mul) |
| v64acc32 | mul_8x2_2x8_conf (v32uint16 a, v32int16 b, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32uint16 a, v32int16 b, int sub_mul) |
| v64acc32 | mul_8x2_2x8_conf (v32int16 a, v32uint16 b, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32int16 a, v32uint16 b, int sub_mul) |
| v64acc32 | mul_8x2_2x8_conf (v32int16 a, v32int16 b, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32int16 a, v32int16 b, int sub_mul) |
8x2_2x8 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_8x2_2x8_conf (v32uint16 a, v32uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32uint16 a, v32uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32uint16 a, v32uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32uint16 a, v32uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_8x2_2x8_conf (v32uint16 a, v32int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32uint16 a, v32int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32uint16 a, v32int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32uint16 a, v32int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_8x2_2x8_conf (v32int16 a, v32uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32int16 a, v32uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32int16 a, v32uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32int16 a, v32uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_8x2_2x8_conf (v32int16 a, v32int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32int16 a, v32int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32int16 a, v32int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32int16 a, v32int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
8x2_2x8 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_8x2_2x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x2_2x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_8x2_2x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x2_2x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_8x2_2x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x2_2x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_8x2_2x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_8x2_2x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_8x2_2x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_8x2_2x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_8x2_2x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_8x2_2x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_64 with dynamic negation of multiplication result | |
| v64acc32 | mul_elem_64_conf (v64uint16 a, v64uint16 b, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, v64uint16 b, int sub_mul) |
| v64acc32 | mul_elem_64_conf (v64uint16 a, v64int16 b, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, v64int16 b, int sub_mul) |
| v64acc32 | mul_elem_64_conf (v64int16 a, v64uint16 b, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, v64uint16 b, int sub_mul) |
| v64acc32 | mul_elem_64_conf (v64int16 a, v64int16 b, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, v64int16 b, int sub_mul) |
elem_64 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v64acc32 | mac_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, v64uint16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mac_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, v64int16 b, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_64 with dynamic sign and dynamic negation of multiplication result | |
| v64acc32 | mul_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | mul_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | negmul_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v64acc32 | mac_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | msc_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v64acc32 | addmac_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v64acc32 | addmsc_elem_64_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v64acc32 acc1, v64acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_32_32b with dynamic negation of multiplication result | |
| v32acc32 | mul_elem_32_32b_conf (v32uint16 a, v32uint16 b, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32uint16 a, v32uint16 b, int sub_mul) |
| v32acc32 | mul_elem_32_32b_conf (v32uint16 a, v32int16 b, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32uint16 a, v32int16 b, int sub_mul) |
| v32acc32 | mul_elem_32_32b_conf (v32int16 a, v32uint16 b, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32int16 a, v32uint16 b, int sub_mul) |
| v32acc32 | mul_elem_32_32b_conf (v32int16 a, v32int16 b, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32int16 a, v32int16 b, int sub_mul) |
elem_32_32b with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v32acc32 | mac_elem_32_32b_conf (v32uint16 a, v32uint16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32uint16 a, v32uint16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32uint16 a, v32uint16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32uint16 a, v32uint16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | mac_elem_32_32b_conf (v32uint16 a, v32int16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32uint16 a, v32int16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32uint16 a, v32int16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32uint16 a, v32int16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | mac_elem_32_32b_conf (v32int16 a, v32uint16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32int16 a, v32uint16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32int16 a, v32uint16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32int16 a, v32uint16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | mac_elem_32_32b_conf (v32int16 a, v32int16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32int16 a, v32int16 b, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32int16 a, v32int16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32int16 a, v32int16 b, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_32_32b with dynamic sign and dynamic negation of multiplication result | |
| v32acc32 | mul_elem_32_32b_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc32 | mac_elem_32_32b_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | mul_elem_32_32b_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc32 | mac_elem_32_32b_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | mul_elem_32_32b_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc32 | mac_elem_32_32b_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | mul_elem_32_32b_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc32 | negmul_elem_32_32b_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc32 | mac_elem_32_32b_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | msc_elem_32_32b_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc32 | addmac_elem_32_32b_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc32 | addmsc_elem_32_32b_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc32 acc1, v32acc32 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
4x4_4x8 with dynamic negation of multiplication result | |
| v32acc64 | mul_4x4_4x8_conf (v32uint16 a, v32uint16 b, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32uint16 a, v32uint16 b, int sub_mul) |
| v32acc64 | mul_4x4_4x8_conf (v32uint16 a, v32int16 b, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32uint16 a, v32int16 b, int sub_mul) |
| v32acc64 | mul_4x4_4x8_conf (v32int16 a, v32uint16 b, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32int16 a, v32uint16 b, int sub_mul) |
| v32acc64 | mul_4x4_4x8_conf (v32int16 a, v32int16 b, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32int16 a, v32int16 b, int sub_mul) |
4x4_4x8 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v32acc64 | mac_4x4_4x8_conf (v32uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_4x4_4x8_conf (v32uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_4x4_4x8_conf (v32int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_4x4_4x8_conf (v32int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
4x4_4x8 with dynamic sign and dynamic negation of multiplication result | |
| v32acc64 | mul_4x4_4x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_4x4_4x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_4x4_4x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_4x4_4x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_4x4_4x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_4x4_4x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_4x4_4x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_4x4_4x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_4x4_4x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_4x4_4x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_4x4_4x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_4x4_4x8_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_32 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v32acc64 | mac_elem_32_conf (v32uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, unsigned short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, unsigned short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, unsigned short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, unsigned short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, signed short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, signed short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, signed short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, signed short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32int16 a, unsigned short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, unsigned short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, unsigned short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, unsigned short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_conf (v32int16 a, signed short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, signed short b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, signed short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, signed short b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, v32bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, v32bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, v32bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, v32bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, v32float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, v32float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, v32float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, v32float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32float16 a, v32bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, v32bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, v32bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, v32bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32float16 a, v32float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, v32float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, v32float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, v32float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32float16 a, bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, bfloat16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, bfloat16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mac_elem_32_conf (v32float16 a, float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, float16 b, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, float16 b, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
elem_32 with dynamic sign and dynamic negation of multiplication result | |
| v32acc64 | mul_elem_32_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32uint16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32uint16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32uint16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32uint16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32uint16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32uint16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32uint16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32uint16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32int16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32int16 a, int sgn_x, unsigned short b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32int16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, int sgn_x, unsigned short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_conf (v32int16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_conf (v32int16 a, int sgn_x, signed short b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_conf (v32int16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_conf (v32int16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_conf (v32int16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_conf (v32int16 a, int sgn_x, signed short b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32bfloat16 a, int sgn_x, v32bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32bfloat16 a, int sgn_x, v32bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32bfloat16 a, int sgn_x, v32float16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32bfloat16 a, int sgn_x, v32float16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32float16 a, int sgn_x, v32bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32float16 a, int sgn_x, v32bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32float16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, int sgn_x, v32bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32float16 a, int sgn_x, v32float16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32float16 a, int sgn_x, v32float16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32float16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, int sgn_x, v32float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32bfloat16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32bfloat16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32bfloat16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32bfloat16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32bfloat16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32bfloat16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32float16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32float16 a, int sgn_x, bfloat16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32float16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, int sgn_x, bfloat16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | mul_elem_32_conf (v32float16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v32accfloat | negmul_elem_32_conf (v32float16 a, int sgn_x, float16 b, int sgn_y, int sub_mul) |
| v32accfloat | mac_elem_32_conf (v32float16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | msc_elem_32_conf (v32float16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc, int zero_acc, int sub_mul, int sub_acc1) |
| v32accfloat | addmac_elem_32_conf (v32float16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
| v32accfloat | addmsc_elem_32_conf (v32float16 a, int sgn_x, float16 b, int sgn_y, v32accfloat acc1, v32accfloat acc2, int zero_acc1, int sub_mul, int sub_acc1, int sub_acc2) |
elem_32_2 with dynamic negation of multiplication result | |
| v32acc64 | mul_elem_32_2_conf (v64uint16 a, v64uint16 b, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64uint16 a, v64uint16 b, int sub_mul) |
| v32acc64 | mul_elem_32_2_conf (v64uint16 a, v64int16 b, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64uint16 a, v64int16 b, int sub_mul) |
| v32acc64 | mul_elem_32_2_conf (v64int16 a, v64uint16 b, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64int16 a, v64uint16 b, int sub_mul) |
| v32acc64 | mul_elem_32_2_conf (v64int16 a, v64int16 b, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64int16 a, v64int16 b, int sub_mul) |
elem_32_2 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v32acc64 | mac_elem_32_2_conf (v64uint16 a, v64uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64uint16 a, v64uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64uint16 a, v64uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64uint16 a, v64uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_2_conf (v64uint16 a, v64int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64uint16 a, v64int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64uint16 a, v64int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64uint16 a, v64int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_2_conf (v64int16 a, v64uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64int16 a, v64uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64int16 a, v64uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64int16 a, v64uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_elem_32_2_conf (v64int16 a, v64int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64int16 a, v64int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64int16 a, v64int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64int16 a, v64int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
elem_32_2 with dynamic sign and dynamic negation of multiplication result | |
| v32acc64 | mul_elem_32_2_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_2_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64uint16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_2_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_2_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64uint16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_2_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_2_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64int16 a, int sgn_x, v64uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_elem_32_2_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_elem_32_2_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_elem_32_2_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_elem_32_2_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_elem_32_2_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_elem_32_2_conf (v64int16 a, int sgn_x, v64int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_32x4 with dynamic negation of multiplication result | |
| v32acc64 | mul_conv_32x4_conf (v64uint16 a, v32uint16 b, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64uint16 a, v32uint16 b, int sub_mul) |
| v32acc64 | mul_conv_32x4_conf (v64uint16 a, v32int16 b, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64uint16 a, v32int16 b, int sub_mul) |
| v32acc64 | mul_conv_32x4_conf (v64int16 a, v32uint16 b, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64int16 a, v32uint16 b, int sub_mul) |
| v32acc64 | mul_conv_32x4_conf (v64int16 a, v32int16 b, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64int16 a, v32int16 b, int sub_mul) |
conv_32x4 with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v32acc64 | mac_conv_32x4_conf (v64uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_conv_32x4_conf (v64uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_conv_32x4_conf (v64int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_conv_32x4_conf (v64int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_32x4 with dynamic sign and dynamic negation of multiplication result | |
| v32acc64 | mul_conv_32x4_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_32x4_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_conv_32x4_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_32x4_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_conv_32x4_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_32x4_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_conv_32x4_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_32x4_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_32x4_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_32x4_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_32x4_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_32x4_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_4x4_8ch with dynamic negation of multiplication result | |
| v32acc64 | mul_conv_4x4_8ch_conf (v64uint16 a, v32uint16 b, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64uint16 a, v32uint16 b, int sub_mul) |
| v32acc64 | mul_conv_4x4_8ch_conf (v64uint16 a, v32int16 b, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64uint16 a, v32int16 b, int sub_mul) |
| v32acc64 | mul_conv_4x4_8ch_conf (v64int16 a, v32uint16 b, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64int16 a, v32uint16 b, int sub_mul) |
| v32acc64 | mul_conv_4x4_8ch_conf (v64int16 a, v32int16 b, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64int16 a, v32int16 b, int sub_mul) |
conv_4x4_8ch with dynamic negation of multiplication result, zeroing of acc1, negation of acc1 | |
| v32acc64 | mac_conv_4x4_8ch_conf (v64uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64uint16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64uint16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64uint16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64uint16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64int16 a, v32uint16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64int16 a, v32uint16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64int16 a, v32int16 b, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64int16 a, v32int16 b, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
conv_4x4_8ch with dynamic sign and dynamic negation of multiplication result | |
| v32acc64 | mul_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64uint16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32uint16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | mul_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | negmul_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, int sub_mul) |
| v32acc64 | mac_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | msc_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc, int zero_acc, int shift16, int sub_mul, int sub_acc1) |
| v32acc64 | addmac_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 | addmsc_conv_4x4_8ch_conf (v64int16 a, int sgn_x, v32int16 b, int sgn_y, v32acc64 acc1, v32acc64 acc2, int zero_acc1, int shift16, int sub_mul, int sub_acc1, int sub_acc2) |
| v32acc64 addmac_4x4_4x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_4x4_4x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_4x4_4x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_4x4_4x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_4x4_4x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x2_2x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x2_2x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x2_2x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_8x2_2x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_32x4 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_32x4 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_32x4 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_32x4_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_4x4_8ch | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_4x4_8ch | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_4x4_8ch | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmac_elem_32 | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32_2 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32_2 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32_2 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32_2 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_2_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmac_elem_32_32b | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmac_elem_32_32b | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmac_elem_32_32b | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmac_elem_32_32b_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmac_elem_32_conf | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| signed short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| signed short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmac_elem_32_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmac_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_4x4_4x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_4x4_4x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_4x4_4x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_4x4_4x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x2_2x8 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x2_2x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x2_2x8 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_8x2_2x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_32x4 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_32x4 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_32x4 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_32x4_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32accfloat addmsc_elem_32 | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32 | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32_2 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32_2 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32_2 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32_2 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_2_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmsc_elem_32_32b | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmsc_elem_32_32b | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmsc_elem_32_32b | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc32 addmsc_elem_32_32b_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc1, | ||
| v32acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32accfloat addmsc_elem_32_conf | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc1, | ||
| v32accfloat | acc2, | ||
| int | zero_acc1, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| signed short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| signed short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 addmsc_elem_32_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc1, | ||
| v32acc64 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64 | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v64acc32 addmsc_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc1, | ||
| v64acc32 | acc2, | ||
| int | zero_acc1, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1, | ||
| int | sub_acc2 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_4x4_4x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_8x2_2x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_32x4_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat mac_elem_32 | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc ) |
| v32acc64 mac_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_2_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 mac_elem_32_32b_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mac_elem_32_conf | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| signed short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| signed short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 mac_elem_32_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 mac_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_4x4_4x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_8x2_2x8_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_32x4_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_conv_4x4_8ch_conf | ( | v64uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc ) |
| v32accfloat msc_elem_32 | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc ) |
| v32acc64 msc_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_2_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc32 msc_elem_32_32b_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat msc_elem_32_conf | ( | v32float16 | a, |
| v32float16 | b, | ||
| v32accfloat | acc, | ||
| int | zero_acc, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| signed short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32int16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| signed short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| unsigned short | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32int16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| int | sgn_x, | ||
| v32uint16 | b, | ||
| int | sgn_y, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| signed short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| unsigned short | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| v32int16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32acc64 msc_elem_32_conf | ( | v32uint16 | a, |
| v32uint16 | b, | ||
| v32acc64 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64int16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64int16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| int | sgn_x, | ||
| v64uint16 | b, | ||
| int | sgn_y, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| v64int16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v64acc32 msc_elem_64_conf | ( | v64uint16 | a, |
| v64uint16 | b, | ||
| v64acc32 | acc, | ||
| int | zero_acc, | ||
| int | shift16, | ||
| int | sub_mul, | ||
| int | sub_acc1 ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| bfloat16 | b ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| float16 | b ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| v32bfloat16 | b ) |
| v32accfloat mul_elem_32 | ( | v32bfloat16 | a, |
| v32float16 | b ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| bfloat16 | b ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| float16 | b ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| v32bfloat16 | b ) |
| v32accfloat mul_elem_32 | ( | v32float16 | a, |
| v32float16 | b ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat mul_elem_32_conf | ( | v32float16 | a, |
| v32float16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| bfloat16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| float16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| v32bfloat16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32bfloat16 | a, |
| v32float16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| bfloat16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| float16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| v32bfloat16 | b ) |
| v32accfloat negmul_elem_32 | ( | v32float16 | a, |
| v32float16 | b ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| v32bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32bfloat16 | a, |
| v32float16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| float16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32bfloat16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| int | sgn_x, | ||
| v32float16 | b, | ||
| int | sgn_y, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| v32bfloat16 | b, | ||
| int | sub_mul ) |
| v32accfloat negmul_elem_32_conf | ( | v32float16 | a, |
| v32float16 | b, | ||
| int | sub_mul ) |