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  ['2_3a_2016_20bit_20complex_20by_2016_20bit_20real_20multiplication_20with_20pre_20adding_20from_20x_20and_20y_20buffers_1',['Lane selection example 2: 16 bit complex by 16 bit real multiplication with pre-adding from X and Y buffers',['../group__vect__mult__intrinsics__explained.html',1,'']]]
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