Performance and Resource Utilization for AXI DataMover v5.1

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Virtex UltraScale+

Artix-7

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a35t	cpg236	1	Atrix_default_1			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=161 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	161	1641	2134	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	1	Atrix_default_1_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=227 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	227	1654	2134	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	2	Atrix_default_2			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=194 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	194	1641	2134	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	2	Atrix_default_2_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=308 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	308	1676	2138	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	3	Atrix_default_3			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=227 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	227	1648	2134	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	3	Atrix_default_3_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=336 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	336	1664	2136	0	4	1	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	1	kintex_default_1			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=260 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	260	1655	2134	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	1	kintex_default_1_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=347 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	347	1663	2136	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	kintex_default_2			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=319 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	319	1664	2134	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	kintex_default_2_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=440 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	440	1680	2140	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	3	kintex_default_3			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=352 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	352	1666	2134	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	3	kintex_default_3_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=494 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	494	1683	2137	0	4	1	PRODUCTION 1.12 2017-02-17

Versal ACAP

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xqvp1052	sbrj1369	1MP	versal_default_config__conf_1																																		U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=599 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	599	1041	1246	0	0	1	1	PRODUCTION 2.02 2024-05-16
xqvp1052	sbrj1369	1MP	versal_default_config__conf_1_mm2s																																		U0/m_axi_mm2s_aclk=669 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	669	1059	1278	0	0	1	1	PRODUCTION 2.02 2024-05-16
xcvp1502_SE	vsva2785	2MP	versal_default_config__conf_2																																		U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=615 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	615	1027	1218	0	0	1	1	PRODUCTION 2.08 2024-04-15
xcvp1502_SE	vsva2785	2MP	versal_default_config__conf_2_mm2s																																		U0/m_axi_mm2s_aclk=735 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	735	1107	1312	0	0	1	1	PRODUCTION 2.08 2024-04-15
xqvp1202	vsra2785	1LP	versal_exdes__conf_003	Full	false	256	32	false	8	true	16	19	2	Basic	false	64	32	false	4	true	4	12	11	false	true	false	2	3	1	0	true	1	1	1	1	39	U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=566 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	566	1075	1433	0	0	4	1	PRODUCTION 2.07 2024-04-02
xqvp1202	vsra2785	1LP	versal_exdes__conf_003_mm2s	Full	false	256	32	false	8	true	16	19	2	Basic	false	64	32	false	4	true	4	12	11	false	true	false	2	3	1	0	true	1	1	1	1	39	U0/m_axi_mm2s_aclk=494 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	494	1185	1533	0	0	4	1	PRODUCTION 2.07 2024-04-02
xcvp1052_SE	vfvf1760	2LLI	versal_exdes__conf_004	Full	false	64	16	false	128	true	16	13	3	Basic	false	64	8	false	64	true	4	14	30	false	true	false	2	0	2	3	true	1	1	1	1	55	U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=582 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	582	1065	1109	0	0	2	1	PRODUCTION 2.02 2024-05-16
xcvp1052_SE	vfvf1760	2LLI	versal_exdes__conf_004_mm2s	Full	false	64	16	false	128	true	16	13	3	Basic	false	64	8	false	64	true	4	14	30	false	true	false	2	0	2	3	true	1	1	1	1	55	U0/m_axi_mm2s_aclk=538 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	538	1084	1138	0	0	2	1	PRODUCTION 2.02 2024-05-16
xcvp1402_SE	vfvf1760	2MP	versal_exdes__conf_005	Basic	false	32	32	false	32	true	4	18	24	Basic	false	64	8	false	8	true	4	22	4	false	false	false	3	1	1	0	false	1	1	1	1	39	U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=779 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	779	625	763	0	0	0	0	PRODUCTION 2.03 2024-03-31
xcvp1402_SE	vfvf1760	2MP	versal_exdes__conf_005_mm2s	Basic	false	32	32	false	32	true	4	18	24	Basic	false	64	8	false	8	true	4	22	4	false	false	false	3	1	1	0	false	1	1	1	1	39	U0/m_axi_mm2s_aclk=774 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	774	586	767	0	0	0	0	PRODUCTION 2.03 2024-03-31
xqvp1702	vsra3340	2MP	versal_exdes__conf_006	Full	false	64	64	true	64	true	8	22	9	Full	false	128	128	false	16	true	16	22	2	false	false	true	1	0	3	3	false	1	1	1	1	36	U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=610 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	610	1820	2571	0	0	2	0	PRODUCTION 2.08 2024-04-16
xqvp1702	vsra3340	2MP	versal_exdes__conf_006_mm2s	Full	false	64	64	true	64	true	8	22	9	Full	false	128	128	false	16	true	16	22	2	false	false	true	1	0	3	3	false	1	1	1	1	36	U0/m_axi_mm2s_aclk=610 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	610	1927	2677	0	0	2	0	PRODUCTION 2.08 2024-04-16
xcvc1802	viva1596	1MP	versal_exdes__conf_007	Full	false	32	32	false	128	true	1	10	5	Full	false	32	32	false	64	true	4	23	22	true	false	false	1	0	7	64	false	1	1	1	1	50	U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=560 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	560	1416	1791	0	0	2	1	PRODUCTION 2.15 2026-03-17
xcvc1802	viva1596	1MP	versal_exdes__conf_007_mm2s	Full	false	32	32	false	128	true	1	10	5	Full	false	32	32	false	64	true	4	23	22	true	false	false	1	0	7	64	false	1	1	1	1	50	U0/m_axi_mm2s_aclk=680 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	680	1536	1894	0	0	2	1	PRODUCTION 2.15 2026-03-17

Virtex-7

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7v585t	ffg1157	1	virtex_default_1			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=249 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	249	1654	2134	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	1	virtex_default_1_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=363 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	363	1668	2136	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	2	virtex_default_2			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=330 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	330	1667	2134	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	2	virtex_default_2_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=435 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	435	1682	2138	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	3	virtex_default_3			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=358 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	358	1665	2134	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	3	virtex_default_3_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=478 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	478	1678	2140	0	4	1	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu440	flgb2377	1	virtexus_2			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=303 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	303	1677	2133	0	4	1	PRODUCTION 1.26 12-04-2018
xcvu440	flgb2377	1	virtexus_2_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=424 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	424	1735	2166	0	4	1	PRODUCTION 1.26 12-04-2018
xcvu440	flgb2377	2	virtexus_3			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=363 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	363	1676	2133	0	4	1	PRODUCTION 1.26 12-04-2018
xcvu440	flgb2377	2	virtexus_3_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=500 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	500	1716	2137	0	4	1	PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu13p	fsga2577	3	virtexuplus_1			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=582 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	582	1722	2134	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	2	virtexuplus_2			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=549 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	549	1705	2133	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	2	virtexuplus_2_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=713 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	713	1765	2167	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	1	virtexuplus_3			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=450 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	450	1689	2133	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	1	virtexuplus_3_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=631 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	631	1773	2173	0	4	1	PRODUCTION 1.28 03-30-2022

Virtex UltraScale+

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcu50	fsvh2104	3	virtexuplusHBM_default			128	128									128	128																				U0/m_axi_mm2s_aclk=100 U0/m_axi_s2mm_aclk=555 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	555	1685	2133	0	4	1	PRODUCTION 1.30 05-01-2022
xcu50	fsvh2104	3	virtexuplusHBM_default_mm2s			128	128									128	128																				U0/m_axi_mm2s_aclk=752 U0/m_axi_s2mm_aclk=100 U0/m_axis_mm2s_cmdsts_aclk=100 U0/m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	752	1716	2133	0	4	1	PRODUCTION 1.30 05-01-2022

COPYRIGHT

Copyright 2026 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.