Performance and Resource Utilization for AXI DataMover v5.1

Vivado Design Suite Release 2025.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2025.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Virtex UltraScale+

Artix-7

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a35t	cpg236	1	Atrix_default_1			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	161	1602	2115	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	1	Atrix_default_1_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	243	1618	2115	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	2	Atrix_default_2			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	194	1601	2115	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	2	Atrix_default_2_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	303	1625	2116	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	3	Atrix_default_3			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	232	1603	2115	0	4	1	PRODUCTION 1.23 2018-06-13
xc7a35t	cpg236	3	Atrix_default_3_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	336	1631	2116	0	4	1	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	1	kintex_default_1			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	265	1611	2115	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	1	kintex_default_1_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	352	1624	2117	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	kintex_default_2			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	319	1627	2115	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	kintex_default_2_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	440	1629	2115	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	3	kintex_default_3			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	347	1629	2115	0	4	1	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	3	kintex_default_3_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	461	1634	2115	0	4	1	PRODUCTION 1.12 2017-02-17

Versal ACAP

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xqvp1052	sbrj1369	1MP	versal_default_config__conf_1																																		m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	571	984	1213	0	0	1	1	PRODUCTION 2.02 2024-05-16
xqvp1052	sbrj1369	1MP	versal_default_config__conf_1_mm2s																																		m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	697	974	1234	0	0	1	1	PRODUCTION 2.02 2024-05-16
xcvp1502_SE	vsva2785	2MP	versal_default_config__conf_2																																		m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	631	983	1216	0	0	1	1	PRODUCTION 2.08 2024-04-15
xcvp1502_SE	vsva2785	2MP	versal_default_config__conf_2_mm2s																																		m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	664	989	1197	0	0	1	1	PRODUCTION 2.08 2024-04-15
xqvp1202	vsra2785	1LP	versal_exdes__conf_003	Full	false	256	32	false	8	true	16	19	2	Basic	false	64	32	false	4	true	4	12	11	false	true	false	2	3	1	0	1	1	1	1	1	39	m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	538	1029	1395	0	0	4	1	PRODUCTION 2.07 2024-04-02
xqvp1202	vsra2785	1LP	versal_exdes__conf_003_mm2s	Full	false	256	32	false	8	true	16	19	2	Basic	false	64	32	false	4	true	4	12	11	false	true	false	2	3	1	0	1	1	1	1	1	39	m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	402	1029	1385	0	0	4	1	PRODUCTION 2.07 2024-04-02
xcvp1052_SE	vfvf1760	2LLI	versal_exdes__conf_004	Full	false	64	16	false	128	true	16	13	3	Basic	false	64	8	false	64	true	4	14	30	false	true	false	2	0	2	3	1	1	1	1	1	55	m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	544	926	971	0	0	2	1	PRODUCTION 2.02 2024-05-16
xcvp1052_SE	vfvf1760	2LLI	versal_exdes__conf_004_mm2s	Full	false	64	16	false	128	true	16	13	3	Basic	false	64	8	false	64	true	4	14	30	false	true	false	2	0	2	3	1	1	1	1	1	55	m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	505	954	1019	0	0	2	1	PRODUCTION 2.02 2024-05-16
xcvp1402_SE	vfvf1760	2MP	versal_exdes__conf_005	Basic	false	32	32	false	32	true	4	18	24	Basic	false	64	8	false	8	true	4	22	4	false	false	false	3	1	1	0	0	1	1	1	1	39	m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	757	530	747	0	0	0	0	PRODUCTION 2.03 2024-03-31
xcvp1402_SE	vfvf1760	2MP	versal_exdes__conf_005_mm2s	Basic	false	32	32	false	32	true	4	18	24	Basic	false	64	8	false	8	true	4	22	4	false	false	false	3	1	1	0	0	1	1	1	1	39	m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	768	547	702	0	0	0	0	PRODUCTION 2.03 2024-03-31
xqvp1702	vsra3340	2MP	versal_exdes__conf_006	Full	false	64	64	true	64	true	8	22	9	Full	false	128	128	false	16	true	16	22	2	false	false	true	1	0	3	3	0	1	1	1	1	36	m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	549	1749	2499	0	0	2	0	PRODUCTION 2.08 2024-04-16
xqvp1702	vsra3340	2MP	versal_exdes__conf_006_mm2s	Full	false	64	64	true	64	true	8	22	9	Full	false	128	128	false	16	true	16	22	2	false	false	true	1	0	3	3	0	1	1	1	1	36	m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	647	1829	2527	0	0	2	0	PRODUCTION 2.08 2024-04-16
xcvc1802	viva1596	1MP	versal_exdes__conf_007	Full	false	32	32	false	128	true	1	10	5	Full	false	32	32	false	64	true	4	23	22	true	false	false	1	0	7	64	0	1	1	1	1	50	m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	549	1359	1776	0	0	2	1	PRODUCTION 2.14 2025-03-24
xcvc1802	viva1596	1MP	versal_exdes__conf_007_mm2s	Full	false	32	32	false	128	true	1	10	5	Full	false	32	32	false	64	true	4	23	22	true	false	false	1	0	7	64	0	1	1	1	1	50	m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	675	1384	1715	0	0	2	1	PRODUCTION 2.14 2025-03-24

Virtex-7

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7v585t	ffg1157	1	virtex_default_1			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	254	1611	2115	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	1	virtex_default_1_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	391	1642	2115	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	2	virtex_default_2			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	330	1628	2115	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	2	virtex_default_2_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	440	1632	2118	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	3	virtex_default_3			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	358	1632	2115	0	4	1	PRODUCTION 1.12 2014-09-11
xc7v585t	ffg1157	3	virtex_default_3_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	494	1647	2115	0	4	1	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu440	flgb2377	1	virtexus_2			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	292	1626	2115	0	4	1	PRODUCTION 1.26 12-04-2018
xcvu440	flgb2377	1	virtexus_2_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	429	1690	2116	0	4	1	PRODUCTION 1.26 12-04-2018
xcvu440	flgb2377	2	virtexus_3			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	347	1633	2114	0	4	1	PRODUCTION 1.26 12-04-2018
xcvu440	flgb2377	2	virtexus_3_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	538	1672	2115	0	4	1	PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu13p	fsga2577	3	virtexuplus_1			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	555	1644	2113	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	2	virtexuplus_2			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	533	1642	2113	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	2	virtexuplus_2_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	730	1665	2114	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	1	virtexuplus_3			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	467	1647	2113	0	4	1	PRODUCTION 1.28 03-30-2022
xcvu13p	fsga2577	1	virtexuplus_3_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	636	1661	2113	0	4	1	PRODUCTION 1.28 03-30-2022

Virtex UltraScale+

Part Information			Configuration Parameters																																			Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_mm2s	c_mm2s_stscmd_is_async	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_mm2s_stsfifo	c_mm2s_stscmd_fifo_depth	c_mm2s_btt_used	c_mm2s_addr_pipe_depth	c_include_s2mm	c_s2mm_stscmd_is_async	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_include_s2mm_stsfifo	c_s2mm_stscmd_fifo_depth	c_s2mm_btt_used	c_s2mm_addr_pipe_depth	c_s2mm_support_indet_btt	c_mm2s_include_sf	c_s2mm_include_sf	c_m_axi_mm2s_id_width	c_m_axi_mm2s_arid	c_m_axi_s2mm_id_width	c_m_axi_s2mm_awid	c_enable_cache_user	c_enable_mm2s	c_enable_s2mm	c_enable_mm2s_adv_sig	c_enable_s2mm_adv_sig	c_addr_width	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcu50	fsvh2104	3	virtexuplusHBM_default			128	128									128	128																				m_axi_mm2s_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_s2mm_aclk	588	1666	2113	0	4	1	PRODUCTION 1.30 05-01-2022
xcu50	fsvh2104	3	virtexuplusHBM_default_mm2s			128	128									128	128																				m_axi_s2mm_aclk=100 m_axis_mm2s_cmdsts_aclk=100 m_axis_s2mm_cmdsts_awclk=100	m_axi_mm2s_aclk	779	1672	2114	0	4	1	PRODUCTION 1.30 05-01-2022

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