Performance and Resource Utilization for AXI to LMB Bridge v1.0

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Kintex UltraScale
Versal ACAP
Virtex-7
Virtex UltraScale

Artix-7

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	fbg676	-3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	556	587	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1037	1057	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	828	925	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	636	715	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Default									U0/Clk=307	Clk	307	914	881	0	0	0	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	-3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	556	587	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1037	1057	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	828	925	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	636	715	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Default									U0/Clk=469	Clk	469	928	882	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	554	587	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1037	1057	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	717	923	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	634	715	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Default									U0/Clk=569	Clk	569	916	881	0	0	0	PRODUCTION 1.25 12-04-2018

Versal ACAP

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	3HP	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	531	597	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	3HP	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1015	1068	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	3HP	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	806	924	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	3HP	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	627	725	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	3HP	Default									U0/Clk=763	Clk	763	990	1053	0	0	0	0	PRODUCTION 2.15 2026-03-17

Virtex-7

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1761	-3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	556	587	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1037	1057	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	828	925	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	636	715	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Default									U0/Clk=444	Clk	444	925	881	0	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	554	587	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1037	1057	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	717	923	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	634	715	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Default									U0/Clk=575	Clk	575	925	881	0	0	0	PRODUCTION 1.27 12-04-2018

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