Performance and Resource Utilization for AXI to LMB Bridge v1.0

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2024.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Kintex UltraScale
Versal ACAP
Virtex-7
Virtex UltraScale

Artix-7

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	fbg676	-3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	463	587	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1026	1057	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	653	924	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	527	715	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	-3	Default									none	Clk	338	953	879	0	0	0	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	-3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	463	587	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1025	1057	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	653	924	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	527	715	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	Default									none	Clk	475	962	879	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	476	587	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1015	1057	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	721	923	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	556	715	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	3	Default									none	Clk	602	916	882	0	0	0	PRODUCTION 1.25 12-04-2018

Versal ACAP

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	3HP	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	514	588	0	0	0	0	PRODUCTION 2.13 2024-03-28
xcvc1902	vsva2197	3HP	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1017	1059	0	0	0	0	PRODUCTION 2.13 2024-03-28
xcvc1902	vsva2197	3HP	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	785	923	0	0	0	0	PRODUCTION 2.13 2024-03-28
xcvc1902	vsva2197	3HP	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	591	716	0	0	0	0	PRODUCTION 2.13 2024-03-28
xcvc1902	vsva2197	3HP	Default									none	Clk	719	866	980	0	0	0	0	PRODUCTION 2.13 2024-03-28

Virtex-7

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1761	-3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	463	587	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1025	1057	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	653	924	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	527	715	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1761	-3	Default									none	Clk	457	959	883	0	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters										Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_DATA_WIDTH	C_ADDR_WIDTH	C_AXI_AW_DEPTH	C_AXI_W_DEPTH	C_AXI_AR_DEPTH	C_AXI_R_DEPTH	C_AXI_ID_WIDTH	C_USE_PAUSE	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	3	Configuration 01	32	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	476	587	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Configuration 02	32	32	4	8	4	8	0	0	Clk=100	N/A	NOT FOUND	1015	1057	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Configuration 03	64	32	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	721	923	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Configuration 04	32	64	2	4	2	4	0	0	Clk=100	N/A	NOT FOUND	555	715	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	Default									none	Clk	556	911	881	0	0	0	PRODUCTION 1.27 12-04-2018

COPYRIGHT

Copyright 2024 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.