Performance and Resource Utilization for AXI Multi Channel Direct Memory Access v1.2

Vivado Design Suite Release 2025.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2025.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex UltraScale+
Versal ACAP
Zynq UltraScale+

Kintex UltraScale+

Part Information			Configuration Parameters																																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_sg	c_num_mm2s_channels	c_num_s2mm_channels	c_sg_length_width	c_prmry_is_aclk_async	c_sg_include_stscntrl_strm	c_include_mm2s	c_mm2s_scheduler	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_s2mm	C_ENABLE_MULTI_CH_RESET	c_sg_use_stsapp_length	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_addr_width	c_enable_multi_intr	c_tst_vec	c_group1_mm2s	c_group2_mm2s	c_group3_mm2s	c_group4_mm2s	c_group5_mm2s	c_group6_mm2s	c_group1_s2mm	c_group2_s2mm	c_group3_s2mm	c_group4_s2mm	c_group5_s2mm	c_group6_s2mm	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffve1517	2	uplus_epr_2_with_mch_rst		8	8		0				128	128				1		128	128																		s_axi_lite_aclk=100	s_axi_aclk	444	8556	10312	0	6	5	PRODUCTION 1.29 05-01-2022
xcku11p	ffve1517	2	uplus_epr_2_without_mch_rst		8	8		0				128	128				0		128	128																		s_axi_lite_aclk=100	s_axi_aclk	513	8129	9808	0	6	5	PRODUCTION 1.29 05-01-2022
xqku15p	ffra1156	1	with_multi_rst_kintexuplus__conf_1	1	16	16	8	0	1	1	3	32	8	0	8	1	1	1	128	32	1	8	64	1	0	0010100100111001	1101010010000110	0000000000000000	0000001000000000	0000000000000000	0000000001000000	0110010010001001	0001001001110010	0000100000000100	0000000000000000	0000000000000000	1000000100000000	s_axi_lite_aclk=100	s_axi_aclk	375	17493	19069	0	5	2	PRODUCTION 1.29 05-01-2022
xqku15p	ffra1156	1	without_mch_rst_kintexuplus__conf_1	1	16	16	8	0	1	1	3	32	8	0	8	1	0	1	128	32	1	8	64	1	0	0010100100111001	1101010010000110	0000000000000000	0000001000000000	0000000000000000	0000000001000000	0110010010001001	0001001001110010	0000100000000100	0000000000000000	0000000000000000	1000000100000000	s_axi_lite_aclk=100	s_axi_aclk	363	16553	18373	0	5	2	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters																																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_sg	c_num_mm2s_channels	c_num_s2mm_channels	c_sg_length_width	c_prmry_is_aclk_async	c_sg_include_stscntrl_strm	c_include_mm2s	c_mm2s_scheduler	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_s2mm	C_ENABLE_MULTI_CH_RESET	c_sg_use_stsapp_length	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_addr_width	c_enable_multi_intr	c_tst_vec	c_group1_mm2s	c_group2_mm2s	c_group3_mm2s	c_group4_mm2s	c_group5_mm2s	c_group6_mm2s	c_group1_s2mm	c_group2_s2mm	c_group3_s2mm	c_group4_s2mm	c_group5_s2mm	c_group6_s2mm	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	versal_epr_1LP_with_mch_rst		8	8		0				128	128				1		128	128																		s_axi_lite_aclk=100	s_axi_aclk	357	8665	10727	0	0	6	5	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	1LP	versal_epr_1LP_without_mch_rst		8	8		0				128	128				0		128	128																		s_axi_lite_aclk=100	s_axi_aclk	375	8181	9986	0	0	6	5	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	2MP	versal_epr_2MP_with_mch_rst		8	8		0				128	128				1		128	128																		s_axi_lite_aclk=100	s_axi_aclk	469	8917	10786	0	0	6	5	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	2MP	versal_epr_2MP_without_mch_rst		8	8		0				128	128				0		128	128																		s_axi_lite_aclk=100	s_axi_aclk	500	8357	10195	0	0	6	5	PRODUCTION 2.14 2025-03-24

Zynq UltraScale+

Part Information			Configuration Parameters																																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	c_include_sg	c_num_mm2s_channels	c_num_s2mm_channels	c_sg_length_width	c_prmry_is_aclk_async	c_sg_include_stscntrl_strm	c_include_mm2s	c_mm2s_scheduler	c_m_axi_mm2s_data_width	c_m_axis_mm2s_tdata_width	c_include_mm2s_dre	c_mm2s_burst_size	c_include_s2mm	C_ENABLE_MULTI_CH_RESET	c_sg_use_stsapp_length	c_m_axi_s2mm_data_width	c_s_axis_s2mm_tdata_width	c_include_s2mm_dre	c_s2mm_burst_size	c_addr_width	c_enable_multi_intr	c_tst_vec	c_group1_mm2s	c_group2_mm2s	c_group3_mm2s	c_group4_mm2s	c_group5_mm2s	c_group6_mm2s	c_group1_s2mm	c_group2_s2mm	c_group3_s2mm	c_group4_s2mm	c_group5_s2mm	c_group6_s2mm	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	uplus_epr_1LV_with_mch_rst		8	8		0				128	128				1		128	128																		s_axi_lite_aclk=100	s_axi_aclk	325	8496	10312	0	6	5	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	uplus_epr_1LV_without_mch_rst		8	8		0				128	128				0		128	128																		s_axi_lite_aclk=100	s_axi_aclk	332	7957	9804	0	6	5	PRODUCTION 1.30 05-15-2022

COPYRIGHT

Copyright 2025 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.