Resource Utilization for AXI Bridge for PCI Express Gen3 Subsystem v3.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 ffva1156 2 xcku040_ffva1156_2_x1g1 X1 2.5_GT/s refclk=100 sys_clk_gt=100 3132 3180 0 7 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x1g2 X1 5.0_GT/s refclk=100 sys_clk_gt=100 3128 3282 0 7 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x1g3 X1 8.0_GT/s refclk=100 sys_clk_gt=100 3127 3314 0 7 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x2g1 X2 2.5_GT/s refclk=100 sys_clk_gt=100 3198 3341 0 7 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x2g2 X2 5.0_GT/s refclk=100 sys_clk_gt=100 3197 3522 0 7 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x2g3 X2 8.0_GT/s refclk=100 sys_clk_gt=100 3785 4681 0 11 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x4g1 X4 2.5_GT/s refclk=100 sys_clk_gt=100 3338 3663 0 7 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x4g2 X4 5.0_GT/s refclk=100 sys_clk_gt=100 3613 4355 0 11 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x4g3 X4 8.0_GT/s refclk=100 sys_clk_gt=100 4771 6608 0 19 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x8g1 X8 2.5_GT/s refclk=100 sys_clk_gt=100 3873 4660 0 11 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x8g2 X8 5.0_GT/s refclk=100 sys_clk_gt=100 4468 5960 0 19 12 PRODUCTION 1.25 12-04-2018
xcku040 ffva1156 2 xcku040_ffva1156_2_x8g3 X8 8.0_GT/s refclk=100 sys_clk_gt=100 4505 6216 0 19 12 PRODUCTION 1.25 12-04-2018

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1761 2 fcsvrg1x1xc7vx690tffg17611_0 X1 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 3872 3525 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg1x2xc7vx690tffg17611_0 X2 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4231 3930 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg1x4xc7vx690tffg17611_0 X4 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4963 4740 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg1x8xc7vx690tffg17611_0 X8 2.5_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 6654 6785 0 15 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg2x1xc7vx690tffg17611_0 X1 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 3874 3525 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg2x2xc7vx690tffg17611_0 X2 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4234 3930 0 11 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg2x4xc7vx690tffg17611_0 X4 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5104 5089 0 15 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg2x8xc7vx690tffg17611_0 X8 5.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7204 7440 0 23 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg3x1xc7vx690tffg17611_0 X1 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 3810 3521 0 7 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg3x2xc7vx690tffg17611_0 X2 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 4360 4269 0 11 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg3x4xc7vx690tffg17611_0 X4 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 5735 5726 0 19 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 2 fcsvrg3x8xc7vx690tffg17611_0 X8 8.0_GT/s DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 refclk=100 7316 7441 0 19 12 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 2 pcie3_xcvu09566180_x1g1 X1 2.5_GT/s refclk=100 sys_clk_gt=100 3131 3180 0 7 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x1g2 X1 5.0_GT/s refclk=100 sys_clk_gt=100 3129 3282 0 7 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x1g3 X1 8.0_GT/s refclk=100 sys_clk_gt=100 3127 3314 0 7 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x2g1 X2 2.5_GT/s refclk=100 sys_clk_gt=100 3203 3341 0 7 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x2g2 X2 5.0_GT/s refclk=100 sys_clk_gt=100 3203 3522 0 7 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x2g3 X2 8.0_GT/s refclk=100 sys_clk_gt=100 3783 4681 0 11 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x4g1 X4 2.5_GT/s refclk=100 sys_clk_gt=100 3335 3663 0 7 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x4g2 X4 5.0_GT/s refclk=100 sys_clk_gt=100 3608 4355 0 11 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x4g3 X4 8.0_GT/s refclk=100 sys_clk_gt=100 4770 6608 0 19 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x8g1 X8 2.5_GT/s refclk=100 sys_clk_gt=100 3877 4660 0 11 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x8g2 X8 5.0_GT/s refclk=100 sys_clk_gt=100 4463 5960 0 19 12 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 pcie3_xcvu09566180_x8g3 X8 8.0_GT/s refclk=100 sys_clk_gt=100 4502 6216 0 19 12 PRODUCTION 1.26 12-04-2018

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