Performance and Resource Utilization for AXI Protocol Converter v2.1

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2024.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Kintex UltraScale
Kintex UltraScale+
Zynq UltraScale+

Artix-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	fbg676	2	axi3_7a2	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	288	406	448	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	2	axi3_7a2_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	365	61	125	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	2	axi4lite_7a2	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	294	530	560	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	2	axi4lite_7a2_0	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	568	35	12	0	0	0	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	2	axi3_7k2	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	419	413	448	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	axi3_7k2_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	528	58	123	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	axi4lite_7k2	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	407	526	560	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	axi4lite_7k2_1	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	873	34	11	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	2	axi3_ku040	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	469	409	450	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	2	axi3_ku040_1	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	639	61	123	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	2	axi4lite_ku040	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	488	536	556	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	2	axi4lite_ku040_1	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	1157	34	9	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku5p	ffvb676	2	axi3_ku5p	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	732	426	448	0	0	0	PRODUCTION 1.29 05-01-2022
xcku5p	ffvb676	2	axi3_ku5p_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	934	61	123	0	0	0	PRODUCTION 1.29 05-01-2022
xcku5p	ffvb676	2	axi4lite_ku5p	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	769	582	556	0	0	0	PRODUCTION 1.29 05-01-2022
xcku5p	ffvb676	2	axi4lite_ku5p_0	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	1220	34	9	0	0	0	PRODUCTION 1.29 05-01-2022

Zynq UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	2	axi3_7z2_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	913	59	123	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	axi3_7zu	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	750	429	449	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	axi4lite_7z2_0	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	1431	35	13	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	axi4lite_7zu	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	732	584	559	0	0	0	PRODUCTION 1.30 05-15-2022

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