Resource Utilization for Block Memory Generator v8.4

Vivado Design Suite Release 2024.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
Interface_Type
AXI_Type
AXI_Slave_Type
Memory_Type
Use_Byte_Write_Enable
Byte_Size
Algorithm
Primitive
Assume_Synchronous_Clk
Write_Width_A
Write_Depth_A
Read_Width_A
Operating_Mode_A
Enable_A
Write_Width_B
Read_Width_B
Operating_Mode_B
Enable_B
Register_PortA_Output_of_Memory_Primitives
Register_PortA_Output_of_Memory_Core
Register_PortB_Output_of_Memory_Primitives
Register_PortB_Output_of_Memory_Core
Fill_Remaining_Memory_Locations
Remaining_Memory_Locations
Use_RSTA_Pin
Output_Reset_Value_A
Use_RSTB_Pin
Output_Reset_Value_B
Collision_Warnings
use_bram_block
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx1140t flg1928 2 bmg_conf_1 Native AXI4_Full Memory_Slave True_Dual_Port_RAM false 9 Minimum_Area 8kx2 false 36 512 36 WRITE_FIRST Use_ENA_Pin 36 36 WRITE_FIRST Use_ENB_Pin false false false false false 0 true 0 true 0 ALL Stand_Alone clka=50 clkb=50 10 12 0 1 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_10 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 34 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Always_Enabled false false false false false 0 true 0 false 0 ALL Stand_Alone clka=50 40 8 0 3 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_11 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Fixed_Primitives 1kx18 false 17 5120 34 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Always_Enabled false false false false false 0 true 0 false 0 ALL Stand_Alone clka=50 41 8 0 3 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_12 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Low_Power 8kx2 false 17 5120 34 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Always_Enabled false false false false false 0 true 0 false 0 ALL Stand_Alone clka=50 41 8 0 3 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_13 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Minimum_Area 8kx2 false 36 4096 36 WRITE_FIRST Use_ENA_Pin 36 36 WRITE_FIRST Always_Enabled false false false false false 0 true 0 false 0 ALL Stand_Alone clka=50 5 6 0 4 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_14 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Fixed_Primitives 512x36 false 36 4096 36 WRITE_FIRST Use_ENA_Pin 36 36 WRITE_FIRST Always_Enabled false false false false false 0 true 0 false 0 ALL Stand_Alone clka=50 43 8 0 4 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_16 AXI4 AXI4_Full Memory_Slave Simple_Dual_Port_RAM true 8 Minimum_Area 8kx2 true 32 1024 32 READ_FIRST Use_ENA_Pin 32 32 READ_FIRST Use_ENB_Pin false false false false false 0 0 0 ALL Stand_Alone s_aclk=50 168 103 0 1 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_17 AXI4 AXI4_Full Memory_Slave Simple_Dual_Port_RAM true 8 Minimum_Area 8kx2 true 64 512 64 READ_FIRST Use_ENA_Pin 64 64 READ_FIRST Use_ENB_Pin false false false false false 0 0 0 ALL Stand_Alone s_aclk=50 185 106 0 1 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_18 AXI4 AXI4_Full Peripheral_Slave Simple_Dual_Port_RAM true 8 Minimum_Area 8kx2 true 32 1024 32 READ_FIRST Use_ENA_Pin 32 32 READ_FIRST Use_ENB_Pin false false false false false 0 0 0 ALL Stand_Alone s_aclk=50 103 59 0 1 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_19 AXI4 AXI4_Full Peripheral_Slave Simple_Dual_Port_RAM true 8 Minimum_Area 8kx2 true 64 512 64 READ_FIRST Use_ENA_Pin 64 64 READ_FIRST Use_ENB_Pin false false false false false 0 0 0 ALL Stand_Alone s_aclk=50 104 57 0 1 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_2 Native AXI4_Full Memory_Slave True_Dual_Port_RAM false 9 Minimum_Area 8kx2 false 36 512 36 WRITE_FIRST Use_ENA_Pin 36 36 WRITE_FIRST Use_ENB_Pin true false true false false 0 true 0 true 0 ALL Stand_Alone clka=50 clkb=50 10 12 0 1 0 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_3 Native AXI4_Full Memory_Slave True_Dual_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Use_ENB_Pin false false false false false 0 true 0 true 0 ALL Stand_Alone clka=50 clkb=50 48 18 0 2 1 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_4 Native AXI4_Full Memory_Slave True_Dual_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Use_ENB_Pin true false true false false 0 true 0 true 0 ALL Stand_Alone clka=50 clkb=50 50 24 0 2 1 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_5 Native AXI4_Full Memory_Slave True_Dual_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Use_ENB_Pin false true false true false 0 true 0 true 0 ALL Stand_Alone clka=50 clkb=50 40 40 0 2 1 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_6 Native AXI4_Full Memory_Slave True_Dual_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Use_ENB_Pin true true true true false 0 true 0 true 0 ALL Stand_Alone clka=50 clkb=50 36 46 0 2 1 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_7 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Always_Enabled true false false false false 0 true 0 false 0 ALL Stand_Alone clka=50 25 12 0 2 1 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_8 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Always_Enabled false true false false false 0 true 0 false 0 ALL Stand_Alone clka=50 20 20 0 2 1 PRODUCTION 1.11 2014-09-11
xc7vx1140t flg1928 2 bmg_conf_9 Native AXI4_Full Memory_Slave Single_Port_RAM false 9 Minimum_Area 8kx2 false 17 5120 17 WRITE_FIRST Use_ENA_Pin 17 17 WRITE_FIRST Always_Enabled true true false false false 0 true 0 false 0 ALL Stand_Alone clka=50 18 23 0 2 1 PRODUCTION 1.11 2014-09-11

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