Performance and Resource Utilization for Binary Counter v12.0

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=636	CLK	636	160	270	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=636	CLK	636	209	530	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=319	CLK	319	212	357	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=768	CLK	768	21	29	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=691	CLK	691	22	31	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=636	CLK	636	25	73	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=544	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=544	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=380	CLK	380	10	0	1	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=702	CLK	702	177	270	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=658	CLK	658	208	494	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=380	CLK	380	212	355	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=997	CLK	997	21	30	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=735	CLK	735	22	31	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=702	CLK	702	25	73	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=675	CLK	675	0	0	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=631	CLK	631	0	0	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=472	CLK	472	10	0	1	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=872	CLK	872	175	270	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=872	CLK	872	208	558	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=577	CLK	577	212	357	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=1418	CLK	1419	23	29	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=1140	CLK	1140	22	30	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=1025	CLK	1025	25	73	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=833	CLK	833	0	0	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=833	CLK	833	0	0	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=664	CLK	664	10	0	1	0	0	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=697	CLK	697	222	277	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=658	CLK	658	299	570	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=577	CLK	577	286	393	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=708	CLK	708	21	30	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=811	CLK	811	22	30	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=790	CLK	790	49	73	0	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=680	CLK	680	0	0	1	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=680	CLK	680	0	0	1	0	0	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=402	CLK	402	11	0	1	0	0	0	PRODUCTION 2.15 2026-03-17

Virtex-7

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=636	CLK	636	160	270	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=636	CLK	636	209	526	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=308	CLK	308	212	339	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=790	CLK	790	22	29	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=730	CLK	730	22	31	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=642	CLK	642	25	74	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=544	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=544	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=385	CLK	385	10	0	1	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=680	CLK	680	176	270	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=647	CLK	647	208	494	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=369	CLK	369	212	357	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=965	CLK	965	22	29	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=697	CLK	697	22	31	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=702	CLK	702	25	73	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=675	CLK	675	0	0	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=631	CLK	631	0	0	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=467	CLK	467	10	0	1	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=872	CLK	872	177	270	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=861	CLK	861	208	560	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=571	CLK	571	212	357	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=1211	CLK	1211	17	29	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=1149	CLK	1150	22	30	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=1047	CLK	1047	25	73	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=833	CLK	833	0	0	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=833	CLK	833	0	0	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=647	CLK	647	10	0	1	0	0	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Implementation	Output_Width	Restrict_Count	Final_Count_Value	Count_Mode	Load	Latency	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_128_lut	Fabric	128	false	1	UP	false	8	U0/CLK=636	CLK	636	176	270	0	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_128_lut_ld	Fabric	128	false	1	UP	true	8	U0/CLK=636	CLK	636	209	494	0	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_128_lut_rc	Fabric	128	true	5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A	UP	false	8	U0/CLK=456	CLK	456	212	357	0	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_18_lut	Fabric	18	false	1	UP	false	2	U0/CLK=1041	CLK	1041	21	29	0	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_18_lut_updown	Fabric	18	false	1	UPDOWN	false	2	U0/CLK=828	CLK	828	22	30	0	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_47_lut	Fabric	47	false	1	UP	false	2	U0/CLK=790	CLK	790	25	73	0	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_48_dsp	DSP48	48	false	1	UP	false	2	U0/CLK=768	CLK	768	0	0	1	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_48_dsp_ld	DSP48	48	false	1	UP	true	2	U0/CLK=768	CLK	768	0	0	1	0	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_48_dsp_rc	DSP48	48	true	05fd2624c	UP	false	2	U0/CLK=450	CLK	450	10	0	1	0	0	PRODUCTION 1.31 12-08-2025

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