Performance and Resource Utilization for Binary Counter v12.0

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 615 209 516 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 341 211 347 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_18_lut Fabric 18 false 1 UP false 2 CLK 768 21 29 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 691 22 31 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_47_lut Fabric 47 false 1 UP false 2 CLK 636 25 73 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 380 10 0 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_128_lut Fabric 128 false 1 UP false 8 CLK 675 174 270 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 642 209 498 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 358 211 357 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_18_lut Fabric 18 false 1 UP false 2 CLK 997 21 30 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 724 22 30 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_47_lut Fabric 47 false 1 UP false 2 CLK 741 25 74 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 489 10 0 1 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 176 270 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 577 211 357 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1397 20 29 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1150 22 30 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1030 25 73 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 669 10 0 1 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_128_lut Fabric 128 false 1 UP false 8 CLK 680 222 375 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 664 264 552 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 533 277 393 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_18_lut Fabric 18 false 1 UP false 2 CLK 680 22 29 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 680 22 30 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 49 73 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_48_dsp DSP48 48 false 1 UP false 2 CLK 680 0 0 1 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 680 0 0 1 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 461 10 0 1 0 0 0 PRODUCTION 2.13 2024-03-28

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 516 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 341 211 343 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_18_lut Fabric 18 false 1 UP false 2 CLK 790 22 29 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 730 22 31 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_47_lut Fabric 47 false 1 UP false 2 CLK 642 25 74 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 385 10 0 1 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_128_lut Fabric 128 false 1 UP false 8 CLK 691 176 270 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 669 209 494 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 380 211 357 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_18_lut Fabric 18 false 1 UP false 2 CLK 1063 20 29 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 697 22 31 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_47_lut Fabric 47 false 1 UP false 2 CLK 708 25 73 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 472 10 0 1 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 175 270 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 599 211 357 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1391 19 30 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1156 22 30 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1052 25 73 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 647 10 0 1 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 177 270 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 494 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 450 211 331 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1041 20 29 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 828 22 30 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_47_lut Fabric 47 false 1 UP false 2 CLK 790 25 73 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 768 0 0 1 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 768 0 0 1 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 472 10 0 1 0 0 PRODUCTION 1.30 05-15-2022

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