Performance and Resource Utilization for Discrete Fourier Transform v4.2

Vivado Design Suite Release 2025.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_d16_area_1536 16 Area false true CLK 347 3658 4743 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_area_5g 16 Area false true true CLK 303 3790 4849 16 10 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_area_no1536 16 Area false false CLK 341 3644 4623 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_spd_1536 16 Speed false true CLK 347 3658 4743 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_spd_5g 16 Speed false true true CLK 303 3790 4849 16 10 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_spd_no1536 16 Speed false false CLK 341 3644 4623 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d8_area_1536 8 Area false true CLK 352 2913 3692 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d8_area_5g 8 Area false true true CLK 325 3208 3801 16 10 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d8_area_no1536 8 Area false false CLK 341 2907 3530 16 3 4 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_d16_area_1536 16 Area false true CLK 402 3560 4683 16 4 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_area_5g 16 Area false true true CLK 407 3874 5140 16 10 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_area_no1536 16 Area false false CLK 407 3581 4652 16 3 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_spd_1536 16 Speed false true CLK 402 3560 4683 16 4 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_spd_5g 16 Speed false true true CLK 407 3874 5140 16 10 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_spd_no1536 16 Speed false false CLK 407 3581 4652 16 3 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d8_area_1536 8 Area false true CLK 402 2920 3603 16 4 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d8_area_5g 8 Area false true true CLK 402 3198 3909 16 10 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d8_area_no1536 8 Area false false CLK 402 2928 3579 16 3 4 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_d16_area_1536 16 Area false true CLK 560 3867 5095 16 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_area_5g 16 Area false true true CLK 571 4130 5116 16 10 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_area_no1536 16 Area false false CLK 560 3870 4791 16 3 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_spd_1536 16 Speed false true CLK 560 3867 5095 16 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_spd_5g 16 Speed false true true CLK 571 4130 5116 16 10 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_spd_no1536 16 Speed false false CLK 560 3870 4791 16 3 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d8_area_1536 8 Area false true CLK 566 3161 3915 16 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d8_area_5g 8 Area false true true CLK 571 3439 4062 16 10 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d8_area_no1536 8 Area false false CLK 571 3162 3834 16 3 4 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_d16_area_1536 16 Area false true CLK 456 3659 5087 16 0 4 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d16_area_5g 16 Area false true true CLK 450 4006 5213 16 0 10 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d16_area_no1536 16 Area false false CLK 456 3679 5060 16 0 3 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d16_spd_1536 16 Speed false true CLK 456 3659 5087 16 0 4 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d16_spd_5g 16 Speed false true true CLK 450 4006 5213 16 0 10 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d16_spd_no1536 16 Speed false false CLK 456 3679 5060 16 0 3 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d8_area_1536 8 Area false true CLK 450 3008 3890 16 0 4 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d8_area_5g 8 Area false true true CLK 450 3363 4139 16 0 10 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP ver_1_d8_area_no1536 8 Area false false CLK 450 3022 3930 16 0 3 4 PRODUCTION 2.14 2025-03-24

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_d16_area_1536 16 Area false true CLK 341 3633 4603 16 4 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_area_5g 16 Area false true true CLK 319 3923 4844 16 10 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_area_no1536 16 Area false false CLK 347 3636 4661 16 3 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_spd_1536 16 Speed false true CLK 341 3633 4603 16 4 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_spd_5g 16 Speed false true true CLK 319 3923 4844 16 10 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_spd_no1536 16 Speed false false CLK 347 3636 4661 16 3 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d8_area_1536 8 Area false true CLK 352 2907 3569 16 4 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d8_area_5g 8 Area false true true CLK 314 3157 3763 16 10 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d8_area_no1536 8 Area false false CLK 358 2955 3561 16 3 4 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_d16_area_1536 16 Area false true CLK 396 3563 4663 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_area_5g 16 Area false true true CLK 407 3846 4950 16 10 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_area_no1536 16 Area false false CLK 402 3593 4690 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_spd_1536 16 Speed false true CLK 396 3563 4663 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_spd_5g 16 Speed false true true CLK 407 3846 4950 16 10 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_spd_no1536 16 Speed false false CLK 402 3593 4690 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d8_area_1536 8 Area false true CLK 402 2915 3540 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d8_area_5g 8 Area false true true CLK 402 3201 3858 16 10 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d8_area_no1536 8 Area false false CLK 391 2899 3567 16 3 4 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_d16_area_1536 16 Area false true CLK 560 3869 4998 16 4 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_area_5g 16 Area false true true CLK 555 4122 5265 16 10 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_area_no1536 16 Area false false CLK 566 3944 4729 16 3 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_spd_1536 16 Speed false true CLK 560 3869 4998 16 4 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_spd_5g 16 Speed false true true CLK 555 4122 5265 16 10 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_spd_no1536 16 Speed false false CLK 566 3944 4729 16 3 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d8_area_1536 8 Area false true CLK 566 3154 3862 16 4 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d8_area_5g 8 Area false true true CLK 560 3393 3969 16 10 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d8_area_no1536 8 Area false false CLK 555 3162 3689 16 3 4 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_d16_area_1536 16 Area false true CLK 456 3601 5035 16 4 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_area_5g 16 Area false true true CLK 440 3839 5222 16 10 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_area_no1536 16 Area false false CLK 456 3638 5091 16 3 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_spd_1536 16 Speed false true CLK 456 3601 5035 16 4 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_spd_5g 16 Speed false true true CLK 440 3839 5222 16 10 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_spd_no1536 16 Speed false false CLK 456 3638 5091 16 3 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d8_area_1536 8 Area false true CLK 456 2917 3844 16 4 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d8_area_5g 8 Area false true true CLK 456 3213 4016 16 10 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d8_area_no1536 8 Area false false CLK 440 2904 3787 16 3 4 PRODUCTION 1.30 05-15-2022

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