Performance and Resource Utilization for Discrete Fourier Transform v4.2

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_d16_area_1536	16	Area	false		true	U0/CLK=330	CLK	330	3609	4873	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_area_5g	16	Area	false	true	true	U0/CLK=319	CLK	319	3927	5115	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_area_no1536	16	Area	false		false	U0/CLK=330	CLK	330	3602	4872	16	3	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_1536	16	Speed	false		true	U0/CLK=330	CLK	330	3609	4873	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=319	CLK	319	3927	5115	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=330	CLK	330	3602	4872	16	3	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_1536	8	Area	false		true	U0/CLK=330	CLK	330	2891	3611	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_5g	8	Area	false	true	true	U0/CLK=303	CLK	303	3128	3798	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_no1536	8	Area	false		false	U0/CLK=341	CLK	341	2912	3675	16	3	4	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_d16_area_1536	16	Area	false		true	U0/CLK=402	CLK	402	3577	4951	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_area_5g	16	Area	false	true	true	U0/CLK=391	CLK	391	3841	5299	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_area_no1536	16	Area	false		false	U0/CLK=402	CLK	402	3586	5027	16	3	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_1536	16	Speed	false		true	U0/CLK=402	CLK	402	3577	4951	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=391	CLK	391	3841	5299	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=402	CLK	402	3586	5027	16	3	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_1536	8	Area	false		true	U0/CLK=407	CLK	407	2938	3931	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_5g	8	Area	false	true	true	U0/CLK=391	CLK	391	3191	4217	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_no1536	8	Area	false		false	U0/CLK=407	CLK	407	2943	3817	16	3	4	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_d16_area_1536	16	Area	false		true	U0/CLK=571	CLK	571	3940	4718	16	4	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_area_5g	16	Area	false	true	true	U0/CLK=549	CLK	549	4068	5309	16	10	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_area_no1536	16	Area	false		false	U0/CLK=549	CLK	549	3742	5061	16	3	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_spd_1536	16	Speed	false		true	U0/CLK=571	CLK	571	3940	4718	16	4	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=549	CLK	549	4068	5309	16	10	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=549	CLK	549	3742	5061	16	3	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d8_area_1536	8	Area	false		true	U0/CLK=555	CLK	555	3139	3931	16	4	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d8_area_5g	8	Area	false	true	true	U0/CLK=549	CLK	549	3328	3857	16	10	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d8_area_no1536	8	Area	false		false	U0/CLK=560	CLK	560	3186	3846	16	3	4	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_d16_area_1536	16	Area	false		true	U0/CLK=450	CLK	450	3628	5364	16	0	4	4	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d16_area_5g	16	Area	false	true	true	U0/CLK=435	CLK	435	3954	5455	16	0	10	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d16_area_no1536	16	Area	false		false	U0/CLK=450	CLK	450	3641	5512	16	0	3	4	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d16_spd_1536	16	Speed	false		true	U0/CLK=450	CLK	450	3628	5364	16	0	4	4	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=435	CLK	435	3954	5455	16	0	10	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=450	CLK	450	3641	5512	16	0	3	4	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d8_area_1536	8	Area	false		true	U0/CLK=450	CLK	450	2925	4200	16	0	4	4	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d8_area_5g	8	Area	false	true	true	U0/CLK=440	CLK	440	3329	4383	16	0	10	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_d8_area_no1536	8	Area	false		false	U0/CLK=450	CLK	450	3037	4212	16	0	3	4	PRODUCTION 2.15 2026-03-17

Virtex-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_d16_area_1536	16	Area	false		true	U0/CLK=325	CLK	325	3603	4800	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_area_5g	16	Area	false	true	true	U0/CLK=303	CLK	303	3787	4971	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_area_no1536	16	Area	false		false	U0/CLK=341	CLK	341	3637	4808	16	3	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_1536	16	Speed	false		true	U0/CLK=325	CLK	325	3603	4800	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=303	CLK	303	3787	4971	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=341	CLK	341	3637	4808	16	3	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_1536	8	Area	false		true	U0/CLK=336	CLK	336	2897	3657	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_5g	8	Area	false	true	true	U0/CLK=308	CLK	308	3160	3901	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_no1536	8	Area	false		false	U0/CLK=336	CLK	336	2893	3582	16	3	4	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_d16_area_1536	16	Area	false		true	U0/CLK=396	CLK	396	3555	4735	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_area_5g	16	Area	false	true	true	U0/CLK=380	CLK	380	3833	5418	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_area_no1536	16	Area	false		false	U0/CLK=407	CLK	407	3664	5292	16	3	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_1536	16	Speed	false		true	U0/CLK=396	CLK	396	3555	4735	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=380	CLK	380	3833	5418	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=407	CLK	407	3664	5292	16	3	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_1536	8	Area	false		true	U0/CLK=407	CLK	407	2934	3884	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_5g	8	Area	false	true	true	U0/CLK=385	CLK	385	3181	4177	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_no1536	8	Area	false		false	U0/CLK=402	CLK	402	2936	3760	16	3	4	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_d16_area_1536	16	Area	false		true	U0/CLK=560	CLK	560	3938	5250	16	4	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_area_5g	16	Area	false	true	true	U0/CLK=527	CLK	527	3918	5427	16	10	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_area_no1536	16	Area	false		false	U0/CLK=560	CLK	560	3950	5223	16	3	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_spd_1536	16	Speed	false		true	U0/CLK=560	CLK	560	3938	5250	16	4	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=527	CLK	527	3918	5427	16	10	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=560	CLK	560	3950	5223	16	3	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d8_area_1536	8	Area	false		true	U0/CLK=544	CLK	544	3025	3640	16	4	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d8_area_5g	8	Area	false	true	true	U0/CLK=522	CLK	522	3215	4500	16	10	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d8_area_no1536	8	Area	false		false	U0/CLK=549	CLK	549	3100	3925	16	3	4	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_d16_area_1536	16	Area	false		true	U0/CLK=424	CLK	424	3500	5180	16	4	4	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d16_area_5g	16	Area	false	true	true	U0/CLK=402	CLK	402	3779	5242	16	10	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d16_area_no1536	16	Area	false		false	U0/CLK=456	CLK	456	3632	5165	16	3	4	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_1536	16	Speed	false		true	U0/CLK=424	CLK	424	3500	5180	16	4	4	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_5g	16	Speed	false	true	true	U0/CLK=402	CLK	402	3779	5242	16	10	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_no1536	16	Speed	false		false	U0/CLK=456	CLK	456	3632	5165	16	3	4	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d8_area_1536	8	Area	false		true	U0/CLK=418	CLK	418	2861	3927	16	4	4	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d8_area_5g	8	Area	false	true	true	U0/CLK=418	CLK	418	3174	4433	16	10	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_d8_area_no1536	8	Area	false		false	U0/CLK=450	CLK	450	2938	3990	16	3	4	PRODUCTION 1.31 12-08-2025

COPYRIGHT

Copyright 2026 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.