Performance and Resource Utilization for DFX AXI Shutdown Manager v1.0

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 423 596 911 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 407 590 911 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 399 539 893 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 462 556 894 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 598 920 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 602 921 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 561 902 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 415 555 902 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 660 1131 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 423 670 1131 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 446 609 1114 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 415 602 1113 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 407 672 1140 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 676 1146 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 625 1124 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 415 619 1124 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 462 569 913 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 614 914 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 524 571 895 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 569 898 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 516 635 922 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 620 923 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 524 577 906 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 500 564 907 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 500 672 1133 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 516 692 1133 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 508 627 1117 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 516 627 1119 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 485 646 1142 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 516 698 1143 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 500 610 1127 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 477 582 1125 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 813 629 914 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 681 595 913 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 743 571 896 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 774 564 897 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 766 629 922 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 727 617 922 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 758 576 905 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 774 575 905 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 727 667 1133 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 790 692 1133 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 743 616 1115 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 790 621 1117 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 750 675 1142 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 735 679 1142 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 813 635 1126 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 750 617 1125 0 0 0 PRODUCTION 1.29 05-01-2022

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 595 913 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 596 911 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 415 539 893 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 546 893 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 616 920 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 621 922 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 407 553 902 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 399 550 902 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 407 661 1131 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 368 646 1131 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 399 603 1113 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 616 1114 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 423 682 1141 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 684 1140 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 431 626 1124 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 415 623 1122 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 508 624 913 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 493 615 917 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 576 897 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 572 896 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 493 618 926 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 485 588 924 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 581 909 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 485 534 904 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 469 656 1134 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 493 673 1134 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 516 617 1118 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 485 578 1116 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 493 672 1142 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 508 690 1144 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 493 618 1128 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 500 614 1129 0 0 0 PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 806 623 914 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 727 628 913 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 806 571 895 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 758 561 896 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 798 635 924 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 750 632 922 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 758 580 904 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 813 588 908 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 750 668 1133 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 684 1133 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 743 612 1116 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 758 617 1115 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 712 667 1142 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 735 689 1142 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 623 1124 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 813 632 1127 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 446 600 913 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 592 911 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 542 893 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 399 543 893 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 597 920 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 423 601 920 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 446 557 902 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 446 561 904 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 674 1131 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 423 675 1132 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 615 1113 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 614 1114 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 666 1140 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 706 1140 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 423 618 1122 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 624 1122 0 0 0 PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 806 618 913 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 813 631 913 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 774 570 895 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 790 578 897 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 782 620 922 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 806 637 923 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 813 584 906 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 798 577 904 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 735 672 1133 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 813 692 1135 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 623 1115 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 806 620 1116 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 766 680 1144 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 693 1142 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 631 1125 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 766 626 1127 0 0 0 PRODUCTION 1.30 05-15-2022

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