Performance and Resource Utilization for DFX AXI Shutdown Manager v1.0

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq-7000
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=407	clk	407	576	897	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=383	clk	383	566	895	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=407	clk	407	523	877	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=423	clk	423	527	877	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=431	clk	431	594	905	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=423	clk	423	596	904	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=446	clk	446	547	886	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=438	clk	438	534	886	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=399	clk	399	658	1123	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=438	clk	438	669	1123	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=423	clk	423	606	1105	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=438	clk	438	617	1105	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=431	clk	431	697	1134	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=438	clk	438	674	1132	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=423	clk	423	613	1114	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=431	clk	431	615	1117	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=532	clk	532	609	897	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=500	clk	500	579	895	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=548	clk	548	555	877	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=516	clk	516	543	878	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=524	clk	524	610	907	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=508	clk	508	603	908	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=516	clk	516	552	889	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=532	clk	532	556	888	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=508	clk	508	667	1124	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=500	clk	500	654	1125	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=516	clk	516	602	1107	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=477	clk	477	558	1106	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=508	clk	508	673	1142	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=462	clk	462	620	1133	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=516	clk	516	614	1115	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=462	clk	462	564	1116	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=696	clk	696	580	895	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=719	clk	719	596	895	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=727	clk	727	551	878	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=766	clk	766	539	879	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=735	clk	735	605	904	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=712	clk	712	592	904	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	552	886	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=719	clk	719	553	886	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=696	clk	696	668	1124	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=696	clk	696	668	1123	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=712	clk	712	604	1106	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=719	clk	719	605	1105	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=649	clk	649	662	1132	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=719	clk	719	675	1133	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=696	clk	696	599	1114	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=719	clk	719	615	1114	0	0	0	PRODUCTION 1.29 05-01-2022

Virtex-7

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=415	clk	415	576	895	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=415	clk	415	577	895	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=446	clk	446	542	879	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=446	clk	446	524	877	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=423	clk	423	587	904	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=438	clk	438	589	904	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=423	clk	423	534	887	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=438	clk	438	542	887	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=423	clk	423	656	1123	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=446	clk	446	677	1123	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=431	clk	431	612	1105	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=438	clk	438	616	1105	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=399	clk	399	667	1132	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=423	clk	423	672	1132	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=415	clk	415	612	1115	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=415	clk	415	618	1114	0	0	0	PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=508	clk	508	605	898	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=431	clk	431	541	895	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=524	clk	524	551	879	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=532	clk	532	563	884	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=516	clk	516	614	904	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=469	clk	469	568	904	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=500	clk	500	544	889	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=462	clk	462	515	886	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=516	clk	516	683	1138	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=500	clk	500	660	1126	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=508	clk	508	617	1106	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=493	clk	493	603	1109	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=454	clk	454	633	1132	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=532	clk	532	690	1134	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=493	clk	493	612	1117	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=431	clk	431	576	1115	0	0	0	PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=719	clk	719	593	895	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=758	clk	758	609	897	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	553	878	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=758	clk	758	554	880	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=696	clk	696	608	904	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=719	clk	719	617	904	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	563	887	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	557	888	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=649	clk	649	660	1123	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=665	clk	665	664	1123	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	618	1106	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=665	clk	665	613	1105	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=649	clk	649	659	1132	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=673	clk	673	678	1132	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=681	clk	681	611	1114	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	616	1116	0	0	0	PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=423	clk	423	570	895	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=399	clk	399	575	895	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=446	clk	446	531	878	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=415	clk	415	521	877	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=431	clk	431	587	906	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=399	clk	399	578	905	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=454	clk	454	552	888	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=407	clk	407	525	886	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=438	clk	438	680	1123	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=438	clk	438	672	1123	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=446	clk	446	612	1105	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=446	clk	446	611	1105	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=438	clk	438	701	1132	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=431	clk	431	679	1132	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=415	clk	415	623	1115	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=438	clk	438	617	1114	0	0	0	PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information			Configuration Parameters																Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	RP_IS_MASTER	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	DP_PROTOCOL	DP_AXI_ADDR_WIDTH	DP_AXI_DATA_WIDTH	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	DP_AXI_RESP	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=750	clk	750	579	895	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=727	clk	727	577	895	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	545	878	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=681	clk	681	526	877	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=758	clk	758	599	905	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	0	U0/clk=750	clk	750	600	904	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=782	clk	782	549	887	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4LITE	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	553	886	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=719	clk	719	655	1123	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=688	clk	688	657	1123	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false	0	false	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=727	clk	727	594	1105	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true	0	true	0	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=750	clk	750	606	1105	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=750	clk	750	666	1132	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	0	U0/clk=681	clk	681	660	1132	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false	0	false	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=727	clk	727	608	1115	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true	0	true	1	32	AXI4MM	32	32	0	0	0	0	0	0	3	U0/clk=727	clk	727	605	1115	0	0	0	PRODUCTION 1.31 12-08-2025

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