Performance and Resource Utilization for DFX AXI Shutdown Manager v1.0

Vivado Design Suite Release 2025.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 593 911 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 589 911 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 368 511 889 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 528 889 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 602 920 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 592 920 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 415 538 898 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 415 542 898 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 662 1131 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 682 1133 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 611 1115 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 431 613 1113 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 670 1140 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 407 679 1140 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 627 1122 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 399 617 1122 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 602 913 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 508 605 914 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 493 547 896 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 500 537 897 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 524 605 922 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 493 593 922 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 566 907 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 532 568 906 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 500 672 1133 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 516 692 1133 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 508 627 1117 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 516 627 1119 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 485 646 1142 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 516 698 1143 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 500 610 1127 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 477 582 1125 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 782 622 914 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 743 599 913 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 829 559 896 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 813 560 897 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 758 615 925 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 758 613 922 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 774 555 905 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 790 564 908 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 727 667 1133 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 750 683 1133 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 743 616 1115 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 743 608 1116 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 782 674 1144 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 750 694 1142 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 813 635 1128 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 798 626 1128 0 0 0 PRODUCTION 1.29 05-01-2022

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 399 576 911 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 423 591 911 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 446 535 892 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 407 529 889 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 600 921 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 603 920 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 438 543 899 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 423 548 898 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 659 1131 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 407 678 1131 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 352 587 1113 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 446 625 1114 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 675 1140 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 678 1141 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 431 621 1122 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 423 623 1122 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 516 616 926 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 508 623 916 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 524 562 898 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 556 895 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 603 928 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 493 613 923 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 493 548 904 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 493 549 906 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 469 656 1134 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 493 673 1134 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 516 617 1118 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 485 578 1116 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 493 672 1142 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 508 690 1144 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 493 618 1128 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 500 614 1129 0 0 0 PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 743 609 913 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 758 595 914 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 743 544 895 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 774 560 896 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 750 616 922 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 782 614 922 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 813 571 906 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 790 557 905 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 750 668 1133 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 684 1133 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 743 612 1116 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 758 617 1115 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 712 667 1142 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 735 689 1142 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 623 1124 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 813 632 1127 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 581 913 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 582 911 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 531 890 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 454 541 891 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 446 610 920 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 423 591 920 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 423 537 899 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 438 537 898 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 446 678 1131 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 407 669 1133 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 446 615 1113 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 368 588 1113 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 431 680 1142 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 678 1141 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 626 1122 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 628 1122 0 0 0 PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 782 607 913 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 813 609 914 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 829 563 896 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 743 545 895 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 798 618 923 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 790 614 922 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 743 549 904 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 758 560 905 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 712 665 1133 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 758 681 1133 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 623 1115 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 806 620 1116 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 671 1142 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 790 691 1142 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 630 1125 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 766 632 1124 0 0 0 PRODUCTION 1.30 05-15-2022

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