Performance and Resource Utilization for DFX Bitstream Monitor v1.0

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq-7000
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=313	clk	313	226	426	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=321	clk	321	322	429	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=321	clk	321	481	626	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=274	clk	274	559	627	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=313	clk	313	226	426	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=321	clk	321	322	429	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=321	clk	321	481	626	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=274	clk	274	559	627	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=306	clk	306	217	426	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=274	clk	274	297	427	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=337	clk	337	498	626	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=298	clk	298	573	627	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=321	clk	321	234	426	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=306	clk	306	312	427	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=329	clk	329	489	626	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=243	clk	243	490	627	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=344	clk	344	236	426	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=313	clk	313	306	427	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=306	clk	306	479	628	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	fbg676	1	xc7k325tfbg676-1_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=298	clk	298	560	627	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=407	clk	407	224	426	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=383	clk	383	321	430	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=391	clk	391	428	627	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=344	clk	344	513	627	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=407	clk	407	224	426	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=383	clk	383	321	430	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=391	clk	391	428	627	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=344	clk	344	513	627	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=375	clk	375	228	426	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=352	clk	352	301	427	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=383	clk	383	417	626	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=337	clk	337	516	627	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=407	clk	407	233	426	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=368	clk	368	311	427	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=407	clk	407	499	626	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=344	clk	344	513	627	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=423	clk	423	229	426	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=375	clk	375	305	427	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=383	clk	383	409	626	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	fbva676	1	xcku040-fbva676-1-i_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=375	clk	375	523	628	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=579	clk	579	228	426	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=563	clk	563	321	427	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=524	clk	524	467	626	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=493	clk	493	594	627	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=579	clk	579	228	426	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=563	clk	563	321	427	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=524	clk	524	467	626	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=493	clk	493	594	627	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=587	clk	587	236	426	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=524	clk	524	308	427	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=556	clk	556	495	626	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=524	clk	524	594	627	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=625	clk	625	232	426	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=548	clk	548	302	428	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=602	clk	602	503	626	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=532	clk	532	588	627	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=594	clk	594	235	426	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=540	clk	540	307	427	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=556	clk	556	487	626	0	0	0	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	1	xcku13p-ffve900-1-e_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=508	clk	508	584	627	0	0	0	PRODUCTION 1.29 05-01-2022

Virtex-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=321	clk	321	223	426	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=306	clk	306	315	429	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=313	clk	313	469	626	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=313	clk	313	587	627	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=321	clk	321	223	426	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=306	clk	306	315	429	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=313	clk	313	469	626	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=313	clk	313	587	627	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=321	clk	321	218	426	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=298	clk	298	305	429	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=313	clk	313	472	626	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=290	clk	290	566	627	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=321	clk	321	231	426	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=290	clk	290	295	427	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=321	clk	321	488	626	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=313	clk	313	587	627	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=321	clk	321	220	426	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=290	clk	290	310	427	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=306	clk	306	475	626	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1157	1	xc7vx690tffg1157-1_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=306	clk	306	570	627	0	0	0	PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=391	clk	391	228	426	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=375	clk	375	322	427	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=391	clk	391	447	626	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=352	clk	352	533	628	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=391	clk	391	228	426	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=375	clk	375	322	427	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=391	clk	391	447	626	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=352	clk	352	533	628	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=368	clk	368	231	426	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=352	clk	352	317	427	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=383	clk	383	438	626	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=337	clk	337	520	627	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=391	clk	391	227	426	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=352	clk	352	320	427	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=407	clk	407	494	627	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=337	clk	337	517	627	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=383	clk	383	233	426	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=352	clk	352	320	427	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=383	clk	383	433	626	0	0	0	PRODUCTION 1.26 12-04-2018
xcvu095	ffvc1517	1	xcvu095-ffvc1517-1-i_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=337	clk	337	534	627	0	0	0	PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=594	clk	594	235	426	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=500	clk	500	308	427	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=548	clk	548	494	626	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=516	clk	516	577	627	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=594	clk	594	235	426	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=500	clk	500	308	427	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=548	clk	548	494	626	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=516	clk	516	577	627	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=579	clk	579	231	426	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=508	clk	508	300	427	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=563	clk	563	497	626	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=524	clk	524	592	627	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=571	clk	571	224	427	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=516	clk	516	310	427	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=563	clk	563	480	626	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=508	clk	508	579	627	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=579	clk	579	231	426	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=548	clk	548	306	433	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=532	clk	532	478	626	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	xcvu11p-flga2577-1-e_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=540	clk	540	579	627	0	0	0	PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=313	clk	313	223	426	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=313	clk	313	324	427	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=306	clk	306	471	626	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=298	clk	298	581	627	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=313	clk	313	223	426	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=313	clk	313	324	427	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=306	clk	306	471	626	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=298	clk	298	581	627	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=321	clk	321	224	426	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=298	clk	298	313	428	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=329	clk	329	487	626	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=290	clk	290	571	627	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=306	clk	306	223	426	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=298	clk	298	309	427	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=298	clk	298	474	626	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=313	clk	313	591	627	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=329	clk	329	221	426	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=290	clk	290	301	427	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=337	clk	337	497	626	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z045	fbg676	1	xc7z045fbg676-1_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=313	clk	313	585	627	0	0	0	PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	RESET_ACTIVE_LEVEL	CTRL_INTERFACE_TYPE	CTRL_ADDR_WIDTH	STS_HIST_BUFFER_WHEN_FULL	DP_PROTOCOL	PROTOCOL_RESET_ACTIVE_LEVEL	DP_AXI_ID_WIDTH	DP_AXI_AWUSER_WIDTH	DP_AXI_WUSER_WIDTH	DP_AXI_BUSER_WIDTH	DP_AXI_ARUSER_WIDTH	DP_AXI_RUSER_WIDTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=579	clk	579	230	426	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=594	clk	594	315	428	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4LITE	0	0	0	0	0	0	0	U0/clk=556	clk	556	492	626	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4LITE	0	0	0	0	0	0	0	U0/clk=524	clk	524	592	627	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=579	clk	579	230	426	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=594	clk	594	315	428	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	AXI4MM	0	0	0	0	0	0	0	U0/clk=556	clk	556	492	626	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	AXI4MM	0	0	0	0	0	0	0	U0/clk=524	clk	524	592	627	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=563	clk	563	229	426	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_GENERIC_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=563	clk	563	316	427	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	GENERIC	0	0	0	0	0	0	0	U0/clk=563	clk	563	493	626	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_GENERIC_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	GENERIC	0	0	0	0	0	0	0	U0/clk=516	clk	516	591	627	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=556	clk	556	223	426	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_ICAP_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=524	clk	524	308	427	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	ICAP	0	0	0	0	0	0	0	U0/clk=571	clk	571	486	626	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_ICAP_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	ICAP	0	0	0	0	0	0	0	U0/clk=516	clk	516	577	627	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_new	0	0	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=610	clk	610	230	426	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_USR_ACCESS_ctrl_0_hist_buf_when_full_discard_old	0	0	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=563	clk	563	316	427	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_new	0	1	32	discard_new	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=556	clk	556	480	626	0	0	0	PRODUCTION 1.31 12-08-2025
xczu4cg	fbvb900	1	xczu4cg-fbvb900-1-e_dp_protocol_USR_ACCESS_ctrl_1_hist_buf_when_full_discard_old	0	1	32	discard_old	USR_ACCESS	0	0	0	0	0	0	0	U0/clk=516	clk	516	575	627	0	0	0	PRODUCTION 1.31 12-08-2025

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