Performance and Resource Utilization for Divider Generator v5.1

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 385 479 549 7 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 347 587 1279 13 0 2 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 385 1339 1844 14 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 90 1019 325 14 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 456 17 103 2 3 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 461 1280 3334 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 636 125 262 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 478 119 207 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 560 64 134 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 461 219 487 7 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 418 545 1281 13 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 511 1072 1813 14 0 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 113 1034 325 14 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 522 18 103 2 3 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 560 1278 3334 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 735 123 264 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 533 119 207 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 593 61 135 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 527 218 453 7 0 2 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 527 539 1246 13 0 2 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 642 1071 1817 14 0 2 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 148 1036 325 14 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 642 18 127 2 3 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 763 1279 3334 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 122 264 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 785 118 209 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 866 63 136 0 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 533 207 453 7 0 0 2 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 489 569 1260 13 0 0 2 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 544 1004 1712 14 0 0 2 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 119 852 311 14 0 0 2 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 615 18 127 2 0 3 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 604 1285 3334 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 680 124 262 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 577 111 207 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 599 61 134 0 0 0 0 PRODUCTION 2.13 2024-03-28

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 380 479 550 7 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 341 584 1280 13 0 2 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 391 1341 1842 14 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 90 1020 325 14 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 450 17 103 2 3 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 456 1280 3334 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 636 125 264 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 489 119 207 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 489 64 134 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 461 220 494 7 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 369 527 1241 13 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 489 983 1795 14 0 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 113 1035 325 14 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 424 18 127 2 3 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 560 1278 3334 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 702 124 264 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 533 118 209 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 625 63 136 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 527 218 453 7 0 2 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 522 538 1248 13 0 2 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 642 1071 1862 14 0 2 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 154 1035 325 14 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 625 18 127 2 3 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 800 1279 3334 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 122 264 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 790 118 209 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 872 61 136 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 494 218 518 7 0 2 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 440 528 1241 13 0 2 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 511 979 1837 14 0 2 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 131 1033 325 14 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 511 18 103 2 3 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 615 1279 3334 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 636 123 262 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 615 119 209 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 636 62 134 0 0 0 PRODUCTION 1.30 05-15-2022

COPYRIGHT

Copyright 2024 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.