Resource Utilization for MIPI TX CPHY/DPHY v1.0

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Versal ACAP

Part Information			Configuration Parameters									Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_PHY_MODE	C_PHY_LANES	C_LINE_RATE	C_EN_ESC_MODE	C_REG_ON	C_EN_TIMEOUT_REGS	C_XMIT_PERIODIC_DESKEW_SEQ	Fixed clocks (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	MMCM	BUFGCE	Speedfile Status
xcvm2152	nfvd1024	1MP	cphy_ln1_lr400_esc0_reg0_timeout0	CPHY	1	400	false	false	false		core_clk=200 txwordclkhs_out=100	953	900	0	0	1	0	1	4	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	cphy_ln1_lr400_esc1_reg0_timeout0	CPHY	1	400	true	false	false		core_clk=200 txclkesc_out=100 txwordclkhs_out=100	1047	945	0	0	1	0	1	5	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	cphy_ln1_lr400_esc1_reg1_timeout1	CPHY	1	400	true	true	true		core_clk=200 s_axi_aclk=100 txclkesc_out=100 txwordclkhs_out=100	1599	1606	0	0	1	0	1	6	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	cphy_ln3_lr4500_esc0_reg0_timeout0	CPHY	3	4500	false	false	false		core_clk=200 txwordclkhs_out=100	3574	4137	0	0	3	0	1	4	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	cphy_ln3_lr4500_esc1_reg0_timeout0	CPHY	3	4500	true	false	false		core_clk=200 txclkesc_out=100 txwordclkhs_out=100	3755	4241	0	0	3	0	1	5	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	cphy_ln3_lr4500_esc1_reg1_timeout1	CPHY	3	4500	true	true	true		core_clk=200 s_axi_aclk=100 txclkesc_out=100 txwordclkhs_out=100	5084	5149	0	0	3	0	1	6	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	cphy_ln3_lr4500_esc1_reg1_timeout1_skew1	CPHY	3	4500	true	true	true	true	core_clk=200 s_axi_aclk=100 txclkesc_out=100 txwordclkhs_out=100	5084	5149	0	0	3	0	1	6	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln1_lr400_esc0_reg0_timeout0	DPHY	1	400	false	false	false		core_clk=200 txwordclkhs_out=100	478	365	0	0	0	0	1	4	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln1_lr400_esc1_reg0_timeout0	DPHY	1	400	true	false	false		core_clk=200 txclkesc_out=100 txwordclkhs_out=100	587	423	0	0	0	0	1	5	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln1_lr400_esc1_reg1_timeout1	DPHY	1	400	true	true	true		core_clk=200 s_axi_aclk=100 txclkesc_out=100 txwordclkhs_out=100	1045	912	0	0	0	0	1	6	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln4_lr4500_esc0_reg0_timeout0	DPHY	4	4500	false	false	false		core_clk=200 txwordclkhs_out=100	874	665	0	0	0	0	1	4	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln4_lr4500_esc1_reg0_timeout0	DPHY	4	4500	true	false	false		core_clk=200 txclkesc_out=100 txwordclkhs_out=100	1126	879	0	0	0	0	1	5	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln4_lr4500_esc1_reg1_timeout1	DPHY	4	4500	true	true	true		core_clk=200 s_axi_aclk=100 txclkesc_out=100 txwordclkhs_out=100	1812	1608	0	0	0	0	1	6	PRODUCTION 2.04 2025-10-08
xcvm2152	nfvd1024	1MP	dphy_ln4_lr4500_esc1_reg1_timeout1_skew1	DPHY	4	4500	true	true	true	true	core_clk=200 s_axi_aclk=100 txclkesc_out=100 txwordclkhs_out=100	1812	1608	0	0	0	0	1	6	PRODUCTION 2.04 2025-10-08

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