Resource Utilization for Multiport RAM v1.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Versal ACAP

Part Information			Configuration Parameters																									Resource Utilization
Device	Package	Speed Grade	Configuration Name	G0_Wr	G1_Wr	G0_Rd	G1_Rd	Num_Inactive_Units	Unit_Intf_Enb	ECC_Report_Enb	U0_Wr	U1_Wr	U2_Wr	U3_Wr	U4_Wr	U5_Wr	U6_Wr	U7_Wr	U0_Rd	U1_Rd	U2_Rd	U3_Rd	U4_Rd	U5_Rd	U6_Rd	U7_Rd	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvp1002	nfvi1369	1MP	global_2_if_ecc_vp1002_1mp	1	2	2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	clk=492	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1002	vfvf1760	2MP	global_2_if_ecc_vp1002_2mp	1	2	2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	clk=492	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1052	sbvj1369	1MP	global_2_if_ecc_vp1052_1mp	1	2	2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	clk=492	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1052	nfvi1369	2MP	global_2_if_ecc_vp1052_2mp	1	2	2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	clk=492	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1002	nfvi1369	1LHP	global_2_unit_8_if_ecc_vp1002_1lhp	2	1	1	2	0	1	1	1	2	1	2	1	2	1	2	0	0	2	1	2	1	2	1	clk=400	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1002	vfvf1760	2HP	global_2_unit_8_if_ecc_vp1002_2hp	2	1	1	2	0	1	1	1	2	1	2	1	2	1	2	0	0	2	1	2	1	2	1	clk=492	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1052	nfvi1369	1LHP	global_2_unit_8_if_ecc_vp1052_1lhp	2	1	1	2	0	1	1	1	2	1	2	1	2	1	2	0	0	2	1	2	1	2	1	clk=400	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1052	nfvi1369	2HP	global_2_unit_8_if_ecc_vp1052_2hp	2	1	1	2	0	1	1	1	2	1	2	1	2	1	2	0	0	2	1	2	1	2	1	clk=492	63	96	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1002	nfvi1369	1LP	unit_8_if_no_ecc_vp1002_1lp	0	0	0	0	0	1	0	1	2	1	2	1	2	1	2	2	1	2	1	2	1	2	1	clk=400	19	29	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1002	vfvf1760	2LP	unit_8_if_no_ecc_vp1002_2lp	0	0	0	0	0	1	0	1	2	1	2	1	2	1	2	2	1	2	1	2	1	2	1	clk=492	19	29	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1052	sbvj1369	1LP	unit_8_if_no_ecc_vp1052_1lp	0	0	0	0	0	1	0	1	2	1	2	1	2	1	2	2	1	2	1	2	1	2	1	clk=400	19	29	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06
xcvp1052	sbvj1369	2LP	unit_8_if_no_ecc_vp1052_2lp	0	0	0	0	0	1	0	1	2	1	2	1	2	1	2	2	1	2	1	2	1	2	1	clk=492	19	29	0	0	0	ENGINEERING-SAMPLE 1.11 2023-09-06

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