Performance and Resource Utilization for Reed-Solomon Encoder v9.0

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 500 201 213 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 275 303 303 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 260 703 491 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 538 172 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 505 322 337 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 472 199 209 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 500 166 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 555 85 105 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 713 205 214 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 352 307 303 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 341 735 491 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 615 175 181 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 610 328 321 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 571 202 208 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 724 178 183 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 735 88 105 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 916 202 213 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 483 305 303 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 483 734 491 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 965 176 181 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 334 322 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 866 205 208 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 1003 174 183 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 82 105 0 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 664 204 213 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 582 305 350 0 0 0 1 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 511 797 741 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 680 173 181 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 675 337 325 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 625 179 221 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 680 174 181 0 0 0 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 680 84 105 0 0 0 0 PRODUCTION 2.13 2024-03-28

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 516 204 213 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 300 303 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 249 707 491 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 538 173 181 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 489 306 332 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 483 199 209 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 538 171 181 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 588 83 105 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 680 203 213 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 358 317 303 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 336 726 491 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 664 174 181 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 615 333 326 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 647 213 210 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 757 173 183 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 708 88 106 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 921 205 216 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 467 299 303 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 483 723 491 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 927 174 181 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 334 334 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 828 203 208 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 975 172 182 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 86 105 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 708 202 213 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 352 322 303 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 363 718 491 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 779 176 182 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 636 321 320 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 636 201 208 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 790 172 183 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 636 82 105 0 0 0 PRODUCTION 1.30 05-15-2022

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