Performance and Resource Utilization for Interleaver/De-interleaver v8.0

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 396 120 151 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 396 119 149 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 188 133 157 0 4 2 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 440 99 108 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 456 102 150 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 456 104 148 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 227 134 168 0 4 2 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 560 98 109 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 571 110 149 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 571 106 147 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 341 133 168 0 4 2 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 866 101 110 0 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 505 129 175 0 0 0 1 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 505 129 176 0 0 0 1 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 260 249 154 0 0 18 2 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP ver_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 571 111 155 0 0 0 0 PRODUCTION 2.13 2024-03-28

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 396 120 151 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 380 118 149 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 188 134 157 0 4 2 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 461 104 108 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 456 104 150 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 456 103 148 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 216 134 152 0 4 2 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 538 102 110 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 571 109 149 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 571 108 147 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 330 134 168 0 4 2 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 866 98 109 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
symbol_width
sid_type
mode
symbol_memory
number_of_branches
number_of_configurations
branch_length_type
branch_length_constant
branch_length_coe_file_name
number_of_rows
number_of_rows_constant_value
row_port_width
number_of_columns
minimum_rows
number_of_columns_constant_value
minimum_columns
number_of_columns_selectable_value
block_size_constant_value
coe_file
block_size_port_width
HAS_BLOCK_START
HAS_BLOCK_END
HAS_ACLKEN
HAS_ARESETN
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_dvb1_rx 8 forney deinterleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 456 101 149 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_dvb1_tx 8 forney interleaver internal 12 1 constant_difference_between_consecutive_branches 17 constant 15 4 constant 15 15 15 4 225 no_coe_file_loaded 8 false false aclk 456 101 147 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_itu_j83b 1 forney interleaver internal 16 16 coe_file_defines_branch_length_constant_for_each_configuration 1 ../../../../../itu_j83.coe constant 15 4 constant 15 15 15 4 225 8 false false aclk 249 133 168 0 4 2 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_rect_3gpp2_fspdcch 1 rectangular interleaver external 16 1 constant_difference_between_consecutive_branches 1 constant 15 4 selectable 15 15 15 3 225 ../../../../../coe_file_3gpp2.coe 8 true true true true aclk 625 101 110 0 0 0 PRODUCTION 1.30 05-15-2022

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