Performance and Resource Utilization for Video Frame Buffer Read v3.0

Vivado Design Suite Release 2025.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
AXIMM_DATA_WIDTH
HAS_ALPHA
HAS_RGBX8
HAS_YUVX8
HAS_YUYV8
HAS_RGBA8
HAS_YUVA8
HAS_RGBX10
HAS_YUVX10
HAS_Y_UV8
HAS_Y_UV8_420
HAS_RGB8
HAS_YUV8
HAS_Y_UV10
HAS_Y_UV10_420
HAS_Y8
HAS_Y10
HAS_BGRA8
HAS_BGRX8
HAS_UYVY8
HAS_BGR8
HAS_RGBX12
HAS_RGB16
HAS_YUVX12
HAS_Y_UV12
HAS_Y_UV12_420
HAS_Y12
HAS_YUV16
HAS_Y_UV16
HAS_Y_UV16_420
HAS_Y16
HAS_Y_U_V8
HAS_Y_U_V8_420
MAX_NR_PLANES
HAS_Y_U_V10
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_100 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 521 8073 13835 0 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_101 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 443 3116 4545 0 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_102 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 537 4845 7991 0 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_103 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 568 5659 10222 0 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_104 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 419 7745 13296 0 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_109 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 435 3080 4484 1 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_111 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 412 5823 10575 1 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_112 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 482 14726 25460 1 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_113 1 10328 7760 8 64 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 ap_clk 419 3658 5018 1 0 17 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_114 2 10328 7760 8 128 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 474 6808 11808 1 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_115 4 10328 7760 8 256 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 490 8625 15778 1 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_116 8 10328 7760 8 512 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 466 15019 29305 1 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_81 1 10328 7760 8 64 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 568 2884 4048 0 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_83 4 10328 7760 8 256 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 474 2523 4120 0 0 11 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_86 2 10328 7760 8 128 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 662 1937 3113 0 0 9 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_87 4 10328 7760 8 256 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 427 4956 9054 0 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_88 8 10328 7760 8 512 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 599 5664 5130 0 0 14 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_89 1 10328 7760 8 64 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 544 3977 5566 0 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_91 4 10328 7760 8 256 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 435 5288 10393 0 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_92 8 10328 7760 8 512 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 419 9457 18610 0 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_93 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 591 1951 2505 1 0 9 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_94 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 568 4088 7200 1 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_98 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 450 1951 2998 0 0 9 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_99 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 450 5600 9862 0 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_29 1 10328 7760 10 64 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 435 4080 5671 0 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_31 4 10328 7760 10 256 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 450 5162 8715 0 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_32 8 10328 7760 10 512 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 537 7828 12847 0 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_33 1 10328 7760 10 64 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1720 2164 0 0 9 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_36 8 10328 7760 10 512 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 388 10862 18572 1 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_37 1 10328 7760 10 64 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 583 3570 5242 1 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_38 2 10328 7760 10 128 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 521 5289 8991 1 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_39 4 10328 7760 10 256 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 412 8082 14384 0 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_41 1 10328 7760 10 64 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 583 3242 4657 1 0 24 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_42 2 10328 7760 10 128 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 591 4798 8047 1 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_44 8 10328 7760 10 512 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 404 8777 14582 0 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_45 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 537 4379 6055 2 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_47 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 404 8451 15035 2 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_48 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 443 4979 7528 1 0 14 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_49 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 ap_clk 607 2108 3028 1 0 15 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_50 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 450 4190 7085 1 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_51 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 ap_clk 474 3486 5961 1 0 18 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_52 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 381 13392 24611 1 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_53 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 591 3131 4565 0 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_54 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 638 2027 3034 0 0 9 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_55 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 529 8843 14628 1 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_56 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 529 10933 18390 1 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_57 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 575 4152 5939 1 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_59 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 427 6680 11413 1 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_61 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 412 4198 5861 1 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_63 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 450 6772 11693 1 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_64 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 404 10636 18416 1 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_65 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 412 4736 6499 1 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_66 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 591 3741 6137 0 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_67 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 529 8549 14673 1 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_68 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 513 12585 22963 0 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_70 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 575 4196 7435 1 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_71 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 419 5768 9496 2 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_72 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 513 13815 24483 2 0 28 4 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_73 1 10328 7760 10 64 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 544 6964 9525 2 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_74 2 10328 7760 10 128 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 482 6933 11177 2 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_75 4 10328 7760 10 256 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 341 10418 18411 2 0 25 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_12bit__conf_1 1 10328 7760 12 64 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 3 1 ap_clk 365 6353 9258 2 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_12bit__conf_2 2 10328 7760 12 128 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 1 3 0 ap_clk 490 7586 12573 2 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_16bit__conf_77 1 10328 7760 16 64 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 3 1 ap_clk 466 7876 11141 2 0 25 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_16bit__conf_78 2 10328 7760 16 128 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 3 1 ap_clk 349 8645 15432 2 0 23 3 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_06 1 10328 7760 10 64 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 474 1604 2057 0 0 9 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_07 2 10328 7760 8 128 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 662 1949 3164 0 0 9 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_09 4 10328 7760 8 256 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 2428 4270 0 0 11 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_10 4 10328 7760 10 256 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 498 2936 5147 0 0 11 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_11 8 10328 7760 8 512 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 3008 6876 0 0 14 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_12 8 10328 7760 10 512 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 2926 5831 0 0 14 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_13 1 10328 7760 8 64 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 654 1687 2130 0 0 9 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_17 4 10328 7760 8 256 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 646 2566 4303 0 0 11 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_19 8 10328 7760 8 512 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 474 3391 7831 0 0 14 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_20 8 10328 7760 10 512 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 591 2993 5714 0 0 14 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_22 1 10328 7760 10 64 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 638 1846 2462 0 0 9 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_23 2 10328 7760 8 128 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 2144 3414 0 0 9 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_24 2 10328 7760 10 128 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 646 2198 3530 0 0 9 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_25 4 10328 7760 8 256 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 599 2708 5025 0 0 11 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_26 4 10328 7760 10 256 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 2809 5273 0 0 11 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_28 8 10328 7760 10 512 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 599 3814 7303 0 0 14 2 PRODUCTION 2.14 2025-03-24

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
AXIMM_DATA_WIDTH
HAS_ALPHA
HAS_RGBX8
HAS_YUVX8
HAS_YUYV8
HAS_RGBA8
HAS_YUVA8
HAS_RGBX10
HAS_YUVX10
HAS_Y_UV8
HAS_Y_UV8_420
HAS_RGB8
HAS_YUV8
HAS_Y_UV10
HAS_Y_UV10_420
HAS_Y8
HAS_Y10
HAS_BGRA8
HAS_BGRX8
HAS_UYVY8
HAS_BGR8
HAS_RGBX12
HAS_RGB16
HAS_YUVX12
HAS_Y_UV12
HAS_Y_UV12_420
HAS_Y12
HAS_YUV16
HAS_Y_UV16
HAS_Y_UV16_420
HAS_Y16
HAS_Y_U_V8
HAS_Y_U_V8_420
MAX_NR_PLANES
HAS_Y_U_V10
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_105 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 435 2317 3234 0 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_106 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 427 3700 5181 0 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_107 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 599 2528 3150 0 11 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_108 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 396 5965 9264 0 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_110 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 458 3229 5064 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_82 2 10328 7760 8 128 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 466 3002 4659 0 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_84 8 10328 7760 8 512 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 544 4189 4992 0 14 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_85 1 10328 7760 8 64 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 544 2716 4030 0 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_90 2 10328 7760 8 128 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 412 3590 5222 0 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_95 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 412 5471 8621 1 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_96 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 506 4726 6900 1 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_97 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 474 3003 3967 0 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_30 2 10328 7760 10 128 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1759 2353 0 9 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_34 2 10328 7760 10 128 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 412 3034 4708 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_35 4 10328 7760 10 256 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 474 4121 6639 0 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_40 8 10328 7760 10 512 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 482 7532 11179 0 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_43 4 10328 7760 10 256 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 412 4232 6862 0 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_46 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 537 1878 2809 1 9 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_58 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 396 3601 5246 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_60 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 412 6343 8976 1 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_62 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 427 3017 4651 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_69 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 412 3336 4409 2 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_76 8 10328 7760 10 512 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 318 11162 16218 2 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_12bit__conf_3 4 10328 7760 12 256 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 568 2068 3014 0 11 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_12bit__conf_4 8 10328 7760 12 512 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 1 3 1 ap_clk 333 19090 27942 2 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_16bit__conf_79 4 10328 7760 16 256 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 3 0 ap_clk 325 9435 17114 2 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_16bit__conf_80 8 10328 7760 16 512 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 3 1 ap_clk 349 19025 30351 2 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_05 1 10328 7760 8 64 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1460 1983 0 8 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_08 2 10328 7760 10 128 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 615 1682 2275 0 9 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_14 1 10328 7760 10 64 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1522 2025 0 8 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_15 2 10328 7760 8 128 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1809 2380 0 9 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_16 2 10328 7760 10 128 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1832 2388 0 9 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_18 4 10328 7760 10 256 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 2153 3073 0 11 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_21 1 10328 7760 8 64 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 607 1562 2135 0 8 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_27 8 10328 7760 8 512 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 552 3389 5513 0 14 2 PRODUCTION 1.30 05-15-2022

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