Resource Utilization for HDMI 2.1 Receiver Subsystem v1.2

Vivado Design Suite Release 2025.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2025.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex UltraScale+
Versal ACAP
Virtex UltraScale+
Virtex UltraScale+
Virtex UltraScale+
Zynq UltraScale+

Kintex UltraScale+

Part Information			Configuration Parameters							Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INCLUDE_HDCP	C_MAX_BITS_PER_COMPONENT	C_INPUT_PIXELS_PER_CLOCK	C_EDID_RAM_SIZE	C_VID_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku15p	ffva1760	2LV	hdmi_2_1_rx_conf_08	false	16	4	4096	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	36753	30867	0	19	18	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	2LV	hdmi_2_1_rx_conf_09	false	10	8	4096	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	37833	33593	0	31	21	PRODUCTION 1.29 05-01-2022
xcku15p	ffva1156	1	hdmi_2_1_rx_conf_11	false	8	4	4096	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	37219	33052	0	26	18	PRODUCTION 1.29 05-01-2022
xcku11p	ffvd900	1	hdmi_2_1_rx_conf_12	true	8	8	256	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	53982	46013	4	33	19	PRODUCTION 1.29 05-01-2022
xqku15p	ffre1517	1LV	hdmi_2_1_rx_conf_18	false	10	4	512	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	36216	30960	0	18	19	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	3	hdmi_2_1_rx_conf_19	true	8	8	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53885	46074	4	34	18	PRODUCTION 1.29 05-01-2022
xcku5p	sfvb784	1	hdmi_2_1_rx_conf_21	true	8	4	4096	1	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=375	52654	43685	4	23	18	PRODUCTION 1.29 05-01-2022
xcku5p	sfvb784	1LV	hdmi_2_1_rx_conf_25	true	10	8	1024	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	54040	46535	4	34	22	PRODUCTION 1.29 05-01-2022
xcku15p	ffva1760	1	hdmi_2_1_rx_conf_30	true	12	4	512	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	54015	46101	4	38	20	PRODUCTION 1.29 05-01-2022
xcku13p	ffve900	2	hdmi_2_1_rx_conf_42	false	16	4	256	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	36664	31355	0	18	19	PRODUCTION 1.29 05-01-2022
xcku3p	ffvb676	2LV	hdmi_2_1_rx_conf_45	false	8	4	256	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	37180	32727	0	25	19	PRODUCTION 1.29 05-01-2022
xcku5p	ffvd900	1L	hdmi_2_1_rx_conf_50	false	10	4	1024	1	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=375	36442	31215	0	18	19	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters							Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INCLUDE_HDCP	C_MAX_BITS_PER_COMPONENT	C_INPUT_PIXELS_PER_CLOCK	C_EDID_RAM_SIZE	C_VID_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	HDMI21_RANDOM__conf_51	true	10	4	512	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	51536	44527	4	0	23	19	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	2LP	HDMI21_RANDOM__conf_52	false	10	4	4096	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	33832	30922	0	0	19	18	PRODUCTION 2.14 2025-03-24
xcvm1802	vsva2197	1MP	HDMI21_RANDOM__conf_53	true	16	4	256	1	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=375	51648	44564	4	0	23	19	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	2MP	HDMI21_RANDOM__conf_54	false	16	4	256	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	34225	31244	0	0	18	19	PRODUCTION 2.14 2025-03-24
xcvm1802	vsva2197	3HP	HDMI21_RANDOM__conf_55	false	16	4	1024	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	33834	31102	0	0	18	19	PRODUCTION 2.14 2025-03-24
xcvm1802	vsva2197	1LP	HDMI21_RANDOM__conf_56	false	16	8	4096	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	36218	35512	0	0	39	20	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	1LHP	HDMI21_RANDOM__conf_57	false	8	8	256	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	34988	33694	0	0	29	19	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	1MP	HDMI21_RANDOM__conf_58	false	16	4	4096	1	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=375	34553	31450	0	0	19	18	PRODUCTION 2.14 2025-03-24
xcvm1802	vsvd1760	2LP	HDMI21_RANDOM__conf_59	false	12	8	1024	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	35356	34449	0	0	33	21	PRODUCTION 2.14 2025-03-24
xcvm1802	vsva2197	2MP	HDMI21_RANDOM__conf_60	true	12	4	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	52172	46789	4	0	40	19	PRODUCTION 2.14 2025-03-24
xcvm1802	vsva2197	3HP	HDMI21_RANDOM__conf_61	true	12	4	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	51763	46500	4	0	40	19	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	2MP	HDMI21_RANDOM__conf_62	false	16	8	512	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	35880	35536	0	0	38	21	PRODUCTION 2.14 2025-03-24
xcvm1802	vsva2197	1MP	HDMI21_RANDOM__conf_63	false	10	8	4096	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	35498	33745	0	0	31	21	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	1LP	HDMI21_RANDOM__conf_64	true	16	8	256	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	53290	48322	4	0	43	21	PRODUCTION 2.14 2025-03-24
xcvc1902	vsva2197	1LHP	HDMI21_RANDOM__conf_65	true	8	4	4096	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	51062	44194	4	0	24	18	PRODUCTION 2.14 2025-03-24

Virtex UltraScale+

Part Information			Configuration Parameters							Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INCLUDE_HDCP	C_MAX_BITS_PER_COMPONENT	C_INPUT_PIXELS_PER_CLOCK	C_EDID_RAM_SIZE	C_VID_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu13p	fsga2577	2	hdmi_2_1_rx_conf_13	false	10	4	256	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	37384	32809	0	30	22	PRODUCTION 1.28 03-30-2022
xqvu11p	flrc2104	2LV	hdmi_2_1_rx_conf_20	true	8	4	512	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	52570	43571	4	22	19	PRODUCTION 1.28 03-30-2022
xcvu9p	flga2104	2L	hdmi_2_1_rx_conf_23	true	8	4	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53487	45635	4	30	18	PRODUCTION 1.28 03-30-2022
xcvu11p	flgf1924	3	hdmi_2_1_rx_conf_27	false	12	8	1024	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	38058	34472	0	33	21	PRODUCTION 1.28 03-30-2022
xcvu7p	flvb2104	2	hdmi_2_1_rx_conf_35	true	12	8	256	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	54311	47000	4	37	21	PRODUCTION 1.28 03-30-2022
xcvu11p	flgc2104	2	hdmi_2_1_rx_conf_47	true	12	4	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53926	46181	4	39	19	PRODUCTION 1.28 03-30-2022

Virtex UltraScale+

Part Information			Configuration Parameters							Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INCLUDE_HDCP	C_MAX_BITS_PER_COMPONENT	C_INPUT_PIXELS_PER_CLOCK	C_EDID_RAM_SIZE	C_VID_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu29p	fsga2577	2	hdmi_2_1_rx_conf_02	false	8	4	512	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	36251	31030	0	18	19	PRODUCTION 1.33 05-09-2022
xcvu29p	figd2104	2L	hdmi_2_1_rx_conf_07	true	16	4	256	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	53021	43902	4	22	19	PRODUCTION 1.33 05-09-2022
xcvu27p	figd2104	2	hdmi_2_1_rx_conf_24	false	12	8	256	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	37923	34471	0	33	21	PRODUCTION 1.33 05-09-2022
xcvu27p	figd2104	1	hdmi_2_1_rx_conf_37	false	12	8	256	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	38076	34194	0	33	21	PRODUCTION 1.33 05-09-2022
xcvu27p	figd2104	3	hdmi_2_1_rx_conf_40	false	8	4	512	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	36270	31089	0	18	19	PRODUCTION 1.33 05-09-2022
xcvu27p	fsga2577	2L	hdmi_2_1_rx_conf_46	true	8	4	4096	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	52452	43688	4	23	18	PRODUCTION 1.33 05-09-2022

Virtex UltraScale+

Part Information			Configuration Parameters							Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INCLUDE_HDCP	C_MAX_BITS_PER_COMPONENT	C_INPUT_PIXELS_PER_CLOCK	C_EDID_RAM_SIZE	C_VID_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu33p	fsvh2104	2	hdmi_2_1_rx_conf_04	true	10	4	1024	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53699	45909	4	34	22	PRODUCTION 1.30 05-01-2022
xcvu35p	fsvh2892	3	hdmi_2_1_rx_conf_06	true	10	4	512	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53765	45777	4	34	22	PRODUCTION 1.30 05-01-2022
xcvu47p	fsvh2892	2	hdmi_2_1_rx_conf_15	true	16	4	4096	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	52969	44026	4	23	18	PRODUCTION 1.30 05-01-2022
xcvu37p	fsvh2892	2LV	hdmi_2_1_rx_conf_16	false	10	4	1024	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	36390	30862	0	18	19	PRODUCTION 1.30 05-01-2022
xcvu35p	fsvh2892	2LV	hdmi_2_1_rx_conf_26	false	16	8	4096	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	38631	34936	0	39	20	PRODUCTION 1.30 05-01-2022
xqvu37p	fsqh2892	2	hdmi_2_1_rx_conf_28	false	16	4	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	38004	34764	0	24	19	PRODUCTION 1.30 05-01-2022
xcvu37p	fsvh2892	2L	hdmi_2_1_rx_conf_29	false	10	8	256	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	37750	33939	0	30	22	PRODUCTION 1.30 05-01-2022
xcvu45p	fsvh2104	2LV	hdmi_2_1_rx_conf_34	true	10	4	1024	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	52736	43363	4	22	19	PRODUCTION 1.30 05-01-2022
xcvu33p	fsvh2104	2	hdmi_2_1_rx_conf_36	false	8	4	4096	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	36121	31163	0	19	18	PRODUCTION 1.30 05-01-2022
xcvu37p	fsvh2892	2LV	hdmi_2_1_rx_conf_43	true	10	4	256	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	52714	43474	4	22	19	PRODUCTION 1.30 05-01-2022
xcvu45p	fsvh2104	2	hdmi_2_1_rx_conf_48	true	10	4	512	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	52602	43732	4	22	19	PRODUCTION 1.30 05-01-2022
xcvu45p	fsvh2104	3	hdmi_2_1_rx_conf_49	true	10	4	1024	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	52724	43485	4	22	19	PRODUCTION 1.30 05-01-2022

Zynq UltraScale+

Part Information			Configuration Parameters							Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INCLUDE_HDCP	C_MAX_BITS_PER_COMPONENT	C_INPUT_PIXELS_PER_CLOCK	C_EDID_RAM_SIZE	C_VID_INTERFACE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu15eg	ffvc900	3	hdmi_2_1_rx_conf_01	true	12	4	1024	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	52863	43782	4	22	19	PRODUCTION 1.30 05-15-2022
xczu15eg	ffvc900	1	hdmi_2_1_rx_conf_03	false	12	4	512	1	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=375	36597	31200	0	18	19	PRODUCTION 1.30 05-15-2022
xczu5ev	fbvb900	1	hdmi_2_1_rx_conf_05	true	12	8	512	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	54536	46579	4	37	21	PRODUCTION 1.30 05-15-2022
xczu17eg	ffvd1760	1L	hdmi_2_1_rx_conf_10	true	8	8	1024	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	53925	45947	4	33	19	PRODUCTION 1.30 05-15-2022
xczu17eg	ffve1924	2	hdmi_2_1_rx_conf_14	true	10	4	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53712	45906	4	35	21	PRODUCTION 1.30 05-15-2022
xczu19eg	ffve1924	1LV	hdmi_2_1_rx_conf_17	false	16	4	4096	1	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=300	36605	31057	0	19	18	PRODUCTION 1.30 05-15-2022
xczu5eg	sfvc784	2L	hdmi_2_1_rx_conf_22	true	12	4	1024	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53894	46101	4	38	20	PRODUCTION 1.30 05-15-2022
xczu19eg	ffvd1760	1	hdmi_2_1_rx_conf_31	true	16	4	512	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	54562	46983	4	27	20	PRODUCTION 1.30 05-15-2022
xczu7cg	fbvb900	2	hdmi_2_1_rx_conf_32	true	12	4	1024	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	53896	45993	4	38	20	PRODUCTION 1.30 05-15-2022
xqzu9eg	ffrc900	1M	hdmi_2_1_rx_conf_33	false	16	8	4096	0	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=380 video_clk=375	38678	35337	0	39	20	PRODUCTION 1.30 05-15-2022
xczu6eg	ffvb1156	2LV	hdmi_2_1_rx_conf_38	true	10	8	4096	0	frl_clk=325 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=300 video_clk=300	54187	46221	4	35	21	PRODUCTION 1.30 05-15-2022
xczu5cg	fbvb900	1	hdmi_2_1_rx_conf_39	true	12	4	256	1	frl_clk=380 link_clk=200 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=375	52893	43784	4	22	19	PRODUCTION 1.30 05-15-2022
xczu11eg	ffvc1760	2	hdmi_2_1_rx_conf_41	false	12	8	4096	0	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 s_axis_video_aclk=375 video_clk=400	38002	34527	0	34	20	PRODUCTION 1.30 05-15-2022
xczu7ev	fbvb900	2	hdmi_2_1_rx_conf_44	true	10	4	256	1	frl_clk=450 link_clk=300 s_axi_cpu_aclk=100 s_axis_audio_aclk=100 video_clk=400	52620	43613	4	22	19	PRODUCTION 1.30 05-15-2022

COPYRIGHT

Copyright 2025 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.