Performance and Resource Utilization for Video Scene Change Detection v1.1

Vivado Design Suite Release 2025.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_DATA_WIDTH
MAX_NR_STREAMS
MEMORY_BASED
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 2MP v_scenechange_memb_300__conf_14 1 8 2 1 ap_clk 598 2015 2356 0 0 2 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_scenechange_memb_300__conf_16 1 8 4 1 ap_clk 469 2336 3351 0 0 2 1 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_scenechange_memb_300__conf_17 1 8 5 1 ap_clk 590 2645 3702 0 0 2 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_scenechange_memb_300__conf_18 1 8 6 1 ap_clk 434 2808 4137 0 0 2 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_scenechange_memb_300__conf_20 1 8 8 1 ap_clk 434 3169 4999 0 0 2 2 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_scenechange_strm_300__conf_01 1 8 1 0 ap_clk 624 1139 1355 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_scenechange_strm_300__conf_03 1 12 1 0 ap_clk 469 1215 1458 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_scenechange_strm_300__conf_04 1 16 1 0 ap_clk 460 1283 1576 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_scenechange_strm_300__conf_05 2 8 1 0 ap_clk 632 1473 1675 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_scenechange_strm_300__conf_06 2 10 1 0 ap_clk 632 1675 1765 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_scenechange_strm_300__conf_07 2 12 1 0 ap_clk 624 1789 1886 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 2MP v_scenechange_strm_300__conf_09 4 8 1 0 ap_clk 598 2258 2353 0 0 0 0 PRODUCTION 2.14 2025-03-24
xcvc1902 vsva2197 1LP v_scenechange_strm_300__conf_10 4 10 1 0 ap_clk 477 2550 2608 0 0 0 0 PRODUCTION 2.14 2025-03-24

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_DATA_WIDTH
MAX_NR_STREAMS
MEMORY_BASED
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu7ev ffvc1156 2 v_scenechange_memb_300__conf_13 1 8 1 1 ap_clk 590 1595 1879 0 2 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_scenechange_memb_300__conf_15 1 8 3 1 ap_clk 598 2132 2838 0 2 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_scenechange_memb_300__conf_19 1 8 7 1 ap_clk 555 2811 4532 0 2 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_scenechange_strm_300__conf_02 1 10 1 0 ap_clk 683 1096 1312 0 0 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_scenechange_strm_300__conf_08 2 16 1 0 ap_clk 615 1808 2155 0 0 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_scenechange_strm_300__conf_11 4 12 1 0 ap_clk 641 2855 2855 0 0 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_scenechange_strm_300__conf_12 4 16 1 0 ap_clk 641 3405 3369 0 0 0 PRODUCTION 1.30 05-15-2022

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