Performance and Resource Utilization for Viterbi Decoder v9.1

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2026.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_par_ch1	Standard	1	Parallel	U0/aclk=281	aclk	281	2208	1720	0	2	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=363	aclk	363	2274	3518	0	2	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_ser_ch1	Standard	1	Serial	U0/aclk=358	aclk	358	1339	1931	0	2	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_par_ch1	Standard	1	Parallel	U0/aclk=347	aclk	347	2266	1743	0	2	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=456	aclk	456	2018	3519	0	2	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_ser_ch1	Standard	1	Serial	U0/aclk=456	aclk	456	1367	1955	0	2	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_par_ch1	Standard	1	Parallel	U0/aclk=516	aclk	516	2279	1750	0	2	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=571	aclk	571	2159	3520	0	2	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_ser_ch1	Standard	1	Serial	U0/aclk=571	aclk	571	1474	1943	0	2	0	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	Ultra RAMs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_par_ch1	Standard	1	Parallel	U0/aclk=429	aclk	429	2130	1806	0	0	2	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=494	aclk	494	2003	3524	0	0	2	0	PRODUCTION 2.15 2026-03-17
xcvc1902	vsva2197	1LP	ver_1_ser_ch1	Standard	1	Serial	U0/aclk=472	aclk	472	1272	1879	0	0	2	0	PRODUCTION 2.15 2026-03-17

Virtex-7

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_par_ch1	Standard	1	Parallel	U0/aclk=286	aclk	286	2265	1720	0	2	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=358	aclk	358	2273	3519	0	2	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_ser_ch1	Standard	1	Serial	U0/aclk=369	aclk	369	1352	1932	0	2	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_par_ch1	Standard	1	Parallel	U0/aclk=363	aclk	363	2284	1745	0	2	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=456	aclk	456	2019	3556	0	2	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_ser_ch1	Standard	1	Serial	U0/aclk=450	aclk	450	1369	2089	0	2	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_par_ch1	Standard	1	Parallel	U0/aclk=522	aclk	522	2293	1755	0	2	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=571	aclk	571	2157	3655	0	2	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_ser_ch1	Standard	1	Serial	U0/aclk=571	aclk	571	1480	1995	0	2	0	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Viterbi_Type	Channels	Architecture	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_par_ch1	Standard	1	Parallel	U0/aclk=402	aclk	402	2252	1719	0	2	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_par_ch3	Multi_Channel	3	Parallel	U0/aclk=456	aclk	456	2015	3519	0	2	0	PRODUCTION 1.31 12-08-2025
xczu9eg	ffvb1156	1LV	zup_1_ser_ch1	Standard	1	Serial	U0/aclk=456	aclk	456	1363	1937	0	2	0	PRODUCTION 1.31 12-08-2025

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