Resource Utilization for 10G/25G Ethernet Subsystem v5.1

Vivado Design Suite Release 2026.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CORE
LINE_RATE
NUM_OF_CORES
DATA_PATH_INTERFACE
BASE_R_KR
INCLUDE_FEC_LOGIC
INCLUDE_RSFEC_LOGIC
INCLUDE_AUTO_NEG_LT_LOGIC
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
ENABLE_TIME_STAMPING
PTP_OPERATION_MODE
GT_LOCATION
GT_REF_CLK_FREQ
GT_TYPE
ENABLE_PIPELINE_REG
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffve1517 2 test_usplus_2_10 10 1 1 0 1 0 1 5969 6855 0 4 0 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 test_usplus_2_25 25 1 1 0 1 0 1 5996 6862 0 4 0 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_mac_pcs_anlt_rsfec Ethernet MAC+PCS/PMA 64-bit 25 1 Include AN/LT Logic 1 0 0 1 20265 19009 0 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_mac_pcs_nofec_anlt Ethernet MAC+PCS/PMA 64-bit 25 Include AN/LT Logic 1 0 0 1 10563 10970 0 4 0 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_mac_pcs_rsfec Ethernet MAC+PCS/PMA 64-bit 25 1 1 0 0 1 15702 14889 0 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_pcs_nofec Ethernet PCS/PMA 64-bit 25 1 0 0 1 2865 4894 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_pcs_nofec_anlt Ethernet PCS/PMA 64-bit 25 Include AN/LT Logic 1 0 0 1 7503 9004 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_pcs_rsfec Ethernet PCS/PMA 64-bit 25 1 1 0 0 1 12729 13388 0 0 4 PRODUCTION 1.29 05-01-2022
xcku11p ffve1517 2 usplus_pcs_rsfec_anlt Ethernet PCS/PMA 64-bit 25 1 Include AN/LT Logic 1 0 0 1 17365 17495 0 0 4 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CORE
LINE_RATE
NUM_OF_CORES
DATA_PATH_INTERFACE
BASE_R_KR
INCLUDE_FEC_LOGIC
INCLUDE_RSFEC_LOGIC
INCLUDE_AUTO_NEG_LT_LOGIC
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
ENABLE_TIME_STAMPING
PTP_OPERATION_MODE
GT_LOCATION
GT_REF_CLK_FREQ
GT_TYPE
ENABLE_PIPELINE_REG
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP test_versal_vsl_1LP_10 10 1 1 0 1 0 1 5617 7154 0 0 4 0 PRODUCTION 2.15 2026-03-17
xcvc1902 vsva2197 1LP test_versal_vsl_1LP_25 25 1 1 0 1 0 1 6126 7181 0 0 4 0 PRODUCTION 2.15 2026-03-17
xcvc1902 vsva2197 2MP test_versal_vsl_2MP_10 10 1 1 0 1 0 1 5614 7232 0 0 4 0 PRODUCTION 2.15 2026-03-17
xcvc1902 vsva2197 2MP test_versal_vsl_2MP_25 25 1 1 0 1 0 1 5844 7156 0 0 4 0 PRODUCTION 2.15 2026-03-17
xcvp1802 lsvc4072 2MP versal_mac_pcs_10G_anlt 10 BASE-R Include AN/LT Logic 156.25 GTM 1 NOT FOUND
xcvp1802 lsvc4072 2MP versal_mac_pcs_25G_anlt 25 BASE-KR Include AN/LT Logic 156.25 GTM 1 NOT FOUND
xcvc1902 vsva2197 2MP versal_mac_pcs_nofec Ethernet MAC+PCS/PMA 64-bit 25 1 0 0 1 5844 7156 0 0 4 0 PRODUCTION 2.15 2026-03-17
xcvc1902 vsva2197 2MP versal_mac_pcs_rsfec Ethernet MAC+PCS/PMA 64-bit 25 1 1 0 0 1 15125 15170 0 0 4 4 PRODUCTION 2.15 2026-03-17
xcvc1902 vsva2197 2MP versal_pcs_nofec Ethernet PCS/PMA 64-bit 25 1 0 0 1 2987 5506 0 0 0 0 PRODUCTION 2.15 2026-03-17
xcvc1902 vsva2197 2MP versal_pcs_rsfec Ethernet PCS/PMA 64-bit 25 1 1 0 0 1 12393 14147 0 0 0 4 PRODUCTION 2.15 2026-03-17

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CORE
LINE_RATE
NUM_OF_CORES
DATA_PATH_INTERFACE
BASE_R_KR
INCLUDE_FEC_LOGIC
INCLUDE_RSFEC_LOGIC
INCLUDE_AUTO_NEG_LT_LOGIC
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
ENABLE_TIME_STAMPING
PTP_OPERATION_MODE
GT_LOCATION
GT_REF_CLK_FREQ
GT_TYPE
ENABLE_PIPELINE_REG
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 2 MAC_KR_1588_2step Ethernet MAC+PCS/PMA 64-bit 10 1 AXI Stream BASE-KR 0 0 1 2 0 4401 5326 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 2 MAC_KR_ANLT Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 Include AN/LT Logic 0 0 7919 6458 0 0 0 PRODUCTION 1.26 12-04-2018

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CORE
LINE_RATE
NUM_OF_CORES
DATA_PATH_INTERFACE
BASE_R_KR
INCLUDE_FEC_LOGIC
INCLUDE_RSFEC_LOGIC
INCLUDE_AUTO_NEG_LT_LOGIC
INCLUDE_AXI4_INTERFACE
INCLUDE_STATISTICS_COUNTERS
ENABLE_TIME_STAMPING
PTP_OPERATION_MODE
GT_LOCATION
GT_REF_CLK_FREQ
GT_TYPE
ENABLE_PIPELINE_REG
ADD_GT_CNTRL_STS_PORTS
INCLUDE_SHARED_LOGIC
FAST_SIM_MODE
LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV test_usplus_1LV_10 10 1 1 0 1 0 1 5971 6855 0 4 0 PRODUCTION 1.31 12-08-2025
xczu11eg ffvc1760 1L test_usplus_1L_25 25 1 1 0 1 0 1 6060 6862 0 4 0 PRODUCTION 1.31 12-08-2025

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