BSCAN_BSCAN
- JTAG_CHAIN=[1:1]
- JTAG_TEST=[0:1]
BUFGMUX
BUFGMUX_BUFGMUX
- CLK_SEL_TYPE=[SYNC:3]
- DISABLE_ATTR=[LOW:3]
- S=[S_INV:1] [S:2]
BUFIO2FB_BUFIO2FB
- DIVIDE_BYPASS=[TRUE:1]
- INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
- DIVIDE=[1:2]
- DIVIDE_BYPASS=[TRUE:2]
- I_INVERT=[FALSE:2]
BUFPLL_MCB_BUFPLL_MCB
- DIVIDE=[2:1]
- LOCK_SRC=[LOCK_TO_0:1]
DCM
- PSCLK=[PSCLK_INV:0] [PSCLK:1]
- PSEN=[PSEN_INV:0] [PSEN:1]
- PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
- RST=[RST:1] [RST_INV:0]
DCM_DCM
- CLKDV_DIVIDE=[2.0:1]
- CLKIN_DIVIDE_BY_2=[FALSE:1]
- CLKOUT_PHASE_SHIFT=[NONE:1]
- CLK_FEEDBACK=[1X:1]
- DESKEW_ADJUST=[5:1]
- DFS_FREQUENCY_MODE=[LOW:1]
- DLL_FREQUENCY_MODE=[LOW:1]
- DSS_MODE=[NONE:1]
- DUTY_CYCLE_CORRECTION=[TRUE:1]
- PSCLK=[PSCLK_INV:0] [PSCLK:1]
- PSEN=[PSEN_INV:0] [PSEN:1]
- PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
- RST=[RST:1] [RST_INV:0]
- STARTUP_WAIT=[FALSE:1]
- VERY_HIGH_FREQUENCY=[FALSE:1]
FF_SR
- CK=[CK:169] [CK_INV:0]
- SRINIT=[SRINIT0:152] [SRINIT1:17]
- SYNC_ATTR=[ASYNC:150] [SYNC:19]
IOB_INBUF
- DIFF_TERM=[TRUE:1]
- IN_TERM=[NONE:18]
IOB_OUTBUF
IODRP2
- IOCLK0=[IOCLK0_INV:0] [IOCLK0:2]
IODRP2_IODRP2
- COUNTER_WRAPAROUND=[WRAPAROUND:2]
- DATA_RATE=[SDR:2]
- DELAYCHAIN_OSC=[FALSE:2]
- DELAY_SRC=[IO:2]
- IDELAY_MODE=[NORMAL:2]
- IDELAY_TYPE=[DEFAULT:2]
- IOCLK0=[IOCLK0_INV:0] [IOCLK0:2]
- IODELAY_CHANGE=[CHANGE_ON_DATA:2]
- SERDES_MODE=[NONE:2]
- TEST_GLITCH_FILTER=[FALSE:2]
IODRP2_MCB
- IOCLK0=[IOCLK0_INV:0] [IOCLK0:22]
IODRP2_MCB_IODRP2_MCB
- DATA_RATE=[SDR:22]
- IOCLK0=[IOCLK0_INV:0] [IOCLK0:22]
- SERDES_MODE=[SLAVE:11] [MASTER:11]
LUT_OR_MEM6
- CLK=[CLK:1] [CLK_INV:0]
- LUT_OR_MEM=[RAM:1]
- RAMMODE=[SRL16:1]
MCB
- P0CMDCLK=[P0CMDCLK:1] [P0CMDCLK_INV:0]
- P0CMDEN=[P0CMDEN:1] [P0CMDEN_INV:0]
- P0RDCLK=[P0RDCLK:1] [P0RDCLK_INV:0]
- P0RDEN=[P0RDEN_INV:0] [P0RDEN:1]
- P0WRCLK=[P0WRCLK_INV:0] [P0WRCLK:1]
- P0WREN=[P0WREN_INV:0] [P0WREN:1]
- P1CMDCLK=[P1CMDCLK:1] [P1CMDCLK_INV:0]
- P1CMDEN=[P1CMDEN_INV:0] [P1CMDEN:1]
- P1RDCLK=[P1RDCLK_INV:0] [P1RDCLK:1]
- P1RDEN=[P1RDEN:1] [P1RDEN_INV:0]
- P1WRCLK=[P1WRCLK_INV:0] [P1WRCLK:1]
- P1WREN=[P1WREN:1] [P1WREN_INV:0]
- P2CLK=[P2CLK:1] [P2CLK_INV:0]
- P2CMDCLK=[P2CMDCLK_INV:0] [P2CMDCLK:1]
- P2CMDEN=[P2CMDEN:1] [P2CMDEN_INV:0]
- P2EN=[P2EN:1] [P2EN_INV:0]
- P3CLK=[P3CLK:1] [P3CLK_INV:0]
- P3CMDCLK=[P3CMDCLK_INV:0] [P3CMDCLK:1]
- P3CMDEN=[P3CMDEN_INV:0] [P3CMDEN:1]
- P3EN=[P3EN_INV:0] [P3EN:1]
- P4CLK=[P4CLK_INV:0] [P4CLK:1]
- P4CMDCLK=[P4CMDCLK_INV:0] [P4CMDCLK:1]
- P4CMDEN=[P4CMDEN_INV:0] [P4CMDEN:1]
- P4EN=[P4EN_INV:0] [P4EN:1]
- P5CLK=[P5CLK_INV:0] [P5CLK:1]
- P5CMDCLK=[P5CMDCLK_INV:0] [P5CMDCLK:1]
- P5CMDEN=[P5CMDEN:1] [P5CMDEN_INV:0]
- P5EN=[P5EN_INV:0] [P5EN:1]
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MCB_MCB
- ARB_NUM_TIME_SLOTS=[12:1]
- CAL_BYPASS=[NO:1]
- CAL_CALIBRATION_MODE=[NOCALIBRATION:1]
- CAL_CLK_DIV=[1:1]
- CAL_DELAY=[HALF:1]
- MEM_ADDR_ORDER=[ROW_BANK_COLUMN:1]
- MEM_BA_SIZE=[3:1]
- MEM_BURST_LEN=[8:1]
- MEM_CAS_LATENCY=[5:1]
- MEM_CA_SIZE=[10:1]
- MEM_DDR1_2_ODS=[FULL:1]
- MEM_DDR2_3_HIGH_TEMP_SR=[NORMAL:1]
- MEM_DDR2_3_PA_SR=[FULL:1]
- MEM_DDR2_ADD_LATENCY=[0:1]
- MEM_DDR2_DIFF_DQS_EN=[YES:1]
- MEM_DDR2_RTT=[50OHMS:1]
- MEM_DDR2_WRT_RECOVERY=[5:1]
- MEM_DDR3_ADD_LATENCY=[OFF:1]
- MEM_DDR3_AUTO_SR=[ENABLED:1]
- MEM_DDR3_CAS_LATENCY=[6:1]
- MEM_DDR3_CAS_WR_LATENCY=[5:1]
- MEM_DDR3_DYN_WRT_ODT=[OFF:1]
- MEM_DDR3_ODS=[DIV6:1]
- MEM_DDR3_RTT=[DIV2:1]
- MEM_DDR3_WRT_RECOVERY=[5:1]
- MEM_MDDR_ODS=[FULL:1]
- MEM_MOBILE_PA_SR=[FULL:1]
- MEM_MOBILE_TC_SR=[0:1]
- MEM_RAS_VAL=[15:1]
- MEM_RA_SIZE=[13:1]
- MEM_RCD_VAL=[5:1]
- MEM_RTP_VAL=[3:1]
- MEM_TYPE=[DDR2:1]
- MEM_WIDTH=[16:1]
- MEM_WR_VAL=[5:1]
- MEM_WTR_VAL=[3:1]
- P0CMDCLK=[P0CMDCLK:1] [P0CMDCLK_INV:0]
- P0CMDEN=[P0CMDEN:1] [P0CMDEN_INV:0]
- P0RDCLK=[P0RDCLK:1] [P0RDCLK_INV:0]
- P0RDEN=[P0RDEN_INV:0] [P0RDEN:1]
- P0WRCLK=[P0WRCLK_INV:0] [P0WRCLK:1]
- P0WREN=[P0WREN_INV:0] [P0WREN:1]
- P1CMDCLK=[P1CMDCLK:1] [P1CMDCLK_INV:0]
- P1CMDEN=[P1CMDEN_INV:0] [P1CMDEN:1]
- P1RDCLK=[P1RDCLK_INV:0] [P1RDCLK:1]
- P1RDEN=[P1RDEN:1] [P1RDEN_INV:0]
- P1WRCLK=[P1WRCLK_INV:0] [P1WRCLK:1]
- P1WREN=[P1WREN:1] [P1WREN_INV:0]
- P2CLK=[P2CLK:1] [P2CLK_INV:0]
- P2CMDCLK=[P2CMDCLK_INV:0] [P2CMDCLK:1]
- P2CMDEN=[P2CMDEN:1] [P2CMDEN_INV:0]
- P2EN=[P2EN:1] [P2EN_INV:0]
- P3CLK=[P3CLK:1] [P3CLK_INV:0]
- P3CMDCLK=[P3CMDCLK_INV:0] [P3CMDCLK:1]
- P3CMDEN=[P3CMDEN_INV:0] [P3CMDEN:1]
- P3EN=[P3EN_INV:0] [P3EN:1]
- P4CLK=[P4CLK_INV:0] [P4CLK:1]
- P4CMDCLK=[P4CMDCLK_INV:0] [P4CMDCLK:1]
- P4CMDEN=[P4CMDEN_INV:0] [P4CMDEN:1]
- P4EN=[P4EN_INV:0] [P4EN:1]
- P5CLK=[P5CLK_INV:0] [P5CLK:1]
- P5CMDCLK=[P5CMDCLK_INV:0] [P5CMDCLK:1]
- P5CMDEN=[P5CMDEN:1] [P5CMDEN_INV:0]
- P5EN=[P5EN_INV:0] [P5EN:1]
- PORT_CONFIG=[B128:1]
OSERDES2
- CLK0=[CLK0_INV:0] [CLK0:45]
OSERDES2_OSERDES2
- BYPASS_GCLK_FF=[TRUE:45]
- CLK0=[CLK0_INV:0] [CLK0:45]
- DATA_RATE_OQ=[SDR:45]
- DATA_RATE_OT=[SDR:45]
- DATA_WIDTH=[2:45]
- OUTPUT_MODE=[SINGLE_ENDED:43] [DIFFERENTIAL:2]
- SERDES_MODE=[SLAVE:3] [MASTER:42]
- TRAIN_PATTERN=[0:28] [5:16] [15:1]
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PLL_ADV
PLL_ADV_PLL_ADV
- BANDWIDTH=[OPTIMIZED:1]
- CLK_FEEDBACK=[CLKFBOUT:1]
- COMPENSATION=[INTERNAL:1]
- PLL_ADD_LEAKAGE=[2:1]
- PLL_AVDD_COMP_SET=[2:1]
- PLL_CLAMP_BYPASS=[FALSE:1]
- PLL_CLAMP_REF_SEL=[1:1]
- PLL_CLK0MX=[0:1]
- PLL_CLK1MX=[0:1]
- PLL_CLK2MX=[0:1]
- PLL_CLK3MX=[0:1]
- PLL_CLK4MX=[0:1]
- PLL_CLK5MX=[0:1]
- PLL_CLKBURST_CNT=[0:1]
- PLL_CLKBURST_ENABLE=[TRUE:1]
- PLL_CLKCNTRL=[0:1]
- PLL_CLKFBMX=[0:1]
- PLL_CLKFBOUT2_EDGE=[TRUE:1]
- PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
- PLL_CLKFBOUT_EDGE=[TRUE:1]
- PLL_CLKFBOUT_EN=[FALSE:1]
- PLL_CLKFBOUT_NOCOUNT=[TRUE:1]
- PLL_CLKOUT0_EDGE=[TRUE:1]
- PLL_CLKOUT0_EN=[FALSE:1]
- PLL_CLKOUT0_NOCOUNT=[TRUE:1]
- PLL_CLKOUT1_EDGE=[TRUE:1]
- PLL_CLKOUT1_EN=[FALSE:1]
- PLL_CLKOUT1_NOCOUNT=[TRUE:1]
- PLL_CLKOUT2_EDGE=[TRUE:1]
- PLL_CLKOUT2_EN=[FALSE:1]
- PLL_CLKOUT2_NOCOUNT=[TRUE:1]
- PLL_CLKOUT3_EDGE=[TRUE:1]
- PLL_CLKOUT3_EN=[FALSE:1]
- PLL_CLKOUT3_NOCOUNT=[TRUE:1]
- PLL_CLKOUT4_EDGE=[TRUE:1]
- PLL_CLKOUT4_EN=[FALSE:1]
- PLL_CLKOUT4_NOCOUNT=[TRUE:1]
- PLL_CLKOUT5_EDGE=[TRUE:1]
- PLL_CLKOUT5_EN=[FALSE:1]
- PLL_CLKOUT5_NOCOUNT=[TRUE:1]
- PLL_CLK_LOST_DETECT=[FALSE:1]
- PLL_CP=[1:1]
- PLL_CP_BIAS_TRIP_SHIFT=[TRUE:1]
- PLL_CP_REPL=[1:1]
- PLL_CP_RES=[0:1]
- PLL_DIRECT_PATH_CNTRL=[TRUE:1]
- PLL_DIVCLK_EDGE=[TRUE:1]
- PLL_DIVCLK_NOCOUNT=[TRUE:1]
- PLL_DVDD_COMP_SET=[2:1]
- PLL_EN=[FALSE:1]
- PLL_EN_DLY=[TRUE:1]
- PLL_EN_LEAKAGE=[2:1]
- PLL_EN_TCLK0=[TRUE:1]
- PLL_EN_TCLK1=[TRUE:1]
- PLL_EN_TCLK2=[TRUE:1]
- PLL_EN_TCLK3=[TRUE:1]
- PLL_EN_VCO0=[FALSE:1]
- PLL_EN_VCO1=[FALSE:1]
- PLL_EN_VCO2=[FALSE:1]
- PLL_EN_VCO3=[FALSE:1]
- PLL_EN_VCO4=[FALSE:1]
- PLL_EN_VCO5=[FALSE:1]
- PLL_EN_VCO6=[FALSE:1]
- PLL_EN_VCO7=[FALSE:1]
- PLL_EN_VCO_DIV1=[FALSE:1]
- PLL_EN_VCO_DIV6=[TRUE:1]
- PLL_INTFB=[0:1]
- PLL_IO_CLKSRC=[0:1]
- PLL_LFHF=[3:1]
- PLL_LOCK_FB_DLY=[3:1]
- PLL_LOCK_REF_DLY=[5:1]
- PLL_MAN_LF_EN=[TRUE:1]
- PLL_NBTI_EN=[TRUE:1]
- PLL_PFD_CNTRL=[8:1]
- PLL_PFD_DLY=[1:1]
- PLL_PWRD_CFG=[FALSE:1]
- PLL_REG_INPUT=[TRUE:1]
- PLL_RES=[1:1]
- PLL_SEL_SLIPD=[FALSE:1]
- PLL_SKEW_CNTRL=[0:1]
- PLL_TEST_IN_WINDOW=[FALSE:1]
- PLL_VDD_SEL=[0:1]
- PLL_VLFHIGH_DIS=[TRUE:1]
- RST=[RST:1] [RST_INV:0]
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PULL_OR_KEEP1
- PULLTYPE=[PULLUP:2] [PULLDOWN:2]
RAMB16BWER
- CLKA=[CLKA_INV:0] [CLKA:2]
- CLKB=[CLKB_INV:0] [CLKB:2]
- ENA=[ENA_INV:0] [ENA:2]
- ENB=[ENB_INV:0] [ENB:2]
- REGCEA=[REGCEA_INV:0] [REGCEA:2]
- REGCEB=[REGCEB_INV:0] [REGCEB:2]
- RSTA=[RSTA:2] [RSTA_INV:0]
- RSTB=[RSTB:2] [RSTB_INV:0]
- WEA0=[WEA0:2] [WEA0_INV:0]
- WEA1=[WEA1:2] [WEA1_INV:0]
- WEA2=[WEA2:2] [WEA2_INV:0]
- WEA3=[WEA3_INV:0] [WEA3:2]
- WEB0=[WEB0:2] [WEB0_INV:0]
- WEB1=[WEB1:2] [WEB1_INV:0]
- WEB2=[WEB2_INV:0] [WEB2:2]
- WEB3=[WEB3:2] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
- CLKA=[CLKA_INV:0] [CLKA:2]
- CLKB=[CLKB_INV:0] [CLKB:2]
- DATA_WIDTH_A=[1:1] [36:1]
- DATA_WIDTH_B=[1:1] [36:1]
- DOA_REG=[0:2]
- DOB_REG=[0:1] [1:1]
- ENA=[ENA_INV:0] [ENA:2]
- ENB=[ENB_INV:0] [ENB:2]
- EN_RSTRAM_A=[TRUE:2]
- EN_RSTRAM_B=[TRUE:2]
- RAM_MODE=[TDP:2]
- REGCEA=[REGCEA_INV:0] [REGCEA:2]
- REGCEB=[REGCEB_INV:0] [REGCEB:2]
- RSTA=[RSTA:2] [RSTA_INV:0]
- RSTB=[RSTB:2] [RSTB_INV:0]
- RSTTYPE=[SYNC:2]
- RST_PRIORITY_A=[CE:2]
- RST_PRIORITY_B=[CE:2]
- WEA0=[WEA0:2] [WEA0_INV:0]
- WEA1=[WEA1:2] [WEA1_INV:0]
- WEA2=[WEA2:2] [WEA2_INV:0]
- WEA3=[WEA3_INV:0] [WEA3:2]
- WEB0=[WEB0:2] [WEB0_INV:0]
- WEB1=[WEB1:2] [WEB1_INV:0]
- WEB2=[WEB2_INV:0] [WEB2:2]
- WEB3=[WEB3:2] [WEB3_INV:0]
- WRITE_MODE_A=[WRITE_FIRST:2]
- WRITE_MODE_B=[WRITE_FIRST:2]
REG_SR
- CK=[CK:670] [CK_INV:0]
- LATCH_OR_FF=[FF:670]
- SRINIT=[SRINIT0:613] [SRINIT1:57]
- SYNC_ATTR=[ASYNC:521] [SYNC:149]
SLICEL
SLICEM
SLICEX
- CLK=[CLK:203] [CLK_INV:0]
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