===
mig_dut	verilog	mig_hw_tb/mig_inst
---
c3_p0_cmd_en	in			
c3_p0_cmd_instr	in	2	0	
c3_p0_cmd_bl	in	5	0	
c3_p0_cmd_byte_addr	in	29	0	
c3_p0_cmd_empty	out			
c3_p0_cmd_full	out			
c3_p0_wr_en	in			
c3_p0_wr_mask	in	15	0	
c3_p0_wr_data	in	127	0	
c3_p0_wr_full	out			
c3_p0_wr_empty	out			
c3_p0_wr_count	out	6	0	
c3_p0_wr_underrun	out			
c3_p0_wr_error	out			
c3_p0_rd_en	in			
c3_p0_rd_data	out	127	0	
c3_p0_rd_full	out			
c3_p0_rd_empty	out			
c3_p0_rd_count	out	6	0	
c3_p0_rd_overflow	out			
c3_p0_rd_error	out			
c3_sys_rst_n	in			
c3_calib_done	out			
c3_clk0	in			
c3_rst0	out			
c3_sys_clk_p	in			
c3_sys_clk_n	in			
mcb3_dram_dq	inout	15	0	
mcb3_dram_a	out	12	0	
mcb3_dram_ba	out	2	0	
mcb3_dram_ras_n	out			
mcb3_dram_cas_n	out			
mcb3_dram_we_n	out			
mcb3_dram_odt	out			
mcb3_dram_cke	out			
mcb3_dram_dm	out			
mcb3_dram_udqs	inout			
mcb3_dram_udqs_n	inout			
mcb3_rzq	inout			
mcb3_zio	inout			
mcb3_dram_udm	out			
mcb3_dram_dqs	inout			
mcb3_dram_dqs_n	inout			
mcb3_dram_ck	out			
mcb3_dram_ck_n	out			
---
C3_P0_MASK_SIZE				signed	16	parameter
C3_P0_DATA_PORT_SIZE				signed	128	parameter
C3_MEMCLK_PERIOD				signed	3000	parameter
C3_CALIB_SOFT_IP	31	0			"TRUE"	parameter
C3_RST_ACT_LOW				signed	0	parameter
C3_INPUT_CLK_TYPE	95	0			"DIFFERENTIAL"	parameter
C3_MEM_ADDR_ORDER	119	0			"ROW_BANK_COLUMN"	parameter
C3_NUM_DQ_PINS				signed	16	parameter
C3_MEM_ADDR_WIDTH				signed	13	parameter
C3_MEM_BANKADDR_WIDTH				signed	3	parameter
C3_MC_CALIB_BYPASS	15	0			"NO"	parameter
===
mig_dut	verilog	mig_hw_tb/mig_inst
---
c3_p0_cmd_en	in			
c3_p0_cmd_instr	in	2	0	
c3_p0_cmd_bl	in	5	0	
c3_p0_cmd_byte_addr	in	29	0	
c3_p0_cmd_empty	out			
c3_p0_cmd_full	out			
c3_p0_wr_en	in			
c3_p0_wr_mask	in	15	0	
c3_p0_wr_data	in	127	0	
c3_p0_wr_full	out			
c3_p0_wr_empty	out			
c3_p0_wr_count	out	6	0	
c3_p0_wr_underrun	out			
c3_p0_wr_error	out			
c3_p0_rd_en	in			
c3_p0_rd_data	out	127	0	
c3_p0_rd_full	out			
c3_p0_rd_empty	out			
c3_p0_rd_count	out	6	0	
c3_p0_rd_overflow	out			
c3_p0_rd_error	out			
c3_sys_rst_n	in			
c3_calib_done	out			
c3_clk0	in			
c3_rst0	out			
c3_sys_clk_p	in			
c3_sys_clk_n	in			
mcb3_dram_dq	inout	15	0	
mcb3_dram_a	out	12	0	
mcb3_dram_ba	out	2	0	
mcb3_dram_ras_n	out			
mcb3_dram_cas_n	out			
mcb3_dram_we_n	out			
mcb3_dram_odt	out			
mcb3_dram_cke	out			
mcb3_dram_dm	out			
mcb3_dram_udqs	inout			
mcb3_dram_udqs_n	inout			
mcb3_rzq	inout			
mcb3_zio	inout			
mcb3_dram_udm	out			
mcb3_dram_dqs	inout			
mcb3_dram_dqs_n	inout			
mcb3_dram_ck	out			
mcb3_dram_ck_n	out			
---
C3_P0_MASK_SIZE				signed	16	parameter
C3_P0_DATA_PORT_SIZE				signed	128	parameter
C3_MEMCLK_PERIOD				signed	3000	parameter
C3_CALIB_SOFT_IP	31	0			"TRUE"	parameter
C3_RST_ACT_LOW				signed	0	parameter
C3_INPUT_CLK_TYPE	95	0			"DIFFERENTIAL"	parameter
C3_MEM_ADDR_ORDER	119	0			"ROW_BANK_COLUMN"	parameter
C3_NUM_DQ_PINS				signed	16	parameter
C3_MEM_ADDR_WIDTH				signed	13	parameter
C3_MEM_BANKADDR_WIDTH				signed	3	parameter
C3_MC_CALIB_BYPASS	15	0			"NO"	parameter
