===
iodrp_mcb_controller	verilog
---
memcell_address	in	7	0	
write_data	in	7	0	
read_data	out	7	0	
rd_not_write	in			
cmd_valid	in			
rdy_busy_n	out			
use_broadcast	in			
drp_ioi_addr	in	4	0	
sync_rst	in			
DRP_CLK	in			
DRP_CS	out			
DRP_SDI	out			
DRP_ADD	out			
DRP_BKST	out			
DRP_SDO	in			
MCB_UIREAD	out			
---
READY	3	0			4'b0	localparam
DECIDE	3	0			4'b01	localparam
ADDR_PHASE	3	0			4'b010	localparam
ADDR_TO_DATA_GAP	3	0			4'b011	localparam
ADDR_TO_DATA_GAP2	3	0			4'b0100	localparam
ADDR_TO_DATA_GAP3	3	0			4'b0101	localparam
DATA_PHASE	3	0			4'b0110	localparam
ALMOST_READY	3	0			4'b0111	localparam
ALMOST_READY2	3	0			4'b1000	localparam
ALMOST_READY3	3	0			4'b1001	localparam
IOI_DQ0	4	0			5'b01	localparam
IOI_DQ1	4	0			5'b0	localparam
IOI_DQ2	4	0			5'b011	localparam
IOI_DQ3	4	0			5'b010	localparam
IOI_DQ4	4	0			5'b0101	localparam
IOI_DQ5	4	0			5'b0100	localparam
IOI_DQ6	4	0			5'b0111	localparam
IOI_DQ7	4	0			5'b0110	localparam
IOI_DQ8	4	0			5'b01001	localparam
IOI_DQ9	4	0			5'b01000	localparam
IOI_DQ10	4	0			5'b01011	localparam
IOI_DQ11	4	0			5'b01010	localparam
IOI_DQ12	4	0			5'b01101	localparam
IOI_DQ13	4	0			5'b01100	localparam
IOI_DQ14	4	0			5'b01111	localparam
IOI_DQ15	4	0			5'b01110	localparam
IOI_UDQS_CLK	4	0			5'b11101	localparam
IOI_UDQS_PIN	4	0			5'b11100	localparam
IOI_LDQS_CLK	4	0			5'b11111	localparam
IOI_LDQS_PIN	4	0			5'b11110	localparam
===
iodrp_controller	verilog
---
memcell_address	in	7	0	
write_data	in	7	0	
read_data	out	7	0	
rd_not_write	in			
cmd_valid	in			
rdy_busy_n	out			
use_broadcast	in			
sync_rst	in			
DRP_CLK	in			
DRP_CS	out			
DRP_SDI	out			
DRP_ADD	out			
DRP_BKST	out			
DRP_SDO	in			
---
READY	2	0			3'b0	localparam
DECIDE	2	0			3'b01	localparam
ADDR_PHASE	2	0			3'b010	localparam
ADDR_TO_DATA_GAP	2	0			3'b011	localparam
ADDR_TO_DATA_GAP2	2	0			3'b100	localparam
ADDR_TO_DATA_GAP3	2	0			3'b101	localparam
DATA_PHASE	2	0			3'b110	localparam
ALMOST_READY	2	0			3'b111	localparam
IOI_DQ0	4	0			5'b01	localparam
IOI_DQ1	4	0			5'b0	localparam
IOI_DQ2	4	0			5'b011	localparam
IOI_DQ3	4	0			5'b010	localparam
IOI_DQ4	4	0			5'b0101	localparam
IOI_DQ5	4	0			5'b0100	localparam
IOI_DQ6	4	0			5'b0111	localparam
IOI_DQ7	4	0			5'b0110	localparam
IOI_DQ8	4	0			5'b01001	localparam
IOI_DQ9	4	0			5'b01000	localparam
IOI_DQ10	4	0			5'b01011	localparam
IOI_DQ11	4	0			5'b01010	localparam
IOI_DQ12	4	0			5'b01101	localparam
IOI_DQ13	4	0			5'b01100	localparam
IOI_DQ14	4	0			5'b01111	localparam
IOI_DQ15	4	0			5'b01110	localparam
IOI_UDQS_CLK	4	0			5'b11101	localparam
IOI_UDQS_PIN	4	0			5'b11100	localparam
IOI_LDQS_CLK	4	0			5'b11111	localparam
IOI_LDQS_PIN	4	0			5'b11110	localparam
===
mcb_soft_calibration	verilog
---
UI_CLK	in			
RST	in			
DONE_SOFTANDHARD_CAL	out			
PLL_LOCK	in			
SELFREFRESH_REQ	in			
SELFREFRESH_MCB_MODE	in			
SELFREFRESH_MCB_REQ	out			
SELFREFRESH_MODE	out			
IODRP_ADD	out			
IODRP_SDI	out			
RZQ_IN	in			
RZQ_IODRP_SDO	in			
RZQ_IODRP_CS	out			
ZIO_IN	in			
ZIO_IODRP_SDO	in			
ZIO_IODRP_CS	out			
MCB_UIADD	out			
MCB_UISDI	out			
MCB_UOSDO	in			
MCB_UODONECAL	in			
MCB_UOREFRSHFLAG	in			
MCB_UICS	out			
MCB_UIDRPUPDATE	out			
MCB_UIBROADCAST	out			
MCB_UIADDR	out	4	0	
MCB_UICMDEN	out			
MCB_UIDONECAL	out			
MCB_UIDQLOWERDEC	out			
MCB_UIDQLOWERINC	out			
MCB_UIDQUPPERDEC	out			
MCB_UIDQUPPERINC	out			
MCB_UILDQSDEC	out			
MCB_UILDQSINC	out			
MCB_UIREAD	out			
MCB_UIUDQSDEC	out			
MCB_UIUDQSINC	out			
MCB_RECAL	out			
MCB_UICMD	out			
MCB_UICMDIN	out			
MCB_UIDQCOUNT	out	3	0	
MCB_UODATA	in	7	0	
MCB_UODATAVALID	in			
MCB_UOCMDREADY	in			
MCB_UO_CAL_START	in			
MCB_SYSRST	out			
Max_Value	out	7	0	
CKE_Train	out			
---
C_MEM_TZQINIT_MAXCNT	9	0			10'b1000000000	parameter
C_MC_CALIBRATION_MODE	87	0			"CALIBRATION"	parameter
C_SIMULATION	39	0			"FALSE"	parameter
SKIP_IN_TERM_CAL					1'b0	parameter
SKIP_DYNAMIC_CAL					1'b0	parameter
SKIP_DYN_IN_TERM					1'b1	parameter
C_MEM_TYPE	23	0			"DDR"	parameter
IOI_DQ0	4	0			{4'b0,1'b1}	localparam
IOI_DQ1	4	0			{4'b0,1'b0}	localparam
IOI_DQ2	4	0			{4'b01,1'b1}	localparam
IOI_DQ3	4	0			{4'b01,1'b0}	localparam
IOI_DQ4	4	0			{4'b010,1'b1}	localparam
IOI_DQ5	4	0			{4'b010,1'b0}	localparam
IOI_DQ6	4	0			{4'b011,1'b1}	localparam
IOI_DQ7	4	0			{4'b011,1'b0}	localparam
IOI_DQ8	4	0			{4'b0100,1'b1}	localparam
IOI_DQ9	4	0			{4'b0100,1'b0}	localparam
IOI_DQ10	4	0			{4'b0101,1'b1}	localparam
IOI_DQ11	4	0			{4'b0101,1'b0}	localparam
IOI_DQ12	4	0			{4'b0110,1'b1}	localparam
IOI_DQ13	4	0			{4'b0110,1'b0}	localparam
IOI_DQ14	4	0			{4'b0111,1'b1}	localparam
IOI_DQ15	4	0			{4'b0111,1'b0}	localparam
IOI_UDM	4	0			{4'b1000,1'b1}	localparam
IOI_LDM	4	0			{4'b1000,1'b0}	localparam
IOI_CK_P	4	0			{4'b1001,1'b1}	localparam
IOI_CK_N	4	0			{4'b1001,1'b0}	localparam
IOI_RESET	4	0			{4'b1010,1'b1}	localparam
IOI_A11	4	0			{4'b1010,1'b0}	localparam
IOI_WE	4	0			{4'b1011,1'b1}	localparam
IOI_BA2	4	0			{4'b1011,1'b0}	localparam
IOI_BA0	4	0			{4'b1100,1'b1}	localparam
IOI_BA1	4	0			{4'b1100,1'b0}	localparam
IOI_RASN	4	0			{4'b1101,1'b1}	localparam
IOI_CASN	4	0			{4'b1101,1'b0}	localparam
IOI_UDQS_CLK	4	0			{4'b1110,1'b1}	localparam
IOI_UDQS_PIN	4	0			{4'b1110,1'b0}	localparam
IOI_LDQS_CLK	4	0			{4'b1111,1'b1}	localparam
IOI_LDQS_PIN	4	0			{4'b1111,1'b0}	localparam
START	5	0			6'b0	localparam
LOAD_RZQ_NTERM	5	0			6'b01	localparam
WAIT1	5	0			6'b010	localparam
LOAD_RZQ_PTERM	5	0			6'b011	localparam
WAIT2	5	0			6'b0100	localparam
INC_PTERM	5	0			6'b0101	localparam
MULTIPLY_DIVIDE	5	0			6'b0110	localparam
LOAD_ZIO_PTERM	5	0			6'b0111	localparam
WAIT3	5	0			6'b01000	localparam
LOAD_ZIO_NTERM	5	0			6'b01001	localparam
WAIT4	5	0			6'b01010	localparam
INC_NTERM	5	0			6'b01011	localparam
SKEW	5	0			6'b01100	localparam
WAIT_FOR_START_BROADCAST	5	0			6'b01101	localparam
BROADCAST_PTERM	5	0			6'b01110	localparam
WAIT5	5	0			6'b01111	localparam
BROADCAST_NTERM	5	0			6'b010000	localparam
WAIT6	5	0			6'b010001	localparam
OFF_RZQ_PTERM	5	0			6'b010010	localparam
WAIT7	5	0			6'b010011	localparam
OFF_ZIO_NTERM	5	0			6'b010100	localparam
WAIT8	5	0			6'b010101	localparam
RST_DELAY	5	0			6'b010110	localparam
START_DYN_CAL_PRE	5	0			6'b010111	localparam
WAIT_FOR_UODONE	5	0			6'b011000	localparam
LDQS_WRITE_POS_INDELAY	5	0			6'b011001	localparam
LDQS_WAIT1	5	0			6'b011010	localparam
LDQS_WRITE_NEG_INDELAY	5	0			6'b011011	localparam
LDQS_WAIT2	5	0			6'b011100	localparam
UDQS_WRITE_POS_INDELAY	5	0			6'b011101	localparam
UDQS_WAIT1	5	0			6'b011110	localparam
UDQS_WRITE_NEG_INDELAY	5	0			6'b011111	localparam
UDQS_WAIT2	5	0			6'b100000	localparam
START_DYN_CAL	5	0			6'b100001	localparam
WRITE_CALIBRATE	5	0			6'b100010	localparam
WAIT9	5	0			6'b100011	localparam
READ_MAX_VALUE	5	0			6'b100100	localparam
WAIT10	5	0			6'b100101	localparam
ANALYZE_MAX_VALUE	5	0			6'b100110	localparam
FIRST_DYN_CAL	5	0			6'b100111	localparam
INCREMENT	5	0			6'b101000	localparam
DECREMENT	5	0			6'b101001	localparam
DONE	5	0			6'b101010	localparam
RZQ	1	0			2'b0	localparam
ZIO	1	0			2'b01	localparam
MCB_PORT	1	0			2'b11	localparam
WRITE_MODE					1'b0	localparam
READ_MODE					1'b1	localparam
NoOp	7	0			8'b0	localparam
DelayControl	7	0			8'b01	localparam
PosEdgeInDly	7	0			8'b010	localparam
NegEdgeInDly	7	0			8'b011	localparam
PosEdgeOutDly	7	0			8'b0100	localparam
NegEdgeOutDly	7	0			8'b0101	localparam
MiscCtl1	7	0			8'b0110	localparam
MiscCtl2	7	0			8'b0111	localparam
MaxValue	7	0			8'b01000	localparam
PDrive	7	0			8'b10000000	localparam
PTerm	7	0			8'b10000001	localparam
NDrive	7	0			8'b10000010	localparam
NTerm	7	0			8'b10000011	localparam
SlewRateCtl	7	0			8'b10000100	localparam
LVDSControl	7	0			8'b10000101	localparam
MiscControl	7	0			8'b10000110	localparam
InputControl	7	0			8'b10000111	localparam
TestReadback	7	0			8'b10001000	localparam
MULT				signed	7	localparam
DIV				signed	4	localparam
PNSKEW					1'b1	localparam
PSKEW_MULT				signed	9	localparam
PSKEW_DIV				signed	8	localparam
NSKEW_MULT				signed	7	localparam
NSKEW_DIV				signed	8	localparam
DQS_NUMERATOR				signed	3	localparam
DQS_DENOMINATOR				signed	8	localparam
INCDEC_THRESHOLD	7	0			8'b011	localparam
RST_CNT	9	0			10'b010000	localparam
TZQINIT_MAXCNT					(C_MEM_TZQINIT_MAXCNT + RST_CNT)	localparam
===
mcb_soft_calibration_top	verilog
---
UI_CLK	in			
RST	in			
IOCLK	in			
DONE_SOFTANDHARD_CAL	out			
PLL_LOCK	in			
SELFREFRESH_REQ	in			
SELFREFRESH_MCB_MODE	in			
SELFREFRESH_MCB_REQ	out			
SELFREFRESH_MODE	out			
MCB_UIADD	out			
MCB_UISDI	out			
MCB_UOSDO	in			
MCB_UODONECAL	in			
MCB_UOREFRSHFLAG	in			
MCB_UICS	out			
MCB_UIDRPUPDATE	out			
MCB_UIBROADCAST	out			
MCB_UIADDR	out	4	0	
MCB_UICMDEN	out			
MCB_UIDONECAL	out			
MCB_UIDQLOWERDEC	out			
MCB_UIDQLOWERINC	out			
MCB_UIDQUPPERDEC	out			
MCB_UIDQUPPERINC	out			
MCB_UILDQSDEC	out			
MCB_UILDQSINC	out			
MCB_UIREAD	out			
MCB_UIUDQSDEC	out			
MCB_UIUDQSINC	out			
MCB_RECAL	out			
MCB_SYSRST	out			
MCB_UICMD	out			
MCB_UICMDIN	out			
MCB_UIDQCOUNT	out	3	0	
MCB_UODATA	in	7	0	
MCB_UODATAVALID	in			
MCB_UOCMDREADY	in			
MCB_UO_CAL_START	in			
RZQ_Pin	inout			
ZIO_Pin	inout			
CKE_Train	out			
---
C_MEM_TZQINIT_MAXCNT	9	0			10'b0100010010	parameter
C_MC_CALIBRATION_MODE	87	0			"CALIBRATION"	parameter
SKIP_IN_TERM_CAL					1'b0	parameter
SKIP_DYNAMIC_CAL					1'b0	parameter
SKIP_DYN_IN_TERM					1'b0	parameter
C_SIMULATION	39	0			"FALSE"	parameter
C_MEM_TYPE	23	0			"DDR"	parameter
===
mcb_raw_wrapper	verilog
---
sysclk_2x	in			
sysclk_2x_180	in			
pll_ce_0	in			
pll_ce_90	in			
pll_lock	in			
sys_rst	in			
p0_arb_en	in			
p0_cmd_clk	in			
p0_cmd_en	in			
p0_cmd_instr	in	2	0	
p0_cmd_bl	in	5	0	
p0_cmd_byte_addr	in	29	0	
p0_cmd_empty	out			
p0_cmd_full	out			
p0_wr_clk	in			
p0_wr_en	in			
p0_wr_mask	in	(C_P0_MASK_SIZE - 1)	0	
p0_wr_data	in	(C_P0_DATA_PORT_SIZE - 1)	0	
p0_wr_full	out			
p0_wr_empty	out			
p0_wr_count	out	6	0	
p0_wr_underrun	out			
p0_wr_error	out			
p0_rd_clk	in			
p0_rd_en	in			
p0_rd_data	out	(C_P0_DATA_PORT_SIZE - 1)	0	
p0_rd_full	out			
p0_rd_empty	out			
p0_rd_count	out	6	0	
p0_rd_overflow	out			
p0_rd_error	out			
p1_arb_en	in			
p1_cmd_clk	in			
p1_cmd_en	in			
p1_cmd_instr	in	2	0	
p1_cmd_bl	in	5	0	
p1_cmd_byte_addr	in	29	0	
p1_cmd_empty	out			
p1_cmd_full	out			
p1_wr_clk	in			
p1_wr_en	in			
p1_wr_mask	in	(C_P1_MASK_SIZE - 1)	0	
p1_wr_data	in	(C_P1_DATA_PORT_SIZE - 1)	0	
p1_wr_full	out			
p1_wr_empty	out			
p1_wr_count	out	6	0	
p1_wr_underrun	out			
p1_wr_error	out			
p1_rd_clk	in			
p1_rd_en	in			
p1_rd_data	out	(C_P1_DATA_PORT_SIZE - 1)	0	
p1_rd_full	out			
p1_rd_empty	out			
p1_rd_count	out	6	0	
p1_rd_overflow	out			
p1_rd_error	out			
p2_arb_en	in			
p2_cmd_clk	in			
p2_cmd_en	in			
p2_cmd_instr	in	2	0	
p2_cmd_bl	in	5	0	
p2_cmd_byte_addr	in	29	0	
p2_cmd_empty	out			
p2_cmd_full	out			
p2_wr_clk	in			
p2_wr_en	in			
p2_wr_mask	in	3	0	
p2_wr_data	in	31	0	
p2_wr_full	out			
p2_wr_empty	out			
p2_wr_count	out	6	0	
p2_wr_underrun	out			
p2_wr_error	out			
p2_rd_clk	in			
p2_rd_en	in			
p2_rd_data	out	31	0	
p2_rd_full	out			
p2_rd_empty	out			
p2_rd_count	out	6	0	
p2_rd_overflow	out			
p2_rd_error	out			
p3_arb_en	in			
p3_cmd_clk	in			
p3_cmd_en	in			
p3_cmd_instr	in	2	0	
p3_cmd_bl	in	5	0	
p3_cmd_byte_addr	in	29	0	
p3_cmd_empty	out			
p3_cmd_full	out			
p3_wr_clk	in			
p3_wr_en	in			
p3_wr_mask	in	3	0	
p3_wr_data	in	31	0	
p3_wr_full	out			
p3_wr_empty	out			
p3_wr_count	out	6	0	
p3_wr_underrun	out			
p3_wr_error	out			
p3_rd_clk	in			
p3_rd_en	in			
p3_rd_data	out	31	0	
p3_rd_full	out			
p3_rd_empty	out			
p3_rd_count	out	6	0	
p3_rd_overflow	out			
p3_rd_error	out			
p4_arb_en	in			
p4_cmd_clk	in			
p4_cmd_en	in			
p4_cmd_instr	in	2	0	
p4_cmd_bl	in	5	0	
p4_cmd_byte_addr	in	29	0	
p4_cmd_empty	out			
p4_cmd_full	out			
p4_wr_clk	in			
p4_wr_en	in			
p4_wr_mask	in	3	0	
p4_wr_data	in	31	0	
p4_wr_full	out			
p4_wr_empty	out			
p4_wr_count	out	6	0	
p4_wr_underrun	out			
p4_wr_error	out			
p4_rd_clk	in			
p4_rd_en	in			
p4_rd_data	out	31	0	
p4_rd_full	out			
p4_rd_empty	out			
p4_rd_count	out	6	0	
p4_rd_overflow	out			
p4_rd_error	out			
p5_arb_en	in			
p5_cmd_clk	in			
p5_cmd_en	in			
p5_cmd_instr	in	2	0	
p5_cmd_bl	in	5	0	
p5_cmd_byte_addr	in	29	0	
p5_cmd_empty	out			
p5_cmd_full	out			
p5_wr_clk	in			
p5_wr_en	in			
p5_wr_mask	in	3	0	
p5_wr_data	in	31	0	
p5_wr_full	out			
p5_wr_empty	out			
p5_wr_count	out	6	0	
p5_wr_underrun	out			
p5_wr_error	out			
p5_rd_clk	in			
p5_rd_en	in			
p5_rd_data	out	31	0	
p5_rd_full	out			
p5_rd_empty	out			
p5_rd_count	out	6	0	
p5_rd_overflow	out			
p5_rd_error	out			
mcbx_dram_addr	out	(C_MEM_ADDR_WIDTH - 1)	0	
mcbx_dram_ba	out	(C_MEM_BANKADDR_WIDTH - 1)	0	
mcbx_dram_ras_n	out			
mcbx_dram_cas_n	out			
mcbx_dram_we_n	out			
mcbx_dram_cke	out			
mcbx_dram_clk	out			
mcbx_dram_clk_n	out			
mcbx_dram_dq	inout	(C_NUM_DQ_PINS - 1)	0	
mcbx_dram_dqs	inout			
mcbx_dram_dqs_n	inout			
mcbx_dram_udqs	inout			
mcbx_dram_udqs_n	inout			
mcbx_dram_udm	out			
mcbx_dram_ldm	out			
mcbx_dram_odt	out			
mcbx_dram_ddr3_rst	out			
calib_recal	in			
rzq	inout			
zio	inout			
ui_read	in			
ui_add	in			
ui_cs	in			
ui_clk	in			
ui_sdi	in			
ui_addr	in	4	0	
ui_broadcast	in			
ui_drp_update	in			
ui_done_cal	in			
ui_cmd	in			
ui_cmd_in	in			
ui_cmd_en	in			
ui_dqcount	in	3	0	
ui_dq_lower_dec	in			
ui_dq_lower_inc	in			
ui_dq_upper_dec	in			
ui_dq_upper_inc	in			
ui_udqs_inc	in			
ui_udqs_dec	in			
ui_ldqs_inc	in			
ui_ldqs_dec	in			
uo_data	out	7	0	
uo_data_valid	out			
uo_done_cal	out			
uo_cmd_ready_in	out			
uo_refrsh_flag	out			
uo_cal_start	out			
uo_sdo	out			
status	out	31	0	
selfrefresh_enter	in			
selfrefresh_mode	out			
---
C_MEMCLK_PERIOD				signed	2500	parameter
C_PORT_ENABLE	5	0			6'b111111	parameter
C_MEM_ADDR_ORDER	119	0			"BANK_ROW_COLUMN"	parameter
C_ARB_NUM_TIME_SLOTS				signed	12	parameter
C_ARB_TIME_SLOT_0	17	0			18'b01010011100101	parameter
C_ARB_TIME_SLOT_1	17	0			18'b01010011100101000	parameter
C_ARB_TIME_SLOT_2	17	0			18'b010011100101000001	parameter
C_ARB_TIME_SLOT_3	17	0			18'b011100101000001010	parameter
C_ARB_TIME_SLOT_4	17	0			18'b100101000001010011	parameter
C_ARB_TIME_SLOT_5	17	0			18'b101000001010011100	parameter
C_ARB_TIME_SLOT_6	17	0			18'b01010011100101	parameter
C_ARB_TIME_SLOT_7	17	0			18'b01010011100101000	parameter
C_ARB_TIME_SLOT_8	17	0			18'b010011100101000001	parameter
C_ARB_TIME_SLOT_9	17	0			18'b011100101000001010	parameter
C_ARB_TIME_SLOT_10	17	0			18'b100101000001010011	parameter
C_ARB_TIME_SLOT_11	17	0			18'b101000001010011100	parameter
C_PORT_CONFIG	31	0			"B128"	parameter
C_MEM_TRAS				signed	45000	parameter
C_MEM_TRCD				signed	12500	parameter
C_MEM_TREFI				signed	7800	parameter
C_MEM_TRFC				signed	127500	parameter
C_MEM_TRP				signed	12500	parameter
C_MEM_TWR				signed	15000	parameter
C_MEM_TRTP				signed	7500	parameter
C_MEM_TWTR				signed	7500	parameter
C_NUM_DQ_PINS				signed	8	parameter
C_MEM_TYPE	31	0			"DDR3"	parameter
C_MEM_DENSITY	31	0			"512M"	parameter
C_MEM_BURST_LEN				signed	8	parameter
C_MEM_CAS_LATENCY				signed	4	parameter
C_MEM_ADDR_WIDTH				signed	13	parameter
C_MEM_BANKADDR_WIDTH				signed	3	parameter
C_MEM_NUM_COL_BITS				signed	11	parameter
C_MEM_DDR3_CAS_LATENCY				signed	7	parameter
C_MEM_MOBILE_PA_SR	31	0			"FULL"	parameter
C_MEM_DDR1_2_ODS	31	0			"FULL"	parameter
C_MEM_DDR3_ODS	31	0			"DIV6"	parameter
C_MEM_DDR2_RTT	47	0			"50OHMS"	parameter
C_MEM_DDR3_RTT	31	0			"DIV2"	parameter
C_MEM_MDDR_ODS	31	0			"FULL"	parameter
C_MEM_DDR2_DIFF_DQS_EN	23	0			"YES"	parameter
C_MEM_DDR2_3_PA_SR	23	0			"OFF"	parameter
C_MEM_DDR3_CAS_WR_LATENCY				signed	5	parameter
C_MEM_DDR3_AUTO_SR	55	0			"ENABLED"	parameter
C_MEM_DDR2_3_HIGH_TEMP_SR	47	0			"NORMAL"	parameter
C_MEM_DDR3_DYN_WRT_ODT	23	0			"OFF"	parameter
C_MEM_TZQINIT_MAXCNT	9	0			10'b1000000000	parameter
C_MC_CALIB_BYPASS	15	0			"NO"	parameter
C_MC_CALIBRATION_RA	14	0			15'b0	parameter
C_MC_CALIBRATION_BA	2	0			3'b0	parameter
C_CALIB_SOFT_IP	31	0			"TRUE"	parameter
C_SKIP_IN_TERM_CAL					1'b0	parameter
C_SKIP_DYNAMIC_CAL					1'b0	parameter
C_SKIP_DYN_IN_TERM					1'b1	parameter
C_SIMULATION	39	0			"FALSE"	parameter
LDQSP_TAP_DELAY_VAL				signed	0	parameter
UDQSP_TAP_DELAY_VAL				signed	0	parameter
LDQSN_TAP_DELAY_VAL				signed	0	parameter
UDQSN_TAP_DELAY_VAL				signed	0	parameter
DQ0_TAP_DELAY_VAL				signed	0	parameter
DQ1_TAP_DELAY_VAL				signed	0	parameter
DQ2_TAP_DELAY_VAL				signed	0	parameter
DQ3_TAP_DELAY_VAL				signed	0	parameter
DQ4_TAP_DELAY_VAL				signed	0	parameter
DQ5_TAP_DELAY_VAL				signed	0	parameter
DQ6_TAP_DELAY_VAL				signed	0	parameter
DQ7_TAP_DELAY_VAL				signed	0	parameter
DQ8_TAP_DELAY_VAL				signed	0	parameter
DQ9_TAP_DELAY_VAL				signed	0	parameter
DQ10_TAP_DELAY_VAL				signed	0	parameter
DQ11_TAP_DELAY_VAL				signed	0	parameter
DQ12_TAP_DELAY_VAL				signed	0	parameter
DQ13_TAP_DELAY_VAL				signed	0	parameter
DQ14_TAP_DELAY_VAL				signed	0	parameter
DQ15_TAP_DELAY_VAL				signed	0	parameter
C_MC_CALIBRATION_CA	11	0			12'b0	parameter
C_MC_CALIBRATION_CLK_DIV				signed	1	parameter
C_MC_CALIBRATION_MODE	87	0			"CALIBRATION"	parameter
C_MC_CALIBRATION_DELAY	31	0			"HALF"	parameter
C_P0_MASK_SIZE				signed	4	parameter
C_P0_DATA_PORT_SIZE				signed	32	parameter
C_P1_MASK_SIZE				signed	4	parameter
C_P1_DATA_PORT_SIZE				signed	32	parameter
C_OSERDES2_DATA_RATE_OQ	23	0			"SDR"	localparam
C_OSERDES2_DATA_RATE_OT	23	0			"SDR"	localparam
C_OSERDES2_SERDES_MODE_MASTER	47	0			"MASTER"	localparam
C_OSERDES2_SERDES_MODE_SLAVE	39	0			"SLAVE"	localparam
C_OSERDES2_OUTPUT_MODE_SE	95	0			"SINGLE_ENDED"	localparam
C_OSERDES2_OUTPUT_MODE_DIFF	95	0			"DIFFERENTIAL"	localparam
C_BUFPLL_0_LOCK_SRC	71	0			"LOCK_TO_0"	localparam
C_DQ_IODRP2_DATA_RATE	23	0			"SDR"	localparam
C_DQ_IODRP2_SERDES_MODE_MASTER	47	0			"MASTER"	localparam
C_DQ_IODRP2_SERDES_MODE_SLAVE	39	0			"SLAVE"	localparam
C_DQS_IODRP2_DATA_RATE	23	0			"SDR"	localparam
C_DQS_IODRP2_SERDES_MODE_MASTER	47	0			"MASTER"	localparam
C_DQS_IODRP2_SERDES_MODE_SLAVE	39	0			"SLAVE"	localparam
C_MEM_DDR3_ADD_LATENCY	23	0			"OFF"	localparam
C_MEM_DDR2_ADD_LATENCY				signed	0	localparam
C_MEM_MOBILE_TC_SR				signed	0	localparam
arbtimeslot0					{C_ARB_TIME_SLOT_0}	localparam
arbtimeslot1					{C_ARB_TIME_SLOT_1}	localparam
arbtimeslot2					{C_ARB_TIME_SLOT_2}	localparam
arbtimeslot3					{C_ARB_TIME_SLOT_3}	localparam
arbtimeslot4					{C_ARB_TIME_SLOT_4}	localparam
arbtimeslot5					{C_ARB_TIME_SLOT_5}	localparam
arbtimeslot6					{C_ARB_TIME_SLOT_6}	localparam
arbtimeslot7					{C_ARB_TIME_SLOT_7}	localparam
arbtimeslot8					{C_ARB_TIME_SLOT_8}	localparam
arbtimeslot9					{C_ARB_TIME_SLOT_9}	localparam
arbtimeslot10					{C_ARB_TIME_SLOT_10}	localparam
arbtimeslot11					{C_ARB_TIME_SLOT_11}	localparam
MEM_RAS_VAL				signed	(((C_MEM_TRAS + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD)	localparam
MEM_RCD_VAL				signed	(((C_MEM_TRCD + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD)	localparam
MEM_REFI_VAL				signed	(((C_MEM_TREFI + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD)	localparam
MEM_RFC_VAL				signed	(((C_MEM_TRFC + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD)	localparam
MEM_RP_VAL				signed	(((C_MEM_TRP + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD)	localparam
MEM_WR_VAL				signed	(((C_MEM_TWR + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD)	localparam
MEM_RTP_CK				signed	cdiv(C_MEM_TRTP,C_MEMCLK_PERIOD)	localparam
MEM_RTP_VAL				signed	((C_MEM_TYPE == "DDR3") ? ((MEM_RTP_CK < 4) ? 4 : MEM_RTP_CK) : ((MEM_RTP_CK < 2) ? 2 : MEM_RTP_CK))	localparam
MEM_WTR_VAL				signed	((C_MEM_TYPE == "DDR") ? 2 : ((C_MEM_TYPE == "DDR3") ? 4 : ((C_MEM_TYPE == "MDDR") ? C_MEM_TWTR : ((C_MEM_TYPE == "LPDDR") ? C_MEM_TWTR : (((C_MEM_TYPE == "DDR2") && ((((C_MEM_TWTR + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD) > 2)) ? (((C_MEM_TWTR + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD) : ((C_MEM_TYPE == "DDR2") ? 2 : 3))))))	localparam
C_MEM_DDR2_WRT_RECOVERY				signed	((C_MEM_TYPE != "DDR2") ? 5 : (((C_MEM_TWR + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD))	localparam
C_MEM_DDR3_WRT_RECOVERY				signed	((C_MEM_TYPE != "DDR3") ? 5 : (((C_MEM_TWR + C_MEMCLK_PERIOD) - 1) / C_MEMCLK_PERIOD))	localparam
===
memc3_wrapper	verilog
---
sysclk_2x	in			
sysclk_2x_180	in			
pll_ce_0	in			
pll_ce_90	in			
pll_lock	in			
async_rst	in			
p0_cmd_clk	in			
p0_cmd_en	in			
p0_cmd_instr	in	2	0	
p0_cmd_bl	in	5	0	
p0_cmd_byte_addr	in	29	0	
p0_cmd_empty	out			
p0_cmd_full	out			
p0_wr_clk	in			
p0_wr_en	in			
p0_wr_mask	in	(C_P0_MASK_SIZE - 1)	0	
p0_wr_data	in	(C_P0_DATA_PORT_SIZE - 1)	0	
p0_wr_full	out			
p0_wr_empty	out			
p0_wr_count	out	6	0	
p0_wr_underrun	out			
p0_wr_error	out			
p0_rd_clk	in			
p0_rd_en	in			
p0_rd_data	out	(C_P0_DATA_PORT_SIZE - 1)	0	
p0_rd_full	out			
p0_rd_empty	out			
p0_rd_count	out	6	0	
p0_rd_overflow	out			
p0_rd_error	out			
mcb3_dram_dq	inout	(C_NUM_DQ_PINS - 1)	0	
mcb3_dram_a	out	(C_MEM_ADDR_WIDTH - 1)	0	
mcb3_dram_ba	out	(C_MEM_BANKADDR_WIDTH - 1)	0	
mcb3_dram_ras_n	out			
mcb3_dram_cas_n	out			
mcb3_dram_we_n	out			
mcb3_dram_odt	out			
mcb3_dram_cke	out			
mcb3_dram_dqs	inout			
mcb3_dram_dqs_n	inout			
mcb3_dram_ck	out			
mcb3_dram_ck_n	out			
mcb3_dram_udqs	inout			
mcb3_dram_udm	out			
mcb3_dram_udqs_n	inout			
mcb3_dram_dm	out			
mcb3_rzq	inout			
mcb3_zio	inout			
mcb_drp_clk	in			
calib_done	out			
selfrefresh_enter	in			
selfrefresh_mode	out			
---
C_MEMCLK_PERIOD				signed	3200	parameter
C_P0_MASK_SIZE				signed	16	parameter
C_P0_DATA_PORT_SIZE				signed	128	parameter
C_P1_MASK_SIZE				signed	16	parameter
C_P1_DATA_PORT_SIZE				signed	128	parameter
C_ARB_NUM_TIME_SLOTS				signed	12	parameter
C_ARB_TIME_SLOT_0	2	0			3'b0	parameter
C_ARB_TIME_SLOT_1	2	0			3'b0	parameter
C_ARB_TIME_SLOT_2	2	0			3'b0	parameter
C_ARB_TIME_SLOT_3	2	0			3'b0	parameter
C_ARB_TIME_SLOT_4	2	0			3'b0	parameter
C_ARB_TIME_SLOT_5	2	0			3'b0	parameter
C_ARB_TIME_SLOT_6	2	0			3'b0	parameter
C_ARB_TIME_SLOT_7	2	0			3'b0	parameter
C_ARB_TIME_SLOT_8	2	0			3'b0	parameter
C_ARB_TIME_SLOT_9	2	0			3'b0	parameter
C_ARB_TIME_SLOT_10	2	0			3'b0	parameter
C_ARB_TIME_SLOT_11	2	0			3'b0	parameter
C_MEM_TRAS				signed	45000	parameter
C_MEM_TRCD				signed	12500	parameter
C_MEM_TREFI				signed	7800000	parameter
C_MEM_TRFC				signed	127500	parameter
C_MEM_TRP				signed	12500	parameter
C_MEM_TWR				signed	15000	parameter
C_MEM_TRTP				signed	7500	parameter
C_MEM_TWTR				signed	7500	parameter
C_MEM_ADDR_ORDER	119	0			"ROW_BANK_COLUMN"	parameter
C_NUM_DQ_PINS				signed	16	parameter
C_MEM_TYPE	31	0			"DDR2"	parameter
C_MEM_DENSITY	23	0			"1Gb"	parameter
C_MEM_BURST_LEN				signed	8	parameter
C_MEM_CAS_LATENCY				signed	5	parameter
C_MEM_ADDR_WIDTH				signed	13	parameter
C_MEM_BANKADDR_WIDTH				signed	3	parameter
C_MEM_NUM_COL_BITS				signed	10	parameter
C_MEM_DDR1_2_ODS	31	0			"FULL"	parameter
C_MEM_DDR2_RTT	47	0			"50OHMS"	parameter
C_MEM_DDR2_DIFF_DQS_EN	23	0			"YES"	parameter
C_MEM_DDR2_3_PA_SR	31	0			"FULL"	parameter
C_MEM_DDR2_3_HIGH_TEMP_SR	47	0			"NORMAL"	parameter
C_MEM_DDR3_CAS_LATENCY				signed	7	parameter
C_MEM_DDR3_ODS	31	0			"DIV6"	parameter
C_MEM_DDR3_RTT	31	0			"DIV2"	parameter
C_MEM_DDR3_CAS_WR_LATENCY				signed	5	parameter
C_MEM_DDR3_AUTO_SR	55	0			"ENABLED"	parameter
C_MEM_DDR3_DYN_WRT_ODT	23	0			"OFF"	parameter
C_MEM_MOBILE_PA_SR	31	0			"FULL"	parameter
C_MEM_MDDR_ODS	31	0			"FULL"	parameter
C_MC_CALIB_BYPASS	15	0			"NO"	parameter
C_SIMULATION	39	0			"FALSE"	parameter
C_LDQSP_TAP_DELAY_VAL				signed	16	parameter
C_UDQSP_TAP_DELAY_VAL				signed	16	parameter
C_LDQSN_TAP_DELAY_VAL				signed	16	parameter
C_UDQSN_TAP_DELAY_VAL				signed	16	parameter
C_DQ0_TAP_DELAY_VAL				signed	0	parameter
C_DQ1_TAP_DELAY_VAL				signed	0	parameter
C_DQ2_TAP_DELAY_VAL				signed	0	parameter
C_DQ3_TAP_DELAY_VAL				signed	0	parameter
C_DQ4_TAP_DELAY_VAL				signed	0	parameter
C_DQ5_TAP_DELAY_VAL				signed	0	parameter
C_DQ6_TAP_DELAY_VAL				signed	0	parameter
C_DQ7_TAP_DELAY_VAL				signed	0	parameter
C_DQ8_TAP_DELAY_VAL				signed	0	parameter
C_DQ9_TAP_DELAY_VAL				signed	0	parameter
C_DQ10_TAP_DELAY_VAL				signed	0	parameter
C_DQ11_TAP_DELAY_VAL				signed	0	parameter
C_DQ12_TAP_DELAY_VAL				signed	0	parameter
C_DQ13_TAP_DELAY_VAL				signed	0	parameter
C_DQ14_TAP_DELAY_VAL				signed	0	parameter
C_DQ15_TAP_DELAY_VAL				signed	0	parameter
C_MC_CALIBRATION_MODE	87	0			"CALIBRATION"	parameter
C_MC_CALIBRATION_DELAY	31	0			"HALF"	parameter
C_CALIB_SOFT_IP	31	0			"TRUE"	parameter
C_SKIP_IN_TERM_CAL				signed	0	parameter
C_SKIP_DYNAMIC_CAL				signed	0	parameter
C_PORT_ENABLE	5	0			6'b01	localparam
C_PORT_CONFIG	31	0			"B128"	localparam
ARB_TIME_SLOT_0					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_0[2:0]}	localparam
ARB_TIME_SLOT_1					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_1[2:0]}	localparam
ARB_TIME_SLOT_2					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_2[2:0]}	localparam
ARB_TIME_SLOT_3					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_3[2:0]}	localparam
ARB_TIME_SLOT_4					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_4[2:0]}	localparam
ARB_TIME_SLOT_5					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_5[2:0]}	localparam
ARB_TIME_SLOT_6					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_6[2:0]}	localparam
ARB_TIME_SLOT_7					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_7[2:0]}	localparam
ARB_TIME_SLOT_8					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_8[2:0]}	localparam
ARB_TIME_SLOT_9					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_9[2:0]}	localparam
ARB_TIME_SLOT_10					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_10[2:0]}	localparam
ARB_TIME_SLOT_11					{3'b111,3'b111,3'b111,3'b111,3'b111,C_ARB_TIME_SLOT_11[2:0]}	localparam
C_MC_CALIBRATION_CLK_DIV				signed	1	localparam
C_MEM_TZQINIT_MAXCNT	9	0			10'b1000000000	localparam
C_SKIP_DYN_IN_TERM					1'b1	localparam
C_MC_CALIBRATION_RA	15	0			16'b0	localparam
C_MC_CALIBRATION_BA	3	0			4'b0	localparam
C_MC_CALIBRATION_CA	11	0			12'b0	localparam
===
memc3_infrastructure	verilog
---
sys_clk_p	in			
sys_clk_n	in			
sys_clk	in			
sys_rst_n	in			
clk0	out			
rst0	out			
async_rst	out			
sysclk_2x	out			
sysclk_2x_180	out			
mcb_drp_clk	out			
pll_ce_0	out			
pll_ce_90	out			
pll_lock	out			
---
C_MEMCLK_PERIOD				signed	2500	parameter
C_RST_ACT_LOW				signed	1	parameter
C_INPUT_CLK_TYPE	95	0			"DIFFERENTIAL"	parameter
C_CLKOUT0_DIVIDE				signed	1	parameter
C_CLKOUT1_DIVIDE				signed	1	parameter
C_CLKOUT2_DIVIDE				signed	16	parameter
C_CLKOUT3_DIVIDE				signed	8	parameter
C_CLKFBOUT_MULT				signed	2	parameter
C_DIVCLK_DIVIDE				signed	1	parameter
RST_SYNC_NUM				signed	25	localparam
CLK_PERIOD_NS				signed	(C_MEMCLK_PERIOD / 1000.0)	localparam
CLK_PERIOD_INT				signed	(C_MEMCLK_PERIOD / 1000)	localparam
===
mig	verilog
---
mcb3_dram_dq	inout	(C3_NUM_DQ_PINS - 1)	0	
mcb3_dram_a	out	(C3_MEM_ADDR_WIDTH - 1)	0	
mcb3_dram_ba	out	(C3_MEM_BANKADDR_WIDTH - 1)	0	
mcb3_dram_ras_n	out			
mcb3_dram_cas_n	out			
mcb3_dram_we_n	out			
mcb3_dram_odt	out			
mcb3_dram_cke	out			
mcb3_dram_dm	out			
mcb3_dram_udqs	inout			
mcb3_dram_udqs_n	inout			
mcb3_rzq	inout			
mcb3_zio	inout			
mcb3_dram_udm	out			
c3_sys_clk_p	in			
c3_sys_clk_n	in			
c3_sys_rst_n	in			
c3_calib_done	out			
c3_clk0	out			
c3_rst0	out			
mcb3_dram_dqs	inout			
mcb3_dram_dqs_n	inout			
mcb3_dram_ck	out			
mcb3_dram_ck_n	out			
c3_p0_cmd_clk	in			
c3_p0_cmd_en	in			
c3_p0_cmd_instr	in	2	0	
c3_p0_cmd_bl	in	5	0	
c3_p0_cmd_byte_addr	in	29	0	
c3_p0_cmd_empty	out			
c3_p0_cmd_full	out			
c3_p0_wr_clk	in			
c3_p0_wr_en	in			
c3_p0_wr_mask	in	(C3_P0_MASK_SIZE - 1)	0	
c3_p0_wr_data	in	(C3_P0_DATA_PORT_SIZE - 1)	0	
c3_p0_wr_full	out			
c3_p0_wr_empty	out			
c3_p0_wr_count	out	6	0	
c3_p0_wr_underrun	out			
c3_p0_wr_error	out			
c3_p0_rd_clk	in			
c3_p0_rd_en	in			
c3_p0_rd_data	out	(C3_P0_DATA_PORT_SIZE - 1)	0	
c3_p0_rd_full	out			
c3_p0_rd_empty	out			
c3_p0_rd_count	out	6	0	
c3_p0_rd_overflow	out			
c3_p0_rd_error	out			
---
C3_P0_MASK_SIZE				signed	16	parameter
C3_P0_DATA_PORT_SIZE				signed	128	parameter
DEBUG_EN				signed	0	parameter
C3_MEMCLK_PERIOD				signed	3200	parameter
C3_CALIB_SOFT_IP	31	0			"TRUE"	parameter
C3_SIMULATION	39	0			"FALSE"	parameter
C3_RST_ACT_LOW				signed	0	parameter
C3_INPUT_CLK_TYPE	95	0			"DIFFERENTIAL"	parameter
C3_MEM_ADDR_ORDER	119	0			"ROW_BANK_COLUMN"	parameter
C3_NUM_DQ_PINS				signed	16	parameter
C3_MEM_ADDR_WIDTH				signed	13	parameter
C3_MEM_BANKADDR_WIDTH				signed	3	parameter
C3_CLKOUT0_DIVIDE				signed	1	localparam
C3_CLKOUT1_DIVIDE				signed	1	localparam
C3_CLKOUT2_DIVIDE				signed	16	localparam
C3_CLKOUT3_DIVIDE				signed	8	localparam
C3_CLKFBOUT_MULT				signed	2	localparam
C3_DIVCLK_DIVIDE				signed	1	localparam
C3_ARB_NUM_TIME_SLOTS				signed	12	localparam
C3_ARB_TIME_SLOT_0	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_1	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_2	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_3	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_4	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_5	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_6	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_7	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_8	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_9	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_10	2	0			3'b0	localparam
C3_ARB_TIME_SLOT_11	2	0			3'b0	localparam
C3_MEM_TRAS				signed	45000	localparam
C3_MEM_TRCD				signed	12500	localparam
C3_MEM_TREFI				signed	7800000	localparam
C3_MEM_TRFC				signed	127500	localparam
C3_MEM_TRP				signed	12500	localparam
C3_MEM_TWR				signed	15000	localparam
C3_MEM_TRTP				signed	7500	localparam
C3_MEM_TWTR				signed	7500	localparam
C3_MEM_TYPE	31	0			"DDR2"	localparam
C3_MEM_DENSITY	23	0			"1Gb"	localparam
C3_MEM_BURST_LEN				signed	8	localparam
C3_MEM_CAS_LATENCY				signed	5	localparam
C3_MEM_NUM_COL_BITS				signed	10	localparam
C3_MEM_DDR1_2_ODS	31	0			"FULL"	localparam
C3_MEM_DDR2_RTT	47	0			"50OHMS"	localparam
C3_MEM_DDR2_DIFF_DQS_EN	23	0			"YES"	localparam
C3_MEM_DDR2_3_PA_SR	31	0			"FULL"	localparam
C3_MEM_DDR2_3_HIGH_TEMP_SR	47	0			"NORMAL"	localparam
C3_MEM_DDR3_CAS_LATENCY				signed	6	localparam
C3_MEM_DDR3_ODS	31	0			"DIV6"	localparam
C3_MEM_DDR3_RTT	31	0			"DIV2"	localparam
C3_MEM_DDR3_CAS_WR_LATENCY				signed	5	localparam
C3_MEM_DDR3_AUTO_SR	55	0			"ENABLED"	localparam
C3_MEM_DDR3_DYN_WRT_ODT	23	0			"OFF"	localparam
C3_MEM_MOBILE_PA_SR	31	0			"FULL"	localparam
C3_MEM_MDDR_ODS	31	0			"FULL"	localparam
C3_MC_CALIB_BYPASS	15	0			"NO"	localparam
C3_MC_CALIBRATION_MODE	87	0			"CALIBRATION"	localparam
C3_MC_CALIBRATION_DELAY	31	0			"HALF"	localparam
C3_SKIP_IN_TERM_CAL				signed	0	localparam
C3_SKIP_DYNAMIC_CAL				signed	0	localparam
C3_LDQSP_TAP_DELAY_VAL				signed	0	localparam
C3_LDQSN_TAP_DELAY_VAL				signed	0	localparam
C3_UDQSP_TAP_DELAY_VAL				signed	0	localparam
C3_UDQSN_TAP_DELAY_VAL				signed	0	localparam
C3_DQ0_TAP_DELAY_VAL				signed	0	localparam
C3_DQ1_TAP_DELAY_VAL				signed	0	localparam
C3_DQ2_TAP_DELAY_VAL				signed	0	localparam
C3_DQ3_TAP_DELAY_VAL				signed	0	localparam
C3_DQ4_TAP_DELAY_VAL				signed	0	localparam
C3_DQ5_TAP_DELAY_VAL				signed	0	localparam
C3_DQ6_TAP_DELAY_VAL				signed	0	localparam
C3_DQ7_TAP_DELAY_VAL				signed	0	localparam
C3_DQ8_TAP_DELAY_VAL				signed	0	localparam
C3_DQ9_TAP_DELAY_VAL				signed	0	localparam
C3_DQ10_TAP_DELAY_VAL				signed	0	localparam
C3_DQ11_TAP_DELAY_VAL				signed	0	localparam
C3_DQ12_TAP_DELAY_VAL				signed	0	localparam
C3_DQ13_TAP_DELAY_VAL				signed	0	localparam
C3_DQ14_TAP_DELAY_VAL				signed	0	localparam
C3_DQ15_TAP_DELAY_VAL				signed	0	localparam
===
mig_dut	verilog
---
c3_p0_cmd_en	in			
c3_p0_cmd_instr	in	2	0	
c3_p0_cmd_bl	in	5	0	
c3_p0_cmd_byte_addr	in	29	0	
c3_p0_cmd_empty	out			
c3_p0_cmd_full	out			
c3_p0_wr_en	in			
c3_p0_wr_mask	in	(C3_P0_MASK_SIZE - 1)	0	
c3_p0_wr_data	in	(C3_P0_DATA_PORT_SIZE - 1)	0	
c3_p0_wr_full	out			
c3_p0_wr_empty	out			
c3_p0_wr_count	out	6	0	
c3_p0_wr_underrun	out			
c3_p0_wr_error	out			
c3_p0_rd_en	in			
c3_p0_rd_data	out	(C3_P0_DATA_PORT_SIZE - 1)	0	
c3_p0_rd_full	out			
c3_p0_rd_empty	out			
c3_p0_rd_count	out	6	0	
c3_p0_rd_overflow	out			
c3_p0_rd_error	out			
c3_sys_rst_n	in			
c3_calib_done	out			
c3_clk0	in			
c3_rst0	out			
c3_sys_clk_p	in			
c3_sys_clk_n	in			
mcb3_dram_dq	inout	(C3_NUM_DQ_PINS - 1)	0	
mcb3_dram_a	out	(C3_MEM_ADDR_WIDTH - 1)	0	
mcb3_dram_ba	out	(C3_MEM_BANKADDR_WIDTH - 1)	0	
mcb3_dram_ras_n	out			
mcb3_dram_cas_n	out			
mcb3_dram_we_n	out			
mcb3_dram_odt	out			
mcb3_dram_cke	out			
mcb3_dram_dm	out			
mcb3_dram_udqs	inout			
mcb3_dram_udqs_n	inout			
mcb3_rzq	inout			
mcb3_zio	inout			
mcb3_dram_udm	out			
mcb3_dram_dqs	inout			
mcb3_dram_dqs_n	inout			
mcb3_dram_ck	out			
mcb3_dram_ck_n	out			
---
C3_P0_MASK_SIZE				signed	16	parameter
C3_P0_DATA_PORT_SIZE				signed	128	parameter
C3_MEMCLK_PERIOD				signed	3000	parameter
C3_CALIB_SOFT_IP	31	0			"TRUE"	parameter
C3_RST_ACT_LOW				signed	0	parameter
C3_INPUT_CLK_TYPE	95	0			"DIFFERENTIAL"	parameter
C3_MEM_ADDR_ORDER	119	0			"ROW_BANK_COLUMN"	parameter
C3_NUM_DQ_PINS				signed	16	parameter
C3_MEM_ADDR_WIDTH				signed	13	parameter
C3_MEM_BANKADDR_WIDTH				signed	3	parameter
C3_MC_CALIB_BYPASS	15	0			"NO"	parameter
===
test_parameters	verilog
---
---
===
mig_hw_tb	verilog
---
---
C3_MEMCLK_PERIOD				signed	3000	parameter
C3_RST_ACT_LOW				signed	0	parameter
C3_INPUT_CLK_TYPE	95	0			"DIFFERENTIAL"	parameter
C3_NUM_DQ_PINS				signed	16	parameter
C3_MEM_ADDR_WIDTH				signed	13	parameter
C3_MEM_BANKADDR_WIDTH				signed	3	parameter
C3_MEM_ADDR_ORDER	119	0			"ROW_BANK_COLUMN"	parameter
C3_P0_BYTE_ADDR_WIDTH				signed	30	parameter
C3_P0_MASK_SIZE				signed	16	parameter
C3_P0_DATA_PORT_SIZE				signed	128	parameter
C3_MEM_BURST_LEN				signed	8	parameter
C3_MEM_NUM_COL_BITS				signed	10	parameter
C3_MC_CALIB_BYPASS	15	0			"NO"	parameter
C3_CALIB_SOFT_IP	31	0			"TRUE"	parameter
INSTR_WRITE	2	0			3'b0	localparam
INSTR_READ	2	0			3'b01	localparam
INSTR_WRITE_PRECHARGE	2	0			3'b010	localparam
INSTR_READ_PRECHARGE	2	0			3'b011	localparam
INSTR_REFRESH	2	0			3'b100	localparam
===
glbl	verilog
---
---
ROC_WIDTH				signed	100000	parameter
TOC_WIDTH				signed	0	parameter
