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**  Copyright 2011 Xilinx, Inc. All rights reserved.
** This file contains confidential and proprietary information of Xilinx, Inc. and 
** is protected under U.S. and international copyright and other intellectual property laws.
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**   ____  ____ 
**  /   /\/   / 
** /___/  \  /   Vendor: Xilinx 
** \   \   \/    
**  \   \        readme.txt Version: 2.0  
**  /   /        Date Last Modified: 25 January 2011
** /___/   /\    Date Created: May 3 2010
** \   \  /  \   Associated Filename: ug743_design_files.zip
**  \___\/\___\ 
** 
**  Device: N/A
**  Purpose: This archive contains the design files for Xilinx PlanAhead Tutorial: Overview of the Partial Reconfiguration Flow
**  Reference: UG743 - Xilinx PlanAhead Tutorial: Overview of the Partial Reconfiguration Flow
**  Revision History: v 13.1
**   
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**
The design has been synthesized.
  The Source directory contains all of the HDL sources for Static and all RMs, as well as the UCF.
  The PlanAhead directory should be used to create the PlanAhead project for the tutorial.
  The Synth directory contains the synthesis results from the scripted run.
  The Implementation directory is also prepared for running the Tcl scripts to implement the full design.
  The Tools directory contains Tcl scripts that can be used to run a scripted command line flow.

To execute the scripts for full synthesis and place and route for all configurations, run the 
following command from the Implementation directory:
  xtclsh ..\Tools\xpartition.tcl ..\Tools\data.tcl

Synthesis or implementation phases only can be run for all configurations by replacing data.tcl in 
the above command with data_synth.tcl or data_impl.tcl, respectively.
**
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** IMPORTANT NOTES **
These are the Design Files for UG743 - Xilinx PlanAhead Tutorial: Overview of the Partial Reconfiguration Flow.

