TABLE OF CONTENTS
Overview Block Diagram External Ports Processor    ppc440_0 Interrupt Controllers    xps_intc_0 Busses    plb_v46_0 Memory    xps_bram_if_cntlr_1_bram Memory Controllers    DDR2_SDRAM    xps_bram_if_cntlr_1 Peripherals    RS232_Uart_1    jtagppc_cntlr_inst    proc_sys_reset_0    xps_timer_0 IP    clock_generator_0 Timing Information

Overview TOC Resources Used 1   PowerPC 440 Virtex-5 1   Processor Local Bus (PLB) 4.6 1   Block RAM (BRAM) Block 1   XPS BRAM Controller 1   PowerPC 440 DDR2 Memory Controller 1   XPS UART (Lite) 1   XPS Timer/Counter 1   Clock Generator 1   PowerPC JTAG Controller 1   Processor System Reset Module 1   XPS Interrupt Controller Specifics Generated Fri Oct 07 19:58:28 2011 EDK Version 13.3 Device Family virtex5 Device xc5vfx70tff1136-1

Block Diagram TOC

External Ports TOC These are the external ports defined in the MHS file. Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  # NAME DIR [LSB:MSB] SIG ATTRIBUTES SHARED fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET  DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin IO 0:7 fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_DQS_pin IO 0:7 fpga_0_DDR2_SDRAM_DDR2_DQS_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_DQ_pin IO 0:63 fpga_0_DDR2_SDRAM_DDR2_DQ_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_A_pin O 0:12 fpga_0_DDR2_SDRAM_DDR2_A_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_BA_pin O 0:1 fpga_0_DDR2_SDRAM_DDR2_BA_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_CKE_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CKE_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_CK_N_pin O 0:1 fpga_0_DDR2_SDRAM_DDR2_CK_N_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_CK_pin O 0:1 fpga_0_DDR2_SDRAM_DDR2_CK_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_CS_N_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CS_N_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_DM_pin O 0:7 fpga_0_DDR2_SDRAM_DDR2_DM_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_ODT_pin O 0:1 fpga_0_DDR2_SDRAM_DDR2_ODT_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin DDR2_SDRAM fpga_0_DDR2_SDRAM_DDR2_WE_N_pin O 1 fpga_0_DDR2_SDRAM_DDR2_WE_N_pin RS232_Uart_1 fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX_pin RS232_Uart_1 fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX_pin clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 dcm_clk_s  CLK  xps_intc_0 Push_Button_pin I 1 Push_Button  INTR

Processors TOC ppc440_0   PowerPC 440 Virtex-5 A wrapper to instantiate the PowerPC 440 Processor Block primitive IP Specs Core Version Documentation ppc440_virtex5 1.01.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 CPMC440CLK I 1 clk_125_0000MHzPLL0 1 CPMINTERCONNECTCLK I 1 clk_125_0000MHzPLL0 2 CPMINTERCONNECTCLKNTO1 I 1 net_vcc 3 EICC440EXTIRQ I 1 ppc440_0_EICC440EXTIRQ 4 CPMMCCLK I 1 clk_125_0000MHzPLL0_ADJUST Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To PPC440MC INITIATOR XIL_PPC440MC ppc440_0_PPC440MC DDR2_SDRAM MPLB MASTER PLBV46 plb_v46_0 4 Peripherals. JTAGPPC TARGET XIL_JTAGPPC ppc440_0_jtagppc_bus jtagppc_cntlr_inst RESETPPC TARGET XIL_RESETPPC ppc_reset_bus proc_sys_reset_0 Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_PIR 0B1111 C_ENDIAN_RESET 0 C_USER_RESET 0B0000 C_INTERCONNECT_IMASK 0xFFFFFFFF C_ICU_RD_FETCH_PLB_PRIO 0B00 C_ICU_RD_SPEC_PLB_PRIO 0B00 C_ICU_RD_TOUCH_PLB_PRIO 0B00 C_DCU_RD_LD_CACHE_PLB_PRIO 0B00 C_DCU_RD_NONCACHE_PLB_PRIO 0B00 C_DCU_RD_TOUCH_PLB_PRIO 0B00 C_DCU_RD_URGENT_PLB_PRIO 0B00 C_DCU_WR_FLUSH_PLB_PRIO 0B00 C_DCU_WR_STORE_PLB_PRIO 0B00 C_DCU_WR_URGENT_PLB_PRIO 0B00 C_DMA0_PLB_PRIO 0b00 C_DMA1_PLB_PRIO 0b00 C_DMA2_PLB_PRIO 0b00 C_DMA3_PLB_PRIO 0b00 C_IDCR_BASEADDR 0B0000000000 C_IDCR_HIGHADDR 0B0011111111 C_APU_CONTROL 0b00010000000000000 C_APU_UDI_0 0b000000000000000000000000 C_APU_UDI_1 0b000000000000000000000000 C_APU_UDI_2 0b000000000000000000000000 C_APU_UDI_3 0b000000000000000000000000 C_APU_UDI_4 0b000000000000000000000000 C_APU_UDI_5 0b000000000000000000000000 C_APU_UDI_6 0b000000000000000000000000 C_APU_UDI_7 0b000000000000000000000000 C_APU_UDI_8 0b000000000000000000000000 C_APU_UDI_9 0b000000000000000000000000 C_APU_UDI_10 0b000000000000000000000000 C_APU_UDI_11 0b000000000000000000000000 C_APU_UDI_12 0b000000000000000000000000 C_APU_UDI_13 0b000000000000000000000000 C_APU_UDI_14 0b000000000000000000000000 C_APU_UDI_15 0b000000000000000000000000 C_PPC440MC_ADDR_BASE 0xFFFFFFFF C_PPC440MC_ADDR_HIGH 0x00000000 C_PPC440MC_ROW_CONFLICT_MASK 0x003FFE00 C_PPC440MC_BANK_CONFLICT_MASK 0x00C00000 C_PPC440MC_CONTROL 0xF810008F C_PPC440MC_PRIO_ICU 4 C_PPC440MC_PRIO_DCUW 3 C_PPC440MC_PRIO_DCUR 2 C_PPC440MC_PRIO_SPLB1 0 C_PPC440MC_PRIO_SPLB0 1 C_PPC440MC_ARB_MODE 0 C_PPC440MC_MAX_BURST 8 C_MPLB_AWIDTH 32 C_MPLB_DWIDTH 128 C_MPLB_NATIVE_DWIDTH 128 C_MPLB_COUNTER 0x00000500 C_MPLB_PRIO_ICU 4 C_MPLB_PRIO_DCUW 3 C_MPLB_PRIO_DCUR 2 C_MPLB_PRIO_SPLB1 0 C_MPLB_PRIO_SPLB0 1 C_MPLB_ARB_MODE 0 C_MPLB_SYNC_TATTRIBUTE 0 C_MPLB_MAX_BURST 8 C_MPLB_ALLOW_LOCK_XFER 1 C_MPLB_READ_PIPE_ENABLE 1 C_MPLB_WRITE_PIPE_ENABLE 1 C_MPLB_WRITE_POST_ENABLE 1 C_MPLB_P2P 0 C_MPLB_WDOG_ENABLE 1 C_SPLB0_AWIDTH 32 Name Value C_SPLB0_DWIDTH 128 C_SPLB0_NATIVE_DWIDTH 128 C_SPLB0_SUPPORT_BURSTS 1 C_SPLB0_USE_MPLB_ADDR 0 C_SPLB0_NUM_MPLB_ADDR_RNG 0 C_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF C_SPLB0_RNG_MC_HIGHADDR 0x00000000 C_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF C_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000 C_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF C_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000 C_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF C_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000 C_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF C_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000 C_SPLB0_NUM_MASTERS 1 C_SPLB0_MID_WIDTH 1 C_SPLB0_ALLOW_LOCK_XFER 1 C_SPLB0_READ_PIPE_ENABLE 1 C_SPLB0_PROPAGATE_MIRQ 0 C_SPLB0_P2P -1 C_SPLB1_AWIDTH 32 C_SPLB1_DWIDTH 128 C_SPLB1_NATIVE_DWIDTH 128 C_SPLB1_SUPPORT_BURSTS 1 C_SPLB1_USE_MPLB_ADDR 0 C_SPLB1_NUM_MPLB_ADDR_RNG 0 C_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF C_SPLB1_RNG_MC_HIGHADDR 0x00000000 C_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF C_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000 C_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF C_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000 C_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF C_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000 C_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF C_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000 C_SPLB1_NUM_MASTERS 1 C_SPLB1_MID_WIDTH 1 C_SPLB1_ALLOW_LOCK_XFER 1 C_SPLB1_READ_PIPE_ENABLE 1 C_SPLB1_PROPAGATE_MIRQ 0 C_SPLB1_P2P -1 C_NUM_DMA 0 C_DMA0_TXCHANNELCTRL 0x01010000 C_DMA0_RXCHANNELCTRL 0x01010000 C_DMA0_CONTROL 0b00000000 C_DMA0_TXIRQTIMER 0b1111111111 C_DMA0_RXIRQTIMER 0b1111111111 C_DMA1_TXCHANNELCTRL 0x01010000 C_DMA1_RXCHANNELCTRL 0x01010000 C_DMA1_CONTROL 0b00000000 C_DMA1_TXIRQTIMER 0b1111111111 C_DMA1_RXIRQTIMER 0b1111111111 C_DMA2_TXCHANNELCTRL 0x01010000 C_DMA2_RXCHANNELCTRL 0x01010000 C_DMA2_CONTROL 0b00000000 C_DMA2_TXIRQTIMER 0b1111111111 C_DMA2_RXIRQTIMER 0b1111111111 C_DMA3_TXCHANNELCTRL 0x01010000 C_DMA3_RXCHANNELCTRL 0x01010000 C_DMA3_CONTROL 0b00000000 C_DMA3_TXIRQTIMER 0b1111111111 C_DMA3_RXIRQTIMER 0b1111111111 C_DCR_AUTOLOCK_ENABLE 1 C_PPCDM_ASYNCMODE 0 C_PPCDS_ASYNCMODE 0 C_GENERATE_PLB_TIMESPECS 1 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Interrupt Controllers TOC xps_intc_0   XPS Interrupt Controller intc core attached to the PLBV46 IP Specs Core Version Documentation xps_intc 2.01.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 Intr I 1 Push_Button & xps_timer_0_Interrupt 1 Irq O 1 ppc440_0_EICC440EXTIRQ Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To SPLB SLAVE PLBV46 plb_v46_0 4 Peripherals. Interrupt Priorities Priority SIG MODULE 0 Push_Button EXTERNALPORTS 1 xps_timer_0_Interrupt xps_timer_0 Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY virtex5 C_BASEADDR 0x81800000 C_HIGHADDR 0x8180FFFF C_SPLB_AWIDTH 32 C_SPLB_DWIDTH 32 C_SPLB_P2P 0 C_SPLB_NUM_MASTERS 1 C_SPLB_MID_WIDTH 1 C_SPLB_NATIVE_DWIDTH 32 C_SPLB_SUPPORT_BURSTS 0 Name Value C_NUM_INTR_INPUTS 2 C_KIND_OF_INTR 0xFFFFFFFF C_KIND_OF_EDGE 0xFFFFFFFF C_KIND_OF_LVL 0xFFFFFFFF C_HAS_IPR 1 C_HAS_SIE 1 C_HAS_CIE 1 C_HAS_IVR 1 C_IRQ_IS_LEVEL 1 C_IRQ_ACTIVE 1 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Busses TOC plb_v46_0   Processor Local Bus (PLB) 4.6 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' IP Specs Core Version Documentation plb_v46 1.05.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 PLB_Clk I 1 clk_125_0000MHzPLL0_ADJUST 1 SYS_Rst I 1 sys_bus_reset Bus Connections INSTANCE INTERFACE TYPE INTERFACE NAME ppc440_0 MASTER MPLB xps_bram_if_cntlr_1 SLAVE SPLB RS232_Uart_1 SLAVE SPLB xps_timer_0 SLAVE SPLB xps_intc_0 SLAVE SPLB Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_PLBV46_NUM_MASTERS 4 C_PLBV46_NUM_SLAVES 8 C_PLBV46_MID_WIDTH 2 C_PLBV46_AWIDTH 32 C_PLBV46_DWIDTH 64 C_DCR_INTFCE 0 C_BASEADDR 0B1111111111 C_HIGHADDR 0B0000000000 C_DCR_AWIDTH 10 Name Value C_DCR_DWIDTH 32 C_EXT_RESET_HIGH 1 C_IRQ_ACTIVE 1 C_NUM_CLK_PLB2OPB_REARB 5 C_ADDR_PIPELINING_TYPE 1 C_FAMILY virtex5 C_P2P 0 C_ARB_TYPE 0   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Memorys TOC xps_bram_if_cntlr_1_bram   Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. IP Specs Core Version Documentation bram_block 1.00.a IP Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To PORTA TARGET XIL_BRAM xps_bram_if_cntlr_1_port xps_bram_if_cntlr_1 Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_MEMSIZE 2048 C_PORT_DWIDTH 32 C_PORT_AWIDTH 32 C_NUM_WE 4 C_FAMILY virtex2 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Memory Controllers TOC DDR2_SDRAM   PowerPC 440 DDR2 Memory Controller A wrapper to instantiate the PowerPC 440 DDR2 Memory Controller IP Specs Core Version Documentation ppc440mc_ddr2 3.00.c IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 mc_mibclk I 1 clk_125_0000MHzPLL0_ADJUST 1 mi_mcclk90 I 1 clk_125_0000MHz90PLL0_ADJUST 2 mi_mcreset I 1 sys_bus_reset 3 mi_mcclkdiv2 I 1 clk_62_5000MHzPLL0_ADJUST 4 mi_mcclk_200 I 1 clk_200_0000MHz 5 DDR2_DQ IO 1 fpga_0_DDR2_SDRAM_DDR2_DQ_pin 6 DDR2_DQS IO 1 fpga_0_DDR2_SDRAM_DDR2_DQS_pin 7 DDR2_DQS_N IO 1 fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin 8 DDR2_A O 1 fpga_0_DDR2_SDRAM_DDR2_A_pin 9 DDR2_BA O 1 fpga_0_DDR2_SDRAM_DDR2_BA_pin 10 DDR2_RAS_N O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin 11 DDR2_CAS_N O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin 12 DDR2_WE_N O 1 fpga_0_DDR2_SDRAM_DDR2_WE_N_pin 13 DDR2_CS_N O 1 fpga_0_DDR2_SDRAM_DDR2_CS_N_pin 14 DDR2_ODT O 1 fpga_0_DDR2_SDRAM_DDR2_ODT_pin 15 DDR2_CKE O 1 fpga_0_DDR2_SDRAM_DDR2_CKE_pin 16 DDR2_DM O 1 fpga_0_DDR2_SDRAM_DDR2_DM_pin 17 DDR2_CK O 1 fpga_0_DDR2_SDRAM_DDR2_CK_pin 18 DDR2_CK_N O 1 fpga_0_DDR2_SDRAM_DDR2_CK_N_pin Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To PPC440MC TARGET XIL_PPC440MC ppc440_0_PPC440MC ppc440_0 Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_DDR_BAWIDTH 2 C_NUM_CLK_PAIRS 2 C_DDR_DWIDTH 64 C_DDR_CAWIDTH 10 C_NUM_RANKS_MEM 1 C_CS_BITS 0 C_DDR_DM_WIDTH 8 C_DQ_BITS 8 C_DDR2_ODT_WIDTH 2 C_DDR2_ADDT_LAT 0 C_INCLUDE_ECC_SUPPORT 0 C_DDR2_ODT_SETTING 1 C_DQS_BITS 3 C_DDR_DQS_WIDTH 8 C_DDR_RAWIDTH 13 C_DDR_BURST_LENGTH 4 C_DDR_CAS_LAT 4 C_REG_DIMM 0 C_MIB_MC_CLOCK_RATIO 1 Name Value C_MEM_BASEADDR 0x00000000 C_MEM_HIGHADDR 0x0FFFFFFF C_REDUCE_DRV 0 C_DDR_TREFI 3900 C_DDR_TRAS 40000 C_DDR_TRCD 15000 C_DDR_TRFC 75000 C_DDR_TRP 15000 C_DDR_TRTP 7500 C_DDR_TWR 15000 C_DDR_TWTR 7500 C_MC_MIBCLK_PERIOD_PS 3000 C_IDEL_HIGH_PERF TRUE C_SIM_ONLY 0 C_NUM_IDELAYCTRL 3 C_IODELAY_GRP NOT_SET C_READ_DATA_PIPELINE 0 C_FPGA_SPEED_GRADE 1   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. xps_bram_if_cntlr_1   XPS BRAM Controller Attaches BRAM to the PLBV46 IP Specs Core Version Documentation xps_bram_if_cntlr 1.00.b IP Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To PORTA INITIATOR XIL_BRAM xps_bram_if_cntlr_1_port xps_bram_if_cntlr_1_bram SPLB SLAVE PLBV46 plb_v46_0 4 Peripherals. Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0xFFFF8000 C_HIGHADDR 0xFFFFFFFF C_SPLB_NATIVE_DWIDTH 64 C_SPLB_AWIDTH 32 C_SPLB_DWIDTH 32 C_SPLB_NUM_MASTERS 2 Name Value C_SPLB_MID_WIDTH 1 C_SPLB_SUPPORT_BURSTS 1 C_SPLB_P2P 0 C_SPLB_SMALLEST_MASTER 32 C_FAMILY virtex5   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Peripherals TOC RS232_Uart_1   XPS UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus. IP Specs Core Version Documentation xps_uartlite 1.02.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 RX I 1 fpga_0_RS232_Uart_1_RX_pin 1 TX O 1 fpga_0_RS232_Uart_1_TX_pin Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To SPLB SLAVE PLBV46 plb_v46_0 4 Peripherals. Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY virtex5 C_SPLB_CLK_FREQ_HZ 100000000 C_BASEADDR 0x84000000 C_HIGHADDR 0x8400FFFF C_SPLB_AWIDTH 32 C_SPLB_DWIDTH 32 C_SPLB_P2P 0 C_SPLB_MID_WIDTH 1 Name Value C_SPLB_NUM_MASTERS 1 C_SPLB_SUPPORT_BURSTS 0 C_SPLB_NATIVE_DWIDTH 32 C_BAUDRATE 9600 C_DATA_BITS 8 C_USE_PARITY 0 C_ODD_PARITY 0   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. jtagppc_cntlr_inst   PowerPC JTAG Controller JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA. IP Specs Core Version Documentation jtagppc_cntlr 2.01.c IP Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To JTAGPPC0 INITIATOR XIL_JTAGPPC ppc440_0_jtagppc_bus ppc440_0 Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_DEVICE X2VP4 C_NUM_PPC_USED 0 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. proc_sys_reset_0   Processor System Reset Module Reset management module IP Specs Core Version Documentation proc_sys_reset 3.00.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 Slowest_sync_clk I 1 clk_125_0000MHzPLL0_ADJUST 1 Ext_Reset_In I 1 sys_rst_s 2 Dcm_locked I 1 Dcm_all_locked 3 Bus_Struct_Reset O 1 sys_bus_reset 4 Peripheral_Reset O 1 sys_periph_reset Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To RESETPPC0 INITIATOR XIL_RESETPPC ppc_reset_bus ppc440_0 Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_SUBFAMILY lx C_EXT_RST_WIDTH 4 C_AUX_RST_WIDTH 4 C_EXT_RESET_HIGH 0 C_AUX_RESET_HIGH 1 C_NUM_BUS_RST 1 C_NUM_PERP_RST 1 C_NUM_INTERCONNECT_ARESETN 1 C_NUM_PERP_ARESETN 1 C_FAMILY virtex5 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. xps_timer_0   XPS Timer/Counter Timer counter with PLBV46 interface IP Specs Core Version Documentation xps_timer 1.02.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 Interrupt O 1 xps_timer_0_Interrupt Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To SPLB SLAVE PLBV46 plb_v46_0 4 Peripherals. Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY virtex5 C_COUNT_WIDTH 32 C_ONE_TIMER_ONLY 0 C_TRIG0_ASSERT 1 C_TRIG1_ASSERT 1 C_GEN0_ASSERT 1 C_GEN1_ASSERT 1 C_BASEADDR 0x83C00000 Name Value C_HIGHADDR 0x83C0FFFF C_SPLB_AWIDTH 32 C_SPLB_DWIDTH 32 C_SPLB_P2P 0 C_SPLB_MID_WIDTH 3 C_SPLB_NUM_MASTERS 8 C_SPLB_SUPPORT_BURSTS 0 C_SPLB_NATIVE_DWIDTH 32 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

IP TOC clock_generator_0   Clock Generator Clock generator for processor system. IP Specs Core Version Documentation clock_generator 4.03.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 CLKIN I 1 dcm_clk_s 1 CLKOUT0 O 1 clk_125_0000MHz90PLL0_ADJUST 2 CLKOUT1 O 1 clk_125_0000MHzPLL0 3 CLKOUT2 O 1 clk_125_0000MHzPLL0_ADJUST 4 CLKOUT3 O 1 clk_200_0000MHz 5 CLKOUT4 O 1 clk_62_5000MHzPLL0_ADJUST 6 RST I 1 sys_rst_s 7 LOCKED O 1 Dcm_all_locked Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY virtex6 C_DEVICE NOT_SET C_PACKAGE NOT_SET C_SPEEDGRADE NOT_SET C_CLKIN_FREQ 100000000 C_CLKOUT0_FREQ 125000000 C_CLKOUT0_PHASE 90 C_CLKOUT0_GROUP PLL0_ADJUST C_CLKOUT0_BUF TRUE C_CLKOUT0_VARIABLE_PHASE FALSE C_CLKOUT1_FREQ 125000000 C_CLKOUT1_PHASE 0 C_CLKOUT1_GROUP PLL0 C_CLKOUT1_BUF TRUE C_CLKOUT1_VARIABLE_PHASE FALSE C_CLKOUT2_FREQ 125000000 C_CLKOUT2_PHASE 0 C_CLKOUT2_GROUP PLL0_ADJUST C_CLKOUT2_BUF TRUE C_CLKOUT2_VARIABLE_PHASE FALSE C_CLKOUT3_FREQ 200000000 C_CLKOUT3_PHASE 0 C_CLKOUT3_GROUP NONE C_CLKOUT3_BUF TRUE C_CLKOUT3_VARIABLE_PHASE FALSE C_CLKOUT4_FREQ 62500000 C_CLKOUT4_PHASE 0 C_CLKOUT4_GROUP PLL0_ADJUST C_CLKOUT4_BUF TRUE C_CLKOUT4_VARIABLE_PHASE FALSE C_CLKOUT5_FREQ 0 C_CLKOUT5_PHASE 0 C_CLKOUT5_GROUP NONE C_CLKOUT5_BUF TRUE C_CLKOUT5_VARIABLE_PHASE FALSE C_CLKOUT6_FREQ 0 C_CLKOUT6_PHASE 0 C_CLKOUT6_GROUP NONE C_CLKOUT6_BUF TRUE C_CLKOUT6_VARIABLE_PHASE FALSE C_CLKOUT7_FREQ 0 C_CLKOUT7_PHASE 0 C_CLKOUT7_GROUP NONE C_CLKOUT7_BUF TRUE C_CLKOUT7_VARIABLE_PHASE FALSE C_CLKOUT8_FREQ 0 C_CLKOUT8_PHASE 0 C_CLKOUT8_GROUP NONE C_CLKOUT8_BUF TRUE C_CLKOUT8_VARIABLE_PHASE FALSE C_CLKOUT9_FREQ 0 C_CLKOUT9_PHASE 0 C_CLKOUT9_GROUP NONE C_CLKOUT9_BUF TRUE C_CLKOUT9_VARIABLE_PHASE FALSE C_CLKOUT10_FREQ 0 Name Value C_CLKOUT10_PHASE 0 C_CLKOUT10_GROUP NONE C_CLKOUT10_BUF TRUE C_CLKOUT10_VARIABLE_PHASE FALSE C_CLKOUT11_FREQ 0 C_CLKOUT11_PHASE 0 C_CLKOUT11_GROUP NONE C_CLKOUT11_BUF TRUE C_CLKOUT11_VARIABLE_PHASE FALSE C_CLKOUT12_FREQ 0 C_CLKOUT12_PHASE 0 C_CLKOUT12_GROUP NONE C_CLKOUT12_BUF TRUE C_CLKOUT12_VARIABLE_PHASE FALSE C_CLKOUT13_FREQ 0 C_CLKOUT13_PHASE 0 C_CLKOUT13_GROUP NONE C_CLKOUT13_BUF TRUE C_CLKOUT13_VARIABLE_PHASE FALSE C_CLKOUT14_FREQ 0 C_CLKOUT14_PHASE 0 C_CLKOUT14_GROUP NONE C_CLKOUT14_BUF TRUE C_CLKOUT14_VARIABLE_PHASE FALSE C_CLKOUT15_FREQ 0 C_CLKOUT15_PHASE 0 C_CLKOUT15_GROUP NONE C_CLKOUT15_BUF TRUE C_CLKOUT15_VARIABLE_PHASE FALSE C_CLKFBIN_FREQ 0 C_CLKFBIN_DESKEW NONE C_CLKFBOUT_FREQ 0 C_CLKFBOUT_PHASE 0 C_CLKFBOUT_GROUP NONE C_CLKFBOUT_BUF TRUE C_PSDONE_GROUP NONE C_EXT_RESET_HIGH 0 C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE C_CLKOUT0_DUTY_CYCLE 0.500000 C_CLKOUT1_DUTY_CYCLE 0.500000 C_CLKOUT2_DUTY_CYCLE 0.500000 C_CLKOUT3_DUTY_CYCLE 0.500000 C_CLKOUT4_DUTY_CYCLE 0.500000 C_CLKOUT5_DUTY_CYCLE 0.500000 C_CLKOUT6_DUTY_CYCLE 0.500000 C_CLKOUT7_DUTY_CYCLE 0.500000 C_CLKOUT8_DUTY_CYCLE 0.500000 C_CLKOUT9_DUTY_CYCLE 0.500000 C_CLKOUT10_DUTY_CYCLE 0.500000 C_CLKOUT11_DUTY_CYCLE 0.500000 C_CLKOUT12_DUTY_CYCLE 0.500000 C_CLKOUT13_DUTY_CYCLE 0.500000 C_CLKOUT14_DUTY_CYCLE 0.500000 C_CLKOUT15_DUTY_CYCLE 0.500000 C_CLK_GEN UPDATE   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Timing Information TOC Post Synthesis Clock Limits No clocks could be identified in the design. Run platgen to generate synthesis information.