| rp Project Status (04/03/2012 - 08:47:32) | |||
| Project File: | rp.xise | Parser Errors: | No Errors |
| Module Name: | rp | Implementation State: | Synthesized |
| Target Device: | xc6vlx240t-1ff1156 |
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No Errors |
| Product Version: | ISE 14.1 |
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2 Warnings (0 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice LUTs | 1 | 150720 | 0% | |
| Number of fully used LUT-FF pairs | 0 | 1 | 0% | |
| Number of bonded IOBs | 0 | 600 | 0% | |
| Number of DSP48E1s | 1 | 768 | 0% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Tue Apr 3 08:47:31 2012 | 0 | 2 Warnings (0 new) | 2 Infos (0 new) | |
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |