rp Project Status (04/02/2013 - 16:52:06)
Project File: rp_adder.xise Parser Errors: No Errors
Module Name: rp Implementation State: Synthesized
Target Device: xc6vlx240t-1ff1156
  • Errors:
 No Errors
Product Version:ISE 14.5
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 32 301440 0%
Number of Slice LUTs 33 150720 0%
Number of fully used LUT-FF pairs 32 33 96%
Number of bonded IOBs 0 600 0%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 2 16:52:05 2013001 Info (1 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 04/02/2013 - 16:52:06