Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > DCFG (USB3_XHCI) Register

DCFG (USB3_XHCI) Register

DCFG (USB3_XHCI) Register Description

Register NameDCFG
Relative Address0x000000C700
Absolute Address 0x00FE20C700 (USB3_0_XHCI)
0x00FE30C700 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000800
DescriptionDevice Configuration Register.
This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

DCFG (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Reserved
Reserved24roRead-only0x0reserved
IgnStrmPP23rwNormal read/write0IgnoreStreamPP
This bit only affects stream-capable bulk endpoints.
When this bit is set to 0 and the controller receives a Data Packet with the Packet Pending (PP) bit set to 0 for OUT endpoints, or it receives an ACK with the NumP field set to 0 and PP set to 0 for IN endpoints, the core attempts to search for another stream (CStream) to initiate to the host. However, there are two situations where this behavior is not optimal:
- When the host is setting PP=0 even though it has not finished the stream, or
- When the endpoint on the device is configured with one transfer resource and therefore does not have any other streams to initiate to the host.
When this bit is set to 1, the core ignores the Packet Pending bit for the purposes of stream selection and does not search for another stream when it receives DP(PP=0) or ACK(NumP=0, PP=0). This can enhance the performance when the device system bus bandwidth is low or the host responds to the cores ERDY transmission very quickly.
LPMCAP22rwNormal read/write0LPM Capable
The application uses this bit to control the controller LPM capabilities. If the core operates as a non-LPM-capable device, it cannot respond to LPM transactions.
- 1b0: LPM capability is not enabled.
- 1b1: LPM capability is enabled.
NUMP21:17rwNormal read/write0Number of Receive Buffers.
This bit indicates the number of receive buffers to be reported in the ACK TP.
The DWC_usb3 controller uses this field if GRXTHRCFG.USBRxPktCntSel is set to 0. The application can program this value based on RxFIFO size, buffer sizes programmed in descriptors, and system latency.
For an OUT endpoint, this field controls the number of receive buffers reported in the NumP field of the ACK TP transmitted by the core.
Note: This bit is used in host mode when Debug Capability is enabled.
INTRNUM16:12rwNormal read/write0Interrupt number
Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated.
Reserved11:10roRead-only0x2Reserved
DEVADDR 9:3rwNormal read/write0Device Address.
The application must perform the following:
- Program this field after every SetAddress request.
- Reset this field to zero after USB reset.
DEVSPD 2:0rwNormal read/write0Device Speed.
Indicates the speed at which the application requires the core to connect, or the maximum speed the application can support.
However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected.
- 3b100: SuperSpeed (USB 3.0 PHY clock is 125 MHz or 250 MHz)
- 3b000: High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
- 3b001: Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)