Zynq UltraScale+ Devices Register Reference > Module Summary > GIC400 Module > GICH_APR0_Alias0 (GIC400) Register

GICH_APR0_Alias0 (GIC400) Register

GICH_APR0_Alias0 (GIC400) Register Description

Register NameGICH_APR0_Alias0
Relative Address0x00000500F0
Absolute Address 0x00F90500F0 (ACPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionActive Priority Register

GICH_APR0_Alias0 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.