Zynq UltraScale+ Devices Register Reference > Module Summary > A53_PMU_1 Module > CIDR0 (A53_PMU_1) Register

CIDR0 (A53_PMU_1) Register

CIDR0 (A53_PMU_1) Register Description

Register NameCIDR0
Relative Address0x0000000FF0
Absolute Address 0x00FED30FF0 (CORESIGHT_A53_PMU_1)
Width32
TyperoRead-only
Reset Value0x0000000D
DescriptionPerformance Monitors Component Identification Register 0

CIDR0 (A53_PMU_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PRMBL_0 7:0roRead-only0xDPreamble. Must read as 0x0D.