Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > SARSIZE1 (DDRC) Register
Register Name | SARSIZE1 |
---|---|
Relative Address | 0x0000000F10 |
Absolute Address | 0x00FD070F10 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | SAR Size Register 1 |
This register is static. Static registers can only be written when the controller is in reset.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
nblocks | 7:0 | rwNormal read/write | 0x0 | Number of blocks for address region 1. This register determines the total size of the region in multiples of minimum block size, 2GB. The register value is encoded as number of blocks = nblocks + 1. For example, if register is programmed to 0, region will have 1 block. |