Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AUD_CH_STATUS_REG0 (DISPLAY_PORT) Register

AUD_CH_STATUS_REG0 (DISPLAY_PORT) Register

AUD_CH_STATUS_REG0 (DISPLAY_PORT) Register Description

Register NameAUD_CH_STATUS_REG0
Relative Address0x000000C008
Absolute Address 0x00FD4AC008 (DISPLAY_PORT)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAUD_CH_STATUS_REG0: Audio Channel status bits 31 to 0

AUD_CH_STATUS_REG0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
STATUS031:0rwNormal read/write0x0-