Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > VCU_AXI_CTRL (VCU_SLCR) Register
Register Name | VCU_AXI_CTRL |
---|---|
Relative Address | 0x0000000040 |
Absolute Address | 0x00A0040040 (VCU_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x0000F000 |
Description | This register controls this reference clock |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 18 | razRead as zero | 0x0 | reserved |
MCU_CLK_SEL | 17 | rwNormal read/write | 0x0 | 0: Encoder MCU clock selected on output port for monitoring purpose. 1: Decoder MCU clock selected on output port for monitoring purpose. |
CORE_CLK_SEL | 16 | rwNormal read/write | 0x0 | 0: Encoder core clock selected on output port for monitoring purpose. 1: Decoder core clock selected on output port for monitoring purpose. |
MCU_CLKACT | 15 | rwNormal read/write | 0x1 | Clock active signal. Switch to 0 to disable the clock |
DEC_CLKACT | 14 | rwNormal read/write | 0x1 | Clock active signal. Switch to 0 to disable the clock |
ENC_CACHE_CLKACT | 13 | rwNormal read/write | 0x1 | Clock active signal. Switch to 0 to disable the clock |
ENC_CLKACT | 12 | rwNormal read/write | 0x1 | Clock active signal. Switch to 0 to disable the clock |
Reserved | 11:0 | razRead as zero | 0x0 | reserved |