Zynq UltraScale+ Devices Register Reference > Module Summary > A53_DBG_1 Module > EDESR (A53_DBG_1) Register
Register Name | EDESR |
---|---|
Relative Address | 0x0000000020 |
Absolute Address | 0x00FED10020 (CORESIGHT_A53_DBG_1) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | External Debug Event Status Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
SS | 2 | rwNormal read/write | 0x0 | Halting step debug event pending. Possible values of this field are: |
RC | 1 | rwNormal read/write | 0x0 | Reset catch debug event pending. Possible values of this field are: |
OSUC | 0 | rwNormal read/write | 0x0 | OS unlock debug event pending. Possible values of this field are: |