Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AUD_CH_A_DATA_REG1 (DISPLAY_PORT) Register
Register Name | AUD_CH_A_DATA_REG1 |
---|---|
Relative Address | 0x000000C024 |
Absolute Address | 0x00FD4AC024 (DISPLAY_PORT) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | AUD_CH_A_DATA_REG1: User data bits 63 to 32 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
USER_DATA1 | 31:0 | rwNormal read/write | 0x0 | - |