Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module

LPD_SLCR Module

LPD_SLCR Module Description

Module NameLPD_SLCR Module
Modules of this TypeLPD_SLCR
Base Address0x00FF410000 (LPD_SLCR)
DescriptionLow-power Domain SLCR, Low-power Domain System-level Control Registers

LPD_SLCR Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
ctrl0x0000000004 1rwNormal read/write0x00000000General control register for the LP SLCR
isr0x0000000008 1wtcReadable, write a 1 to clear0x00000000Interrupt Status Register
imr0x000000000C 1roRead-only0x00000001Interrupt Mask Register
ier0x0000000010 1woWrite-only0x00000000Interrupt Enable Register
idr0x0000000014 1woWrite-only0x00000000Interrupt Disable Register
itr0x0000000018 1woWrite-only0x00000000Interrupt Trigger Register
persistent00x000000002032rwNormal read/write0x00000000This register is never reset, even through POR.
persistent10x000000002432rwNormal read/write0x00000000This register is never reset, even through POR.
persistent20x000000002832rwNormal read/write0x00000000This register is never reset, even through POR.
persistent30x000000002C32rwNormal read/write0x00000000This register is never reset, even through POR.
persistent40x000000003032rwNormal read/write0x00000000This register is never reset, even through POR.
persistent50x000000003432rwNormal read/write0x00000000This register is never reset, even through POR.
persistent60x000000003832rwNormal read/write0x00000000This register is never reset, even through POR.
persistent70x000000003C32rwNormal read/write0x00000000This register is never reset, even through POR.
SAFETY_CHK00x000000004032rwNormal read/write0x00000000Safety endpoint connectivity check Register
SAFETY_CHK10x000000004432rwNormal read/write0x00000000Safety endpoint connectivity check Register
SAFETY_CHK20x000000004832rwNormal read/write0x00000000Safety endpoint connectivity check Register
SAFETY_CHK30x000000004C32rwNormal read/write0x00000000Safety endpoint connectivity check Register
CSUPMU_WDT_CLK_SEL0x000000005032mixedMixed types. See bit-field details.0x00000000SWDT clock source select
adma_cfg0x000000200C 7roRead-only0x00000028GDMA RF2 Configuation
ADMA_RAM0x000000201016mixedMixed types. See bit-field details.0x00003B3BRAM control register
afi_fs0x000000500016mixedMixed types. See bit-field details.0x00000200afi fs SLCR control register. Do not change the bits durin
ERR_ATB_ISR0x000000600032mixedMixed types. See bit-field details.0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
ERR_ATB_IMR0x000000600432mixedMixed types. See bit-field details.0x00000003Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
ERR_ATB_IER0x000000600832mixedMixed types. See bit-field details.0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
ERR_ATB_IDR0x000000600C32mixedMixed types. See bit-field details.0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
ATB_CMD_STORE_EN0x000000601032mixedMixed types. See bit-field details.0x00000003ATB Sideband Signals
ATB_RESP_EN0x000000601432mixedMixed types. See bit-field details.0x00000000ATB Sideband Signals
ATB_RESP_TYPE0x000000601832mixedMixed types. See bit-field details.0x00000003ATB Sideband Signals
ATB_PRESCALE0x000000602032mixedMixed types. See bit-field details.0x0000FFFFATB Sideband Signals
GICP0_IRQ_STATUS0x000000800032wtcReadable, write a 1 to clear0x00000000GIC Proxy Interrupt Status (1/2)
GICP0_IRQ_MASK0x000000800432roRead-only0xFFFFFFFFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
GICP0_IRQ_ENABLE0x000000800832woWrite-only0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
GICP0_IRQ_DISABLE0x000000800C32woWrite-only0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
GICP0_IRQ_TRIGGER0x000000801032woWrite-only0x00000000Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt.
GICP1_IRQ_STATUS0x000000801432wtcReadable, write a 1 to clear0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
GICP1_IRQ_MASK0x000000801832roRead-only0xFFFFFFFFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
GICP1_IRQ_ENABLE0x000000801C32woWrite-only0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
GICP1_IRQ_DISABLE0x000000802032woWrite-only0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
GICP1_IRQ_TRIGGER0x000000802432woWrite-only0x00000000Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt.
GICP2_IRQ_STATUS0x000000802832wtcReadable, write a 1 to clear0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
GICP2_IRQ_MASK0x000000802C32roRead-only0xFFFFFFFFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
GICP2_IRQ_ENABLE0x000000803032woWrite-only0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
GICP2_IRQ_DISABLE0x000000803432woWrite-only0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
GICP2_IRQ_TRIGGER0x000000803832woWrite-only0x00000000Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt.
GICP3_IRQ_STATUS0x000000803C32wtcReadable, write a 1 to clear0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
GICP3_IRQ_MASK0x000000804032roRead-only0xFFFFFFFFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
GICP3_IRQ_ENABLE0x000000804432woWrite-only0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
GICP3_IRQ_DISABLE0x000000804832woWrite-only0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
GICP3_IRQ_TRIGGER0x000000804C32woWrite-only0x00000000Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt.
GICP4_IRQ_STATUS0x000000805032wtcReadable, write a 1 to clear0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
GICP4_IRQ_MASK0x000000805432roRead-only0xFFFFFFFFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
GICP4_IRQ_ENABLE0x000000805832woWrite-only0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
GICP4_IRQ_DISABLE0x000000805C32woWrite-only0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
GICP4_IRQ_TRIGGER0x000000806032woWrite-only0x00000000Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt.
GICP_PMU_IRQ_STATUS0x00000080A032mixedMixed types. See bit-field details.0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
GICP_PMU_IRQ_MASK0x00000080A432mixedMixed types. See bit-field details.0x000000FFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
GICP_PMU_IRQ_ENABLE0x00000080A832mixedMixed types. See bit-field details.0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
GICP_PMU_IRQ_DISABLE0x00000080AC32mixedMixed types. See bit-field details.0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
GICP_PMU_IRQ_TRIGGER0x00000080B032mixedMixed types. See bit-field details.0x00000000Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt.