Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_PIN_8 (IOU_SLCR) Register
Register Name | MIO_PIN_8 |
---|---|
Relative Address | 0x0000000020 |
Absolute Address | 0x00FF180020 (IOU_SLCR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Configures MIO Pin 8 peripheral interface mapping |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | rwNormal read/write | 0x0 | reserved |
L3_SEL | 7:5 | rwNormal read/write | 0x0 | Level 3 Mux Select: 0: GPIO [8] input/output bank 0. 1: CAN1 TX output. 2: I2C1 SCL input/output clock. 3: FPD SWDT clock output. 4: SPI1 SS [1] output. 5: TTC3 clock input. 6: UART1 TxD output. 7: TracePort DQ[6] output. |
L2_SEL | 4:3 | rwNormal read/write | 0x0 | Level 2 Mux Select: 0: Level 3 Mux output 1: reserved 2: Scan Test [8] input/output. 3: reserved |
L1_SEL | 2 | rwNormal read/write | 0x0 | Level 1 Mux Select: 0: Level 2 Mux output 1: reserved |
L0_SEL | 1 | rwNormal read/write | 0x0 | Level 0 Mux Select: 0: Level 1 Mux output 1: Quad SPI1 IO[0] input/output (upper) |
Reserved | 0 | rwNormal read/write | 0x0 | reserved |