Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > DCCP_LO (USB3_XHCI) Register

DCCP_LO (USB3_XHCI) Register

DCCP_LO (USB3_XHCI) Register Description

Register NameDCCP_LO
Relative Address0x0000000940
Absolute Address 0x00FE200940 (USB3_0_XHCI)
0x00FE300940 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDCCP_LO

DCCP_LO (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DCCPR31:4rwNormal read/write0DCCPR
Reserved 3:0roRead-only0x0Reserved