Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_DEC_TOP Module > AXI_WBW1 (VCU_DEC_TOP) Register

AXI_WBW1 (VCU_DEC_TOP) Register

AXI_WBW1 (VCU_DEC_TOP) Register Description

Register NameAXI_WBW1
Relative Address0x000000921C
Absolute Address 0x00A002921C (VCU_DECODE)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAXI Write Bandwidth Status 1

AXI_WBW1 (VCU_DEC_TOP) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
AxiWriteBwStatus131:0roRead-only0x0Returns the number of 128-bit words written by the AXI master port 1 during the preceding bandwidth measurement window (when enabled by AXI_BW).