Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU_REG Module > MISC (SMMU_REG) Register

MISC (SMMU_REG) Register

MISC (SMMU_REG) Register Description

Register NameMISC
Relative Address0x0000000054
Absolute Address 0x00FD5F0054 (SMMU_REG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000016
DescriptionMiscellaneous signals

MISC (SMMU_REG) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:13rwNormal read/write0x0reserved
spniden12rwNormal read/write0x0allow counting of secure events by performance monitors
Reserved11:8roRead-only0x0reserved.
awakeup_prog 7rwNormal read/write0x0Wakeup signal for Programming interface
Reserved 6rwNormal read/write0x0reserved.
Reserved 5:4rwNormal read/write0x1reserved.
Reserved 3:1rwNormal read/write0x3reserved.
Reserved 0rwNormal read/write0x0reserved