Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > IOU_TTC_APB_CLK (IOU_SLCR) Register
Register Name | IOU_TTC_APB_CLK |
---|---|
Relative Address | 0x0000000380 |
Absolute Address | 0x00FF180380 (IOU_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | TTC APB Interface Clock Select |
00: APB Interconnect clock (LPD_APB_CLK, lpd_lsbus_clk). 01: Device Pin, PS_REF_CLK. 10: RPU clock (RPU_CLK, cpu_r5_clk). 11: reserved.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
TTC3_SEL | 7:6 | rwNormal read/write | 0x0 | TTC3 interface clock. |
TTC2_SEL | 5:4 | rwNormal read/write | 0x0 | TTC2 interface clock. |
TTC1_SEL | 3:2 | rwNormal read/write | 0x0 | TTC1 interface clock. |
TTC0_SEL | 1:0 | rwNormal read/write | 0x0 | TTC0 interface clock. |