Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_INIT_WAIT (DISPLAY_PORT) Register
Register Name | DP_INIT_WAIT |
---|---|
Relative Address | 0x00000001CC |
Absolute Address | 0x00FD4A01CC (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000020 |
Description | This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:7 | razRead as zero | 0x0 | |
INIT_WAIT | 6:0 | rwNormal read/write | 0x20 | If (MIN_BYTES_PER_TU <= 4 ) - [6:0] - Set INIT_WAIT to 64 Else - [6:0] - Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU) |