Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > GP_CONTR_REG_AXI_BUS_ERROR_STAT (GPU) Register

GP_CONTR_REG_AXI_BUS_ERROR_STAT (GPU) Register

GP_CONTR_REG_AXI_BUS_ERROR_STAT (GPU) Register Description

Register NameGP_CONTR_REG_AXI_BUS_ERROR_STAT
Relative Address0x0000000094
Absolute Address 0x00FD4B0094 (GPU)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionGP Control AXI Bus Error Status

GP_CONTR_REG_AXI_BUS_ERROR_STAT (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10roRead-only0x0Reserved, write as zero, read undefined
GP_READ_ERROR_ID 9:6roRead-only0x0ID of read error cause
GP_WRITE_ERROR_ID 5:2roRead-only0x0ID of write error cause
GP_READ_ERROR 1roRead-only0x0Set when a read error occurs
GP_WRITE_ERROR 0roRead-only0x0Set when a write error occurs