Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > csu_ctrl (CSU) Register

csu_ctrl (CSU) Register

csu_ctrl (CSU) Register Description

Register Namecsu_ctrl
Relative Address0x0000000004
Absolute Address 0x00FFCA0004 (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCSU Control

csu_ctrl (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
slverr_enable 4rwNormal read/write0x0Enable for the SLVERR signal during an address decode failure on the APB interface.
0: disable (default), invalid address requests are ignored and the system can hang.
1: enable, the SLVERR signal is asserted back to the master; writes are ignored and a read returns 0.
Reserved 3:1rwNormal read/write0x0reserved
csu_clk_sel 0rwNormal read/write0x0Selects the clock source for the CSU clock. This clock goes to the DMA, AES, SHA, & RSA.
0: SysOsc
1: PLL