Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_95 (PCIE_ATTRIB) Register

ATTR_95 (PCIE_ATTRIB) Register

ATTR_95 (PCIE_ATTRIB) Register Description

Register NameATTR_95
Relative Address0x000000017C
Absolute Address 0x00FD48017C (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionATTR_95

This register should only be written to during reset of the PCIe block

ATTR_95 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_pm_aspml0s_timeout_en15rwNormal read/write0x0Enables the ASPM L0S Timer to use the user-defined PM_ASPML0S_TIMEOUT value (or combined with the built-in value, depending on PM_ASPML0S_TIMEOUT_FUNC). If FALSE, the built-in value is used.
attr_pm_aspml0s_timeout14:0rwNormal read/write0x0Sets a user-defined timeout for the ASPM L0s Timer; refer to PM_ASPML0S_TIMEOUT_EN and PM_ASPML0S_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.