Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > CIDR0 (TSGEN) Register
Register Name | CIDR0 |
---|---|
Relative Address | 0x0000000FF0 |
Absolute Address | 0x00FE900FF0 (CORESIGHT_SOC_TSGEN) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x0000000D |
Description | A component identification register, that indicates that the identification registers are present. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PRMBL_0 | 7:0 | roRead-only | 0xD | Contains bits[7:0] of the component identification code. |