Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > IOVCR0 (DDR_PHY) Register

IOVCR0 (DDR_PHY) Register

IOVCR0 (DDR_PHY) Register Description

Register NameIOVCR0
Relative Address0x0000000520
Absolute Address 0x00FD080520 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0F000000
DescriptionIO VREF Control Register 0

IOVCR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29roRead-only0x0Reserved. Return zeros on reads.
ACREFPEN28rwNormal read/write0x0Address/command lane VREF Pad Enable: Enables the pass gate
between (to connect) VREF and PAD.
Reserved27:26rwNormal read/write0x3reserved.
ACREFSEN25rwNormal read/write0x1Address/command lane Single-End VREF Enable: Enables the
generation of VREF value for internal address/command lane
single-end IO buffers.
ACREFIEN24rwNormal read/write0x1Address/command lane Internal VREF Enable: Enables the
generation of VREF value for internal address/command lane
differential IO buffers.
Reserved23rwNormal read/write0x0reserved.
Reserved22:16rwNormal read/write0x0reserved.
ACREFSSELRANGE15rwNormal read/write0x0Single ended VREF generator REFSEL range select.
ACREFSSEL14:8rwNormal read/write0x0Address/command lane Single-End VREF Select: Selects the
generated VREF value for internal address/command lane single-
end I/O buffers.
ACVREFISELRANGE 7rwNormal read/write0x0Internal VREF generator REFSEL range select
ACVREFISEL 6:0rwNormal read/write0x0REFSEL Control for internal AC IOs: Selects the
generated VREF value for internal AC IOs.