Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > MISC_CTRL (PCIE_ATTRIB) Register

MISC_CTRL (PCIE_ATTRIB) Register

MISC_CTRL (PCIE_ATTRIB) Register Description

Register NameMISC_CTRL
Relative Address0x0000000300
Absolute Address 0x00FD480300 (PCIE_ATTRIB)
Width 1
TyperwNormal read/write
Reset Value0x00000000
DescriptionMISC_CTRL

MISC_CTRL (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
slverr_enable 0rwNormal read/write0x0By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur.
Enable/Disable SLVERR during address decode failure.
0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0.
1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0.