Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_ANA_BYP_12 (SERDES) Register

L0_TM_ANA_BYP_12 (SERDES) Register

L0_TM_ANA_BYP_12 (SERDES) Register Description

Register NameL0_TM_ANA_BYP_12
Relative Address0x000000102C
Absolute Address 0x00FD40102C (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_ANA_BYP_12 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_ANA_BYP_12_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
uphy_PSO_HSRXDIG 7rwNormal read/write0x0Value generated by PCW.
force_uphy_PSO_HSRXDIG 6rwNormal read/write0x0Value generated by PCW.
uphy_PDN_HS_DES 5rwNormal read/write0x0Value generated by PCW.
force_uphy_PDN_HS_DES 4rwNormal read/write0x0Value generated by PCW.
uphy_RST_GF_MUX 3rwNormal read/write0x0Value generated by PCW.
force_uphy_RST_GF_MUX 2rwNormal read/write0x0Value generated by PCW.
uphy_ENABLE_CDR 1rwNormal read/write0x0Value generated by PCW.
force_uphy_ENABLE_CDR 0rwNormal read/write0x0Value generated by PCW.