Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > puf_cfg0 (CSU) Register

puf_cfg0 (CSU) Register

puf_cfg0 (CSU) Register Description

Register Namepuf_cfg0
Relative Address0x0000004004
Absolute Address 0x00FFCA4004 (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000002
DescriptionPUF Configuration 0

puf_cfg0 (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CFG031:0rwNormal read/write0x2Configures digital procesing pipeline.
For "4k" bit Syndrome, use CFG0 = 0x2.