Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_PIN_49 (IOU_SLCR) Register

MIO_PIN_49 (IOU_SLCR) Register

MIO_PIN_49 (IOU_SLCR) Register Description

Register NameMIO_PIN_49
Relative Address0x00000000C4
Absolute Address 0x00FF1800C4 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 49 Multiplexer Controls.

MIO_PIN_49 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [49] input/output bank 1.
1: CAN1 RX input.
2: I2C1 SDA input/output.
3: FPD SWDT reset output.
4: SPI1 MOSI input/output.
5: TTC3 waveform output.
6: UART1 RxD input.
7: reserved
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: SDIO0 Card Bus Power output.
2: SDIO1 Data [3] input/output.
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: reserved
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM1 RGMII Rx Control input.
Reserved 0rwNormal read/write0x0reserved