Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_MISC2 (SERDES) Register

L0_TM_MISC2 (SERDES) Register

L0_TM_MISC2 (SERDES) Register Description

Register NameL0_TM_MISC2
Relative Address0x000000189C
Absolute Address 0x00FD40189C (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_MISC2 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_MISC2_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
ill_cal_bypass_counts 7rwNormal read/write0x0Value generated by PCW.
pwr_seq_samp_cal_always 6rwNormal read/write0x0Value generated by PCW.
pwr_seq_byp_cal_done 5rwNormal read/write0x0Value generated by PCW.
pwr_seq_byp_cal_done_val 4rwNormal read/write0x0Value generated by PCW.
samp_bypass_cal_to_eq 3rwNormal read/write0x0Value generated by PCW.
samp_bypass_cal_to_eq_val 2rwNormal read/write0x0Value generated by PCW.
UNUSED 1:0roRead-only0x0Value generated by PCW.