Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > PTR3 (DDR_PHY) Register
Register Name | PTR3 |
---|---|
Relative Address | 0x000000004C |
Absolute Address | 0x00FD08004C (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00411810 |
Description | PHY Timing Register 3 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:23 | roRead-only | 0x0 | Return zeroes on reads. |
tDINIT0 | 22:0 | rwNormal read/write | 0x411810 | DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR4 = CKE low time with power and clock stable (500 us) DDR3 = CKE low time with power and clock stable (500 us) LPDDR4 = CKE low time with power and clock stable (2000 us) LPDDR3 = CKE high time to first command (200 us) Note: Default value corresponds to LPDDR4 CKE low time of 2000 us at 2133 MHz. |