Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_77 (PCIE_ATTRIB) Register
Register Name | ATTR_77 |
---|---|
Relative Address | 0x0000000134 |
Absolute Address | 0x00FD480134 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | ATTR_77 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_rbar_cap_control_encodedbar1 | 12:8 | rwNormal read/write | 0x0 | Initial value for the 2nd RBAR Control "BAR Size" field (if any). Encoding is 0=1MB, 1=2MB,2=4MB,etc. This value must correspond to the size requested in the attribute BARx (where x is the value of RBAR_CAP_INDEX1). For instance, if RBAR_CAP_INDEX1=3, and BAR3 requests a 16MB aperture, then this attribute must be set to 4 (meaning 16MB). |
attr_rbar_cap_control_encodedbar0 | 7:3 | rwNormal read/write | 0x0 | Initial value for the 1st RBAR Control "BAR Size" field (if any). Encoding is 0=1MB, 1=2MB,2=4MB,etc. This value must correspond to the size requested in the attribute BARx (where x is the value of RBAR_CAP_INDEX0). For instance, if RBAR_CAP_INDEX0=3, and BAR3 requests a 16MB aperture, then this attribute must be set to 4 (meaning 16MB). |
attr_rbar_cap_index5 | 2:0 | rwNormal read/write | 0x0 | BAR Index value for Resizable BAR Control Register(5). Set to 0 if 5 or fewer BARs can be resized. This value should not be lower than the value on RBAR_CAP_INDEX0,1,2,3,4. |