Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU_SINK Module > isr (XPPU_SINK) Register

isr (XPPU_SINK) Register

isr (XPPU_SINK) Register Description

Register Nameisr
Relative Address0x000000FF10
Absolute Address 0x00FF9CFF10 (LPD_XPPU_SINK)
Width 1
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status and Clear.

isr (XPPU_SINK) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0wtcReadable, write a 1 to clear0x0Access violation (poisoned AXI transaction or register access error).
READ:
0: no interrupt.
1: interrupt asserted.
WRITE:
0: no effect.
1: clear bit to 0.
If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers.
The ERR_CTRL [PSLVERR] can enable a violation event to cause the XMPU_Sink to assert the PSLVERR signal back to the APB interconnect.