Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > pcap_prog (CSU) Register
Register Name | pcap_prog |
---|---|
Relative Address | 0x0000003000 |
Absolute Address | 0x00FFCA3000 (CSU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | PCAP PROG |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
pcfg_prog_b | 0 | rwNormal read/write | 0x0 | PROG control to the PL. The PL is reset when this bit is deasserted and will remain in reset until this register is asserted. After PROG is released, wait for PCAP_STATUS[INIT] before sending configuration data. 0x0 - PL in reset 0x1 - PL not in reset |