Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX5GCR4 (DDR_PHY) Register
Register Name | DX5GCR4 |
---|---|
Relative Address | 0x0000000C10 |
Absolute Address | 0x00FD080C10 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x0E00003C |
Description | DATX8 n General Configuration Register 4 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:29 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
DXREFPEN | 28 | rwNormal read/write | 0x0 | Byte Lane VREF Pad Enable: Enables the pass gate between (to connect) VREF and PAD. |
Reserved | 27:26 | rwNormal read/write | 0x3 | reserved. |
DXREFSEN | 25 | rwNormal read/write | 0x1 | Byte Lane Single-End VREF Enable: Enables the generation of VREF value for internal byte lane single-end IO buffers. |
Reserved | 24 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
Reserved | 23 | rwNormal read/write | 0x0 | reserved. |
Reserved | 22:16 | rwNormal read/write | 0x0 | reserved. |
DXREFSSELRANGE | 15 | rwNormal read/write | 0x0 | Single ended VREF generator REFSEL range select |
DXREFSSEL | 14:8 | rwNormal read/write | 0x0 | Byte Lane Single-End VREF Select: Selects the generated VREF value for internal byte lane single-end I/O buffers. |
Reserved | 7:6 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
DXREFIEN | 5:2 | rwNormal read/write | 0xF | VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. |
DXREFIMON | 1:0 | rwNormal read/write | 0x0 | VRMON control for DQ IO (Single Ended) buffers of a byte lane. |