Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_GPV Module

IOU_GPV Module

IOU_GPV Module Description

Module NameIOU_GPV Module
Modules of this TypeIOU_GPV
Base Address0x00FE000000 (IOU_GPV)
DescriptionIOP GPV, GPV

IOU_GPV Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
periph_id_40x0000001FD032roRead-only0x000000044KB count, JEP106 continuation code
periph_id_50x0000001FD432roRead-only0x00000000Reserved
periph_id_60x0000001FD832roRead-only0x00000000Reserved
periph_id_70x0000001FDC32roRead-only0x00000000Reserved
periph_id_00x0000001FE032roRead-only0x00000000Part Number [7:0]
periph_id_10x0000001FE432roRead-only0x000000B4JEP106[3:0], part number [11:8]
periph_id_20x0000001FE832roRead-only0x0000002BRevision, JEP106 code flag, JEP106[6:4]
periph_id_30x0000001FEC32roRead-only0x00000000You can set this using the AMBA Designer Graphical User Interface (GUI)
comp_id_00x0000001FF032roRead-only0x0000000DPreamble
comp_id_10x0000001FF432roRead-only0x000000F0Generic IP component class, preamble
comp_id_20x0000001FF832roRead-only0x00000005Preamble
comp_id_30x0000001FFC32roRead-only0x000000B1Preamble
intiou_intlpd_fn_mod_iss_bm0x000000200832rwNormal read/write0x00000000Bus matrix issuing functionality modification register
apb_ns_0_ib_fn_mod_iss_bm0x000000700832rwNormal read/write0x00000000Bus matrix issuing functionality modification register
apb_ns_1_ib_fn_mod_iss_bm0x000000800832rwNormal read/write0x00000000Bus matrix issuing functionality modification register
intlpd_intiou_fn_mod0x000004210832rwNormal read/write0x00000000Issuing functionality modification register
intlpd_intiou_qos_cntl0x000004210C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
intlpd_intiou_max_ot0x000004211032rwNormal read/write0x00000000Maximum number of outstanding transactions
intlpd_intiou_max_comb_ot0x000004211432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
intlpd_intiou_aw_p0x000004211832rwNormal read/write0x00000000AW channel peak rate
intlpd_intiou_aw_b0x000004211C32rwNormal read/write0x00000000AW channel burstiness allowance
intlpd_intiou_aw_r0x000004212032rwNormal read/write0x00000000AW channel average rate
intlpd_intiou_ar_p0x000004212432rwNormal read/write0x00000000AR channel peak rate
intlpd_intiou_ar_b0x000004212832rwNormal read/write0x00000000AR channel burstiness allowance
intlpd_intiou_ar_r0x000004212C32rwNormal read/write0x00000000AR channel average rate
gem0M_intiou_read_qos0x000004310032rwNormal read/write0x00000000Read channel QoS value
gem0M_intiou_write_qos0x000004310432rwNormal read/write0x00000000Write channel QoS value
gem0M_intiou_fn_mod0x000004310832rwNormal read/write0x00000000Issuing functionality modification register
gem0M_intiou_qos_cntl0x000004310C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
gem0M_intiou_max_ot0x000004311032rwNormal read/write0x00000000Maximum number of outstanding transactions
gem0M_intiou_max_comb_ot0x000004311432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
gem0M_intiou_aw_p0x000004311832rwNormal read/write0x00000000AW channel peak rate
gem0M_intiou_aw_b0x000004311C32rwNormal read/write0x00000000AW channel burstiness allowance
gem0M_intiou_aw_r0x000004312032rwNormal read/write0x00000000AW channel average rate
gem0M_intiou_ar_p0x000004312432rwNormal read/write0x00000000AR channel peak rate
gem0M_intiou_ar_b0x000004312832rwNormal read/write0x00000000AR channel burstiness allowance
gem0M_intiou_ar_r0x000004312C32rwNormal read/write0x00000000AR channel average rate
gem1M_intiou_read_qos0x000004410032rwNormal read/write0x00000000Read channel QoS value
gem1M_intiou_write_qos0x000004410432rwNormal read/write0x00000000Write channel QoS value
gem1M_intiou_fn_mod0x000004410832rwNormal read/write0x00000000Issuing functionality modification register
gem1M_intiou_qos_cntl0x000004410C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
gem1M_intiou_max_ot0x000004411032rwNormal read/write0x00000000Maximum number of outstanding transactions
gem1M_intiou_max_comb_ot0x000004411432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
gem1M_intiou_aw_p0x000004411832rwNormal read/write0x00000000AW channel peak rate
gem1M_intiou_aw_b0x000004411C32rwNormal read/write0x00000000AW channel burstiness allowance
gem1M_intiou_aw_r0x000004412032rwNormal read/write0x00000000AW channel average rate
gem1M_intiou_ar_p0x000004412432rwNormal read/write0x00000000AR channel peak rate
gem1M_intiou_ar_b0x000004412832rwNormal read/write0x00000000AR channel burstiness allowance
gem1M_intiou_ar_r0x000004412C32rwNormal read/write0x00000000AR channel average rate
gem2M_intiou_read_qos0x000004510032rwNormal read/write0x00000000Read channel QoS value
gem2M_intiou_write_qos0x000004510432rwNormal read/write0x00000000Write channel QoS value
gem2M_intiou_fn_mod0x000004510832rwNormal read/write0x00000000Issuing functionality modification register
gem2M_intiou_qos_cntl0x000004510C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
gem2M_intiou_max_ot0x000004511032rwNormal read/write0x00000000Maximum number of outstanding transactions
gem2M_intiou_max_comb_ot0x000004511432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
gem2M_intiou_aw_p0x000004511832rwNormal read/write0x00000000AW channel peak rate
gem2M_intiou_aw_b0x000004511C32rwNormal read/write0x00000000AW channel burstiness allowance
gem2M_intiou_aw_r0x000004512032rwNormal read/write0x00000000AW channel average rate
gem2M_intiou_ar_p0x000004512432rwNormal read/write0x00000000AR channel peak rate
gem2M_intiou_ar_b0x000004512832rwNormal read/write0x00000000AR channel burstiness allowance
gem2M_intiou_ar_r0x000004512C32rwNormal read/write0x00000000AR channel average rate
gem3M_intiou_read_qos0x000004610032rwNormal read/write0x00000000Read channel QoS value
gem3M_intiou_write_qos0x000004610432rwNormal read/write0x00000000Write channel QoS value
gem3M_intiou_fn_mod0x000004610832rwNormal read/write0x00000000Issuing functionality modification register
gem3M_intiou_qos_cntl0x000004610C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
gem3M_intiou_max_ot0x000004611032rwNormal read/write0x00000000Maximum number of outstanding transactions
gem3M_intiou_max_comb_ot0x000004611432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
gem3M_intiou_aw_p0x000004611832rwNormal read/write0x00000000AW channel peak rate
gem3M_intiou_aw_b0x000004611C32rwNormal read/write0x00000000AW channel burstiness allowance
gem3M_intiou_aw_r0x000004612032rwNormal read/write0x00000000AW channel average rate
gem3M_intiou_ar_p0x000004612432rwNormal read/write0x00000000AR channel peak rate
gem3M_intiou_ar_b0x000004612832rwNormal read/write0x00000000AR channel burstiness allowance
gem3M_intiou_ar_r0x000004612C32rwNormal read/write0x00000000AR channel average rate
nandM_intiou_ib_fn_mod20x000004702432rwNormal read/write0x00000000This register is only present if upsizing or downsizing happens
nandM_intiou_ib_read_qos0x000004710032rwNormal read/write0x00000000Read channel QoS value
nandM_intiou_ib_write_qos0x000004710432rwNormal read/write0x00000000Write channel QoS value
nandM_intiou_ib_fn_mod0x000004710832rwNormal read/write0x00000000Issuing functionality modification register
nandM_intiou_ib_qos_cntl0x000004710C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
nandM_intiou_ib_max_ot0x000004711032rwNormal read/write0x00000000Maximum number of outstanding transactions
nandM_intiou_ib_max_comb_ot0x000004711432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
nandM_intiou_ib_aw_p0x000004711832rwNormal read/write0x00000000AW channel peak rate
nandM_intiou_ib_aw_b0x000004711C32rwNormal read/write0x00000000AW channel burstiness allowance
nandM_intiou_ib_aw_r0x000004712032rwNormal read/write0x00000000AW channel average rate
nandM_intiou_ib_ar_p0x000004712432rwNormal read/write0x00000000AR channel peak rate
nandM_intiou_ib_ar_b0x000004712832rwNormal read/write0x00000000AR channel burstiness allowance
nandM_intiou_ib_ar_r0x000004712C32rwNormal read/write0x00000000AR channel average rate
sd0M_intiou_ib_fn_mod20x000004802432rwNormal read/write0x00000000This register is only present if upsizing or downsizing happens
sd0M_intiou_ib_read_qos0x000004810032rwNormal read/write0x00000000Read channel QoS value
sd0M_intiou_ib_write_qos0x000004810432rwNormal read/write0x00000000Write channel QoS value
sd0M_intiou_ib_fn_mod0x000004810832rwNormal read/write0x00000000Issuing functionality modification register
sd0M_intiou_ib_qos_cntl0x000004810C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
sd0M_intiou_ib_max_ot0x000004811032rwNormal read/write0x00000000Maximum number of outstanding transactions
sd0M_intiou_ib_max_comb_ot0x000004811432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
sd0M_intiou_ib_aw_p0x000004811832rwNormal read/write0x00000000AW channel peak rate
sd0M_intiou_ib_aw_b0x000004811C32rwNormal read/write0x00000000AW channel burstiness allowance
sd0M_intiou_ib_aw_r0x000004812032rwNormal read/write0x00000000AW channel average rate
sd0M_intiou_ib_ar_p0x000004812432rwNormal read/write0x00000000AR channel peak rate
sd0M_intiou_ib_ar_b0x000004812832rwNormal read/write0x00000000AR channel burstiness allowance
sd0M_intiou_ib_ar_r0x000004812C32rwNormal read/write0x00000000AR channel average rate
sd1M_intiou_ib_fn_mod20x000004902432rwNormal read/write0x00000000This register is only present if upsizing or downsizing happens
sd1M_intiou_ib_read_qos0x000004910032rwNormal read/write0x00000000Read channel QoS value
sd1M_intiou_ib_write_qos0x000004910432rwNormal read/write0x00000000Write channel QoS value
sd1M_intiou_ib_fn_mod0x000004910832rwNormal read/write0x00000000Issuing functionality modification register
sd1M_intiou_ib_qos_cntl0x000004910C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
sd1M_intiou_ib_max_ot0x000004911032rwNormal read/write0x00000000Maximum number of outstanding transactions
sd1M_intiou_ib_max_comb_ot0x000004911432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
sd1M_intiou_ib_aw_p0x000004911832rwNormal read/write0x00000000AW channel peak rate
sd1M_intiou_ib_aw_b0x000004911C32rwNormal read/write0x00000000AW channel burstiness allowance
sd1M_intiou_ib_aw_r0x000004912032rwNormal read/write0x00000000AW channel average rate
sd1M_intiou_ib_ar_p0x000004912432rwNormal read/write0x00000000AR channel peak rate
sd1M_intiou_ib_ar_b0x000004912832rwNormal read/write0x00000000AR channel burstiness allowance
sd1M_intiou_ib_ar_r0x000004912C32rwNormal read/write0x00000000AR channel average rate
qspiM_intiou_ib_fn_mod20x000004A02432rwNormal read/write0x00000000This register is only present if upsizing or downsizing happens
qspiM_intiou_ib_read_qos0x000004A10032rwNormal read/write0x00000000Read channel QoS value
qspiM_intiou_ib_write_qos0x000004A10432rwNormal read/write0x00000000Write channel QoS value
qspiM_intiou_ib_fn_mod0x000004A10832rwNormal read/write0x00000000Issuing functionality modification register
qspiM_intiou_ib_qos_cntl0x000004A10C32rwNormal read/write0x00000000The QoS control register contains the enable bits for all the regulators.
qspiM_intiou_ib_max_ot0x000004A11032rwNormal read/write0x00000000Maximum number of outstanding transactions
qspiM_intiou_ib_max_comb_ot0x000004A11432rwNormal read/write0x00000000Maximum number of combined outstanding transactions
qspiM_intiou_ib_aw_p0x000004A11832rwNormal read/write0x00000000AW channel peak rate
qspiM_intiou_ib_aw_b0x000004A11C32rwNormal read/write0x00000000AW channel burstiness allowance
qspiM_intiou_ib_aw_r0x000004A12032rwNormal read/write0x00000000AW channel average rate
qspiM_intiou_ib_ar_p0x000004A12432rwNormal read/write0x00000000AR channel peak rate
qspiM_intiou_ib_ar_b0x000004A12832rwNormal read/write0x00000000AR channel burstiness allowance
qspiM_intiou_ib_ar_r0x000004A12C32rwNormal read/write0x00000000AR channel average rate