Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_SCR1 (SMMU500) Register

SMMU_SCR1 (SMMU500) Register

SMMU_SCR1 (SMMU500) Register Description

Register NameSMMU_SCR1
Relative Address0x0000000004
Absolute Address 0x00FD800004 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x02013010
DescriptionProvides top-level Secure control of the SMMU.

SMMU_SCR1 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NSCAFRO28roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SPMEN27rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SIF26rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GEFRO25rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GASRAE24rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNUMIRPTO23:16roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNUMSMRGO13:8rwNormal read/write0x30Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNUMCBO 4:0rwNormal read/write0x10Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details