Zynq UltraScale+ Devices Register Reference > Module Summary > APMDDR Module > FECR (APMDDR) Register
Register Name | FECR |
---|---|
Relative Address | 0x0000000400 |
Absolute Address | 0x00FD0B0400 (APM_DDR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Flag Enable. |
0: disable. 1: enable.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31 | rwNormal read/write | 0x0 | reserved. |
Reserved | 30 | rwNormal read/write | 0x0 | reserved. |
Reserved | 29 | rwNormal read/write | 0x0 | reserved. |
Reserved | 28 | rwNormal read/write | 0x0 | reserved. |
Reserved | 27 | rwNormal read/write | 0x0 | reserved. |
Reserved | 26 | rwNormal read/write | 0x0 | reserved. |
Reserved | 25 | rwNormal read/write | 0x0 | reserved. |
Reserved | 24 | rwNormal read/write | 0x0 | reserved. |
Reserved | 23 | rwNormal read/write | 0x0 | reserved. |
Reserved | 22 | rwNormal read/write | 0x0 | reserved. |
SMP_CNT_LAPSE_FLG | 21 | rwNormal read/write | 0x0 | Enable Sample Counter Lapse flag |
GCC_OFVL_FLG | 20 | rwNormal read/write | 0x0 | Enable Global Clock count overflow flag |
Reserved | 19 | rwNormal read/write | 0x0 | reserved. |
Reserved | 18 | rwNormal read/write | 0x0 | reserved. |
Reserved | 17 | rwNormal read/write | 0x0 | reserved. |
SFT_DATA_FLG_EN | 16 | rwNormal read/write | 0x0 | Enable software-written data flag |
Reserved | 15:7 | razRead as zero | 0x0 | reserved. |
LAST_READ_FLG | 6 | rwNormal read/write | 0x0 | Enable Last Read flag |
FIRST_READ_FLG | 5 | rwNormal read/write | 0x0 | Enable First Read flag |
READ_ADDR_FLG | 4 | rwNormal read/write | 0x0 | Enable Read Addr flag |
RESPONSE_FLG | 3 | rwNormal read/write | 0x0 | Enable Responese flag |
LAST_WRITE_FLG | 2 | rwNormal read/write | 0x0 | Enable Last Write flag |
FIRST_WRITE_FLG | 1 | rwNormal read/write | 0x0 | Enable First Write flag |
WRITE_ADDR_FLG | 0 | rwNormal read/write | 0x0 | Enable Write Addr flag |