Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > GQSPI_IDR (QSPI) Register
Register Name | GQSPI_IDR |
---|---|
Relative Address | 0x000000010C |
Absolute Address | 0x00FF0F010C (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | GQSPI Interrupt disable |
Writing a 1 to this register resets the corresponding bits of the interrupt mask register. 0: no effect. 1: disable the interrupt (set mask = 1).
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:12 | razRead as zero | 0x0 | reserved |
RX_FIFO_EMPTY | 11 | woWrite-only | 0x0 | RX FIFO Empty interrupt disable |
Gen_FIFO_full | 10 | woWrite-only | 0x0 | Generic FIFO full interrupt disable |
Gen_FIFO_not_full | 9 | woWrite-only | 0x0 | Generic FIFO not full interrupt disable |
TX_FIFO_EMPTY | 8 | woWrite-only | 0x0 | TX FIFO Empty interrupt disable |
Gen_FIFO_Empty | 7 | woWrite-only | 0x0 | Generic FIFO Empty interrupt disable |
Reserved | 6 | razRead as zero | 0x0 | reserved |
RX_FIFO_full | 5 | woWrite-only | 0x0 | RX FIFO full disable |
RX_FIFO_not_empty | 4 | woWrite-only | 0x0 | RX FIFO not empty disable |
TX_FIFO_full | 3 | woWrite-only | 0x0 | TX FIFO full disable |
TX_FIFO_not_full | 2 | woWrite-only | 0x0 | TX FIFO not full disable |
Poll_Time_Expire | 1 | woWrite-only | 0x0 | Poll Time out counter expire interrupt disable |
Reserved | 0 | razRead as zero | 0x0 | reserved |