Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_ENC_TOP Module > AXI_BW (VCU_ENC_TOP) Register
Register Name | AXI_BW |
---|---|
Relative Address | 0x0000009204 |
Absolute Address | 0x00A0009204 (VCU_ENCODE) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | AXI Bandwidth Measurement Window |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
AxiBandwidthWindow | 31:0 | rwNormal read/write | 0x0 | Time window of the bandwidth counters for the 128-bit AXI master ports. It sets the number of aclk clock cycles during which average bandwidth figures are measured. A zero value disables the counters. |