Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_DMA Module > DMA_CHANNEL_DMA_CONTROL (AXIPCIE_DMA) Register

DMA_CHANNEL_DMA_CONTROL (AXIPCIE_DMA) Register

DMA_CHANNEL_DMA_CONTROL (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_DMA_CONTROL
Relative Address0x0000000078
Absolute Address 0x00FD0F0078 (AXIPCIE_DMA0)
0x00FD0F00F8 (AXIPCIE_DMA1)
0x00FD0F0178 (AXIPCIE_DMA2)
0x00FD0F01F8 (AXIPCIE_DMA3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDMA Channel Control

DMA_CHANNEL_DMA_CONTROL (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:3roRead-only0x0
cmpl_stat_q_elem_size 2rwNormal read/write0x0DMA Channel Completion Status Queue Element Size. If UserID and/or UserHandle information is needed for an application, the application must setup the DMA Channel with 64-bit Status Queue Elements. If these features are not needed, then the DMA Channel may be setup with 32-bit Status Queue Elements to reduce the bus utilization required to write status Queue Elements.
dma_reset 1rwNormal read/write0x0DMA Channel Reset. Each DMA Channel has a small Source SGL FIFO, Destination SGL FIFO, Source DMA Completion Status FIFO, and Destination DMA Completion Status FIFO to enable overlapping of DMA transactions for higher throughput. When a DMA Channel is disabled, these FIFOs may not empty fully and may need to be flushed before the DMA Channel can be reused for a new operation.
dma_enable 0rwNormal read/write0x0DMA Channel Enable