Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX0GSR1 (DDR_PHY) Register
Register Name | DX0GSR1 |
---|---|
Relative Address | 0x00000007E4 |
Absolute Address | 0x00FD0807E4 (DDR_PHY) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | DATX8 n General Status Register 1 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |
DLTCODE | 24:1 | roRead-only | 0x0 | Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. |
DLTDONE | 0 | roRead-only | 0x0 | Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. |