Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_ENC_TOP Module > AXI_WBW0 (VCU_ENC_TOP) Register
Register Name | AXI_WBW0 |
---|---|
Relative Address | 0x0000009218 |
Absolute Address | 0x00A0009218 (VCU_ENCODE) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | AXI Write Bandwidth Status 0 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
AxiWriteBwStatus0 | 31:0 | roRead-only | 0x0 | Returns the number of 128-bit words written by the AXI master port 0 during the preceding bandwidth measurement window (when enabled by AXI_BW). |