Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > PL1_THR_CNT (CRL_APB) Register

PL1_THR_CNT (CRL_APB) Register

PL1_THR_CNT (CRL_APB) Register Description

Register NamePL1_THR_CNT
Relative Address0x00000000DC
Absolute Address 0x00FF5E00DC (CRL_APB)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionPL Clock 1 Threshold Count Value.

PL1_THR_CNT (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LAST_CNT15:0rwNormal read/write0x0The number of clocks after receiving a trigger that the clocks should stop