Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_LOCAL Module > L2_PWR_CNTRL (PMU_LOCAL) Register
Register Name | L2_PWR_CNTRL |
---|---|
Relative Address | 0x00000000B0 |
Absolute Address | 0x00FFD600B0 (PMU_LOCAL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000001 |
Description | L2 Cache Power Control. Reset by POR only. |
Controls the on-chip power switch: 0: power off. 1: power on. Field can only be read or written by the PMU processor. This register maintains its contents during a System Reset.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | roRead-only | 0x0 | reserved |
Bank0 | 0 | rwNormal read/write | 0x1 | Power switch enable for the L2 cache. |