Zynq UltraScale+ Devices Register Reference > Module Summary > A53_DBG_0 Module > EDECR (A53_DBG_0) Register

EDECR (A53_DBG_0) Register

EDECR (A53_DBG_0) Register Description

Register NameEDECR
Relative Address0x0000000024
Absolute Address 0x00FEC10024 (CORESIGHT_A53_DBG_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExternal Debug Execution Control Register

EDECR (A53_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SS 2rwNormal read/write0x0Halting step enable. Possible values of this field are:If the value of EDECR.SS is changed when the processor is in Non-debug state, the resulting value of EDECR.SS is UNKNOWN.
RCE 1rwNormal read/write0x0Reset catch enable. Possible values of this field are:
OSUCE 0rwNormal read/write0x0OS unlock catch enabled. Possible values of this field are: