Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > USBCMD (USB3_XHCI) Register

USBCMD (USB3_XHCI) Register

USBCMD (USB3_XHCI) Register Description

Register NameUSBCMD
Relative Address0x0000000020
Absolute Address 0x00FE200020 (USB3_0_XHCI)
0x00FE300020 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionUSB Command Register
For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.

USBCMD (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:14roRead-only0x0Reserved
CME13rwNormal read/write0CEM Enable
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Reserved12roRead-only0Reserved
EU3S11rwNormal read/write0EU3S
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
EWE10rwNormal read/write0EWE
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
CRS 9rwNormal read/write0Controller Restore State
This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to 1, the controller immediately sets DSTS.RSS to 1. When the controller has finished the restore process, it sets DSTS.RSS to 0.
Note: When read, this field always returns 0.
CSS 8rwNormal read/write0Controller Save State
This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to 1, the controller immediately sets DSTS.SSS to 1.
When the controller has finished the save process, it sets DSTS.SSS to 0.
Note: When read, this field always returns 0.
LHCRST 7rwNormal read/write0Light Host Controller Reset
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
The following bits reset the internal logic of the host controller. Under soft reset, some CSR accesses may fail (Timeout).
- HCRST
- LHCRST
Bit Bash register testing is not recommended.
Reserved 6:4roRead-only0x0Reserved
HSEE 3rwNormal read/write0HSEE
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
INTE 2rwNormal read/write0INTE
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
HCRST 1rwNormal read/write0HCRST
The following bits reset the internal logic of the host controller. Under soft reset, some CSR accesses may fail (Timeout).
- HCRST
- LHCRST
Bit Bash register testing is not recommended.
R_S 0rwNormal read/write0R_S
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Due to side-effects this reguster field is not recommended for Bit-Bash testing.