Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > PATGEN_CRC_G (DISPLAY_PORT) Register
Register Name | PATGEN_CRC_G |
---|---|
Relative Address | 0x000000CC14 |
Absolute Address | 0x00FD4ACC14 (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | 16 bit CRC calculated on the second component of video output from Internal Test Pattern Generator |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:16 | razRead as zero | 0x0 | |
CRC_G | 15:0 | roRead-only | 0x0 | - |