Zynq UltraScale+ Devices Register Reference > Module Summary > APM Module > FECR (APM) Register

FECR (APM) Register

FECR (APM) Register Description

Register NameFECR
Relative Address0x0000000400
Absolute Address 0x00FD490400 (APM_CCI_INTC)
0x00FFA00400 (APM_INTC_OCM)
0x00FFA10400 (APM_LPD_FPD)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionFlag Enable

0: disable. 1: enable.

FECR (APM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31rwNormal read/write0x0reserved.
Reserved30rwNormal read/write0x0reserved.
Reserved29rwNormal read/write0x0reserved.
Reserved28rwNormal read/write0x0reserved.
Reserved27rwNormal read/write0x0reserved.
Reserved26rwNormal read/write0x0reserved.
Reserved25rwNormal read/write0x0reserved.
Reserved24rwNormal read/write0x0reserved.
Reserved23rwNormal read/write0x0reserved.
Reserved22rwNormal read/write0x0reserved.
SMP_CNT_LAPSE_FLG21rwNormal read/write0x0Enable Sample Counter Lapse flag
GCC_OFVL_FLG20rwNormal read/write0x0Enable Global Clock count overflow flag
Reserved19rwNormal read/write0x0reserved.
Reserved18rwNormal read/write0x0reserved.
Reserved17rwNormal read/write0x0reserved.
SFT_DATA_FLG_EN16rwNormal read/write0x0Enable software-written data flag
Reserved15:7razRead as zero0x0reserved.
LAST_READ_FLG 6rwNormal read/write0x0Enable Last Read flag
FIRST_READ_FLG 5rwNormal read/write0x0Enable First Read flag
READ_ADDR_FLG 4rwNormal read/write0x0Enable Read Addr flag
RESPONSE_FLG 3rwNormal read/write0x0Enable Responese flag
LAST_WRITE_FLG 2rwNormal read/write0x0Enable Last Write flag
FIRST_WRITE_FLG 1rwNormal read/write0x0Enable First Write flag
WRITE_ADDR_FLG 0rwNormal read/write0x0Enable Write Addr flag