Zynq UltraScale+ Devices Register Reference > Module Summary > A53_PMU_0 Module > CIDR1 (A53_PMU_0) Register

CIDR1 (A53_PMU_0) Register

CIDR1 (A53_PMU_0) Register Description

Register NameCIDR1
Relative Address0x0000000FF4
Absolute Address 0x00FEC30FF4 (CORESIGHT_A53_PMU_0)
Width32
TyperoRead-only
Reset Value0x00000090
DescriptionPerformance Monitors Component Identification Register 1

CIDR1 (A53_PMU_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLASS 7:4roRead-only0x9Component class. Reads as 0x9, debug component.
PRMBL_1 3:0roRead-only0x0Preamble. RAZ.