Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > PMEVCNTR1 (SMMU500) Register

PMEVCNTR1 (SMMU500) Register

PMEVCNTR1 (SMMU500) Register Description

Register NamePMEVCNTR1
Relative Address0x0000003004
Absolute Address 0x00FD803004 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.

PMEVCNTR1 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PMN131:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details