Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_VENDOR Module > PTS (SATA_AHCI_VENDOR) Register

PTS (SATA_AHCI_VENDOR) Register

PTS (SATA_AHCI_VENDOR) Register Description

Register NamePTS
Relative Address0x000000002C
Absolute Address 0x00FD0C00CC (SATA_AHCI_VENDOR)
Width32
TyperoRead-only
Reset Value0x0000012D
DescriptionTransport Layer Status (TransStatus).

This register can be read to determine the status of the Transport Layer for either Port 0 or Port 1. The Port monitored is controlled by the value programmed into the Port Config Register. Note: All Status Registers have no predefined Reset value. The value shown in reset is a typical value that will be read after reset but will be dependent on the SERDES status, the actual value read can differ from this.

PTS (SATA_AHCI_VENDOR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9roRead-only0x0Reserved
TXSM 8:4roRead-only0x12Tx State Machine (TXSM) states
0: TxTrnIdle
1: TxTrnReset
2: TxTrnWaitResetComplete
3: TxTrnNonDataInitial
4: TxTrnNonDataAbort
5: TxTrnNonDataSend
6: TxTrnNonDataComp
7: TxTrnNonDataOk
8: TxTrnNonDataNotOk
9: TxTrnDataHeader
10: TxTrnDataHeaderOut
11: TxTrnDataSend
12: TxTrnDataComp
13: TxTrnDataNotOk
14: TxTrnDataOk
15: TxTrnCmdReset
16: TxTrnCmdResetComp
17: TxTrnCmdResetOverFlow
18: TxTrnNonDataBackDown
RXSM 3:0roRead-only0xDRx State Machine (RXSM) tates
0: p_rx_idle
1: p_rx_enable
2: p_rx_datafis
3: p_rx_datafis_rxd
4: p_rx_nondatafis
5: p_rx_unknownfis
6: p_rx_unknownfis_rxd
7: p_rx_badcrc
8: p_rx_good
9: p_rx_bad
10: p_rx_reset
11: p_rx_cmdreset
12: p_rx_cmdreset_comp
13: p_rx_reset_oflow
14: p_rx_forcebad