Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_PHY_STATUS (DISPLAY_PORT) Register

DP_PHY_STATUS (DISPLAY_PORT) Register

DP_PHY_STATUS (DISPLAY_PORT) Register Description

Register NameDP_PHY_STATUS
Relative Address0x0000000280
Absolute Address 0x00FD4A0280 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionProvides the current status from the PHY.

DP_PHY_STATUS (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0
Reserved 7:6roRead-only0x0reserved.
Reserved 5roRead-only0x0
PLL_LOCKED 4roRead-only0x0GT PLL locked status
RATE_CHANGE_DONE_0_1 3:2roRead-only0x0Received PHYSTATUS pulse from GT after rate change request from lanes 0(bit2) and 1(bit3)
RESET_LANES_0_1 1:0roRead-only0x0Reset done for lanes 0 and 1.