Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module > CSUPMU_WDT_CLK_SEL (LPD_SLCR) Register

CSUPMU_WDT_CLK_SEL (LPD_SLCR) Register

CSUPMU_WDT_CLK_SEL (LPD_SLCR) Register Description

Register NameCSUPMU_WDT_CLK_SEL
Relative Address0x0000000050
Absolute Address 0x00FF410050 (LPD_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSWDT clock source select

CSUPMU_WDT_CLK_SEL (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SELECT 0rwNormal read/write0x0System watchdog timer clock source selection:
0: internal clock APB interface clock; LPD_LSBUS_CLK
1: external clock PS_REF_CLK