Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > aes_kup_wr (CSU) Register

aes_kup_wr (CSU) Register

aes_kup_wr (CSU) Register Description

Register Nameaes_kup_wr
Relative Address0x000000101C
Absolute Address 0x00FFCA101C (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAES KUP Write Control

aes_kup_wr (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
iv_write 1rwNormal read/write0x0When this bit is set the IV register will be written with the output of the AES. This bit can be combined with the KUP_WRITE to write the KUP and IV at the same time. The data format is {KUP0:KUP7,IV0:IV3}. All registers must be written before the key/iv will be updated.
kup_write 0rwNormal read/write0x0When this bit is set, the output of the AES will be written into the KUP. This bit can be combined with the IV_WRITE to write the KUP and IV at the same time. All 12 registers must be written to in order to correctly set the KUP and IV values. The data must be loaded {KUP0:KUP7,IV0:IV3}