Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L2_TM_CDR16 (SERDES) Register

L2_TM_CDR16 (SERDES) Register

L2_TM_CDR16 (SERDES) Register Description

Register NameL2_TM_CDR16
Relative Address0x0000009C40
Absolute Address 0x00FD409C40 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L2_TM_CDR16 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_CDR16_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
UNUSED 7:5roRead-only0x0Value generated by PCW.
ffl_ph0_prop_gain 4:0rwNormal read/write0x0Value generated by PCW.