Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module > CSUPMU_WDT_CLK_SEL (LPD_SLCR) Register
Register Name | CSUPMU_WDT_CLK_SEL |
---|---|
Relative Address | 0x0000000050 |
Absolute Address | 0x00FF410050 (LPD_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | SWDT clock source select |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
SELECT | 0 | rwNormal read/write | 0x0 | System watchdog timer clock source selection: 0: internal clock APB interface clock; LPD_LSBUS_CLK 1: external clock PS_REF_CLK |