Zynq UltraScale+ Devices Register Reference > Module Summary > GIC400 Module > GICD_ISENABLER3 (GIC400) Register

GICD_ISENABLER3 (GIC400) Register

GICD_ISENABLER3 (GIC400) Register Description

Register NameGICD_ISENABLER3
Relative Address0x000001010C
Absolute Address 0x00F901010C (ACPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionInterrupt Set-Enable Registers

GICD_ISENABLER3 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.