Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_QOS_CTRL Module > DDRC_MRR_STATUS (DDR_QOS_CTRL) Register

DDRC_MRR_STATUS (DDR_QOS_CTRL) Register

DDRC_MRR_STATUS (DDR_QOS_CTRL) Register Description

Register NameDDRC_MRR_STATUS
Relative Address0x0000000518
Absolute Address 0x00FD090518 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDDRC MRR Register Status

DDRC_MRR_STATUS (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4razRead as zero0x0Reserved for future use
VALID_CNT 3:1roRead-only0x0Indicate How many valid data available in FIFO.
VALID 0roRead-only0x0Indicate Valid data is available in FIFO.