Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > IOU_TAPDLY_BYPASS (IOU_SLCR) Register

IOU_TAPDLY_BYPASS (IOU_SLCR) Register

IOU_TAPDLY_BYPASS (IOU_SLCR) Register Description

Register NameIOU_TAPDLY_BYPASS
Relative Address0x0000000390
Absolute Address 0x00FF180390 (IOU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000007
DescriptionTap Delay enables for the LQSPI and NAND controllers.

IOU_TAPDLY_BYPASS (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:3razRead as zero0x0Reserved. Writes are ignored, read data is zero.
LQSPI_RX 2rwNormal read/write0x1LQSPI Tap Delay Enable on Rx Clock signal.
0: enable.
1: disable (bypass tap delay).
NAND_DQS_OUT 1rwNormal read/write0x1NAND Tap Delay Enable on DQS Output signal.
0: enable.
1: disable (bypass tap delay).
NAND_DQS_IN 0rwNormal read/write0x1NAND Tap Delay Enable on DQS Input signal.
0: enable.
1: disable (bypass tap delay).