Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > TX_thres (SPI) Register

TX_thres (SPI) Register

TX_thres (SPI) Register Description

Register NameTX_thres
Relative Address0x0000000028
Absolute Address 0x00FF040028 (SPI0)
0x00FF050028 (SPI1)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionTX FIFO Threshold

TX_thres (SPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Threshold_of_TX_FIFO31:0rwNormal read/write0x1Defines the level at which the TX FIFO not full interrupt is generated
Change only when controller is not actively transmitting or receiving data.