Zynq UltraScale+ Devices Register Reference > Module Summary > ETR Module > ITATBCTR2 (ETR) Register
Register Name | ITATBCTR2 |
---|---|
Relative Address | 0x0000000EF0 |
Absolute Address | 0x00FE970EF0 (CORESIGHT_SOC_ETR) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | The Integration Test ATB Control Register 2 enables control of the ATREADYS and AFVALIDS outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
SYNCREQS | 2 | woWrite-only | 0x0 | Set the value of SYNCREQS output |
AFVALIDS | 1 | woWrite-only | 0x0 | Set the value of AFVALIDS output |
ATREADYS | 0 | woWrite-only | 0x0 | Set the value of ATREADYS output |