Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_IOMODULE Module > GPO1 (PMU_IOMODULE) Register
Register Name | GPO1 |
---|---|
Relative Address | 0x0000000014 |
Absolute Address | 0x00FFD40014 (PMU_IOMODULE) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | PMU to MIO Signals (GPO1) |
GPOs assigned to MIO for signaling and Power Supply Management
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:11 | razRead as zero | 0x0 | reserved |
Reserved | 10 | razRead as zero | 0x0 | reserved |
Reserved | 9:6 | razRead as zero | 0x0 | reserved |
MIO_5 | 5 | woWrite-only | 0x0 | GPO to MIO |
MIO_4 | 4 | woWrite-only | 0x0 | GPO to MIO |
MIO_3 | 3 | woWrite-only | 0x0 | GPO to MIO |
MIO_2 | 2 | woWrite-only | 0x0 | GPO to MIO |
MIO_1 | 1 | woWrite-only | 0x0 | GPO to MIO |
MIO_0 | 0 | woWrite-only | 0x0 | GPO to MIO |
This register holds the value that will be driven to the corresponding bits in the I/O Module GPO2 port output signals.
All bits are in the register are updated wihen the register is written.