Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_PIN_67 (IOU_SLCR) Register

MIO_PIN_67 (IOU_SLCR) Register

MIO_PIN_67 (IOU_SLCR) Register Description

Register NameMIO_PIN_67
Relative Address0x000000010C
Absolute Address 0x00FF18010C (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 67 Multiplexer Controls.

MIO_PIN_67 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [67] input/output bank 2.
1: CAN0 TX output.
2: I2C0 SDA input/output.
3: LPD SWDT reset output.
4: SPI0 SS [0] input/output.
5: TTC2 waveform output.
6: UART0 TxD output.
7: TracePort DQ[13] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: SDIO0 Data [0] input/output.
2: reserved
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: USB1 ULPI Next input.
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM3 RGMII Tx Data [2] output.
Reserved 0rwNormal read/write0x0reserved