Zynq UltraScale+ Devices Register Reference > Module Summary > GEM Module > upper_tx_q_base_addr (GEM) Register
Register Name | upper_tx_q_base_addr |
---|---|
Relative Address | 0x00000004C8 |
Absolute Address |
0x00FF0B04C8 (GEM0) 0x00FF0C04C8 (GEM1) 0x00FF0D04C8 (GEM2) 0x00FF0E04C8 (GEM3) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Upper 32 bits of transmit buffer descriptor queue base address. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
upper_tx_q_base_addr | 31:0 | rwNormal read/write | 0x0 | Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.) |