Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_DEC_TOP Module > AXI_WBW0 (VCU_DEC_TOP) Register

AXI_WBW0 (VCU_DEC_TOP) Register

AXI_WBW0 (VCU_DEC_TOP) Register Description

Register NameAXI_WBW0
Relative Address0x0000009218
Absolute Address 0x00A0029218 (VCU_DECODE)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAXI Write Bandwidth Status 0

AXI_WBW0 (VCU_DEC_TOP) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
AxiWriteBwStatus031:0roRead-only0x0Returns the number of 128-bit words written by the AXI master port 0 during the preceding bandwidth measurement window (when enabled by AXI_BW).