Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > ISR (SPI) Register
Register Name | ISR |
---|---|
Relative Address | 0x0000000004 |
Absolute Address |
0x00FF040004 (SPI0) 0x00FF050004 (SPI1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000004 |
Description | SPI interrupt status |
This register is set when the described event occurs and the interrupt is enabled in the mask register. When any of these bits are set the interrupt output is asserted high. In the default configuration, these bits are all cleared simultaneously by reading this register, though this may be configured for an individual write-one-to-clear scheme.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:7 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
TX_FIFO_underflow | 6 | wtcReadable, write a 1 to clear | 0x0 | TX FIFO underflow, write one to this bit location to clear. 1: underflow is detected 0: no underflow has been detected |
RX_FIFO_full | 5 | wtcReadable, write a 1 to clear | 0x0 | RX FIFO full 1: FIFO is full 0: FIFO is not full |
RX_FIFO_not_empty | 4 | wtcReadable, write a 1 to clear | 0x0 | RX FIFO not empty 1: FIFO has more than or equal to THRESHOLD entries 0: FIFO has less than RX THRESHOLD entries |
TX_FIFO_full | 3 | wtcReadable, write a 1 to clear | 0x0 | TX FIFO full 1: FIFO is full 0: FIFO is not full |
TX_FIFO_not_full | 2 | wtcReadable, write a 1 to clear | 0x1 | TX FIFO not full 1: FIFO has less than THRESHOLD entries 0: FIFO has more than or equal toTHRESHOLD entries |
MODE_FAIL | 1 | wtcReadable, write a 1 to clear | 0x0 | Logic level on n_ss_in pin is inconsistent with the SPI mode. 1: Use if n_ss_in is low in master mode (multi-master contention) or n_ss_in goes high during a transmission in slave mode. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read. ModeFail interrupt, write one to this bit location to clear. 1: a mode fault has occurred 0: no mode fault has been detected |
RX_OVERFLOW | 0 | wtcReadable, write a 1 to clear | 0x0 | Receive Overflow interrupt, write one to this bit location to clear. 1: overflow occured 0: no overflow occurred |