Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB2_TTBR1_high (SMMU500) Register

SMMU_CB2_TTBR1_high (SMMU500) Register

SMMU_CB2_TTBR1_high (SMMU500) Register Description

Register NameSMMU_CB2_TTBR1_high
Relative Address0x000001202C
Absolute Address 0x00FD81202C (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe Translation Table Base register 0 holds the base address of the translation table 1.

SMMU_CB2_TTBR1_high (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ASID31:16rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
address15:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details