Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AUD_CH_STATUS_REG0 (DISPLAY_PORT) Register
Register Name | AUD_CH_STATUS_REG0 |
---|---|
Relative Address | 0x000000C008 |
Absolute Address | 0x00FD4AC008 (DISPLAY_PORT) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | AUD_CH_STATUS_REG0: Audio Channel status bits 31 to 0 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
STATUS0 | 31:0 | rwNormal read/write | 0x0 | - |