Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > HCSPARAMS1 (USB3_XHCI) Register
Register Name | HCSPARAMS1 |
---|---|
Relative Address | 0x0000000004 |
Absolute Address |
0x00FE200004 (USB3_0_XHCI) 0x00FE300004 (USB3_1_XHCI) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Structural Parameters 1 Register For register definitions, refer to the xHCI specification. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
MAXPORTS | 31:24 | roRead-only | 0 | Number of Ports (MaxPorts) - Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS) - Number of ports enabled is controlled by the core input signals host_num_u2_port[3:0]+host_num_u3_port[3:0] Note: In USB 2.0-only mode, the host_num_u3_port signal is zero. |
Reserved | 23:19 | roRead-only | 0x0 | Reserved |
MAXINTRS | 18:8 | roRead-only | 0 | Number of Interrupters (MaxIntrs) Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT |
MAXSLOTS | 7:0 | roRead-only | 0 | Number of device slots (MaxSlots) Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT |