Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > SAFETY_GATE (PMU_GLOBAL) Register
Register Name | SAFETY_GATE |
---|---|
Relative Address | 0x0000000650 |
Absolute Address | 0x00FFD80650 (PMU_GLOBAL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000007 |
Description | Safety gates disable hardware functions. |
Disable hardware functions against accidental enabling. Register is reset only by a POR reset.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:3 | roRead-only | 0x0 | |
PMU_LOGCLR_Enable | 2 | rwNormal read/write | 0x1 | PMU Logic Clear Gate Function. If set to 0, it would prevent PMU Logic Clear function from being accidentally enabled. |
LBIST_Enable | 1 | rwNormal read/write | 0x1 | After a POR reset, the PMU hardware generates a signal to the LBIST controllers. Set [LBIST_Enable] = 0 to help prevent an SEU in the signaling hardware from inadvertently causing LBIST operations to occur during normal operating mode. |
Scan_Enable | 0 | rwNormal read/write | 0x1 | Scan Clear Function Enable. Set [Scan_Enable] = 0 to help prevent inadvertent assertion of the scan clear signal by software or an SEU in the hardware. |