Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > HEMASTR (STM) Register

HEMASTR (STM) Register

HEMASTR (STM) Register Description

Register NameHEMASTR
Relative Address0x0000000DF4
Absolute Address 0x00FE9C0DF4 (CORESIGHT_SOC_STM)
Width32
TyperoRead-only
Reset Value0x00000080
DescriptionMaster Number in Event Trace

Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2.

HEMASTR (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MASTER15:0roRead-only0x80The STPv2 master number for hardware event trace:
80h: master number.