Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PIDR7 (SMMU500) Register

SMMU_PIDR7 (SMMU500) Register

SMMU_PIDR7 (SMMU500) Register Description

Register NameSMMU_PIDR7
Relative Address0x0000000FDC
Absolute Address 0x00FD800FDC (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPeripheral Identificaation register 7

SMMU_PIDR7 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details