Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_101 (PCIE_ATTRIB) Register
Register Name | ATTR_101 |
---|---|
Relative Address | 0x0000000194 |
Absolute Address | 0x00FD480194 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | ATTR_101 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_enable_msg_route | 15:5 | rwNormal read/write | 0x0 | Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message TLP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off |
attr_disable_rx_poisoned_resp | 4 | rwNormal read/write | 0x0 | Disable error message and status bit response due to receiving a Poisoned TLP. |
attr_disable_rx_tc_filter | 3 | rwNormal read/write | 0x0 | Disable TC filtering of received TLPs |
attr_disable_id_check | 2 | rwNormal read/write | 0x0 | Disable checking for Requester ID of received completions |
attr_disable_bar_filtering | 1 | rwNormal read/write | 0x0 | Disable BAR filtering. Does not change the behavior of the bar hit outputs |
attr_disable_aspm_l1_timer | 0 | rwNormal read/write | 0x0 | Disables the internal timer that causes an Upstream Port enter into ASPM L1. |