Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > GP_CONTR_REG_PLB_ALLOC_END_ADDR (GPU) Register
Register Name | GP_CONTR_REG_PLB_ALLOC_END_ADDR |
---|---|
Relative Address | 0x0000000014 |
Absolute Address | 0x00FD4B0014 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | GP Control Register PLB Allocate End Address |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
GP_CONTR_REG_PLB_ALLOC_END_ADDR | 31:7 | rwNormal read/write | 0x0 | End address for the polygon list allocation |
Reserved | 6:0 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined |