Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > MASK_DATA_2_MSW (GPIO) Register

MASK_DATA_2_MSW (GPIO) Register

MASK_DATA_2_MSW (GPIO) Register Description

Register NameMASK_DATA_2_MSW
Relative Address0x0000000014
Absolute Address 0x00FF0A0014 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMaskable Output Data (GPIO Bank2, MIO, Upper 10 bits)

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 10 bits of bank2, which corresponds to MIO[77:68].

MASK_DATA_2_MSW (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26razRead as zero0x0Not used, read back as zero
MASK_2_MSW25:16woWrite-only0x0Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW]
Reserved15:10razRead as zero0x0Not used, read back as zero
DATA_2_MSW 9:0rwNormal read/write0Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW]