Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DTCR1 (DDR_PHY) Register
Register Name | DTCR1 |
---|---|
Relative Address | 0x0000000204 |
Absolute Address | 0x00FD080204 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00030237 |
Description | Data Training Configuration Register 1 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
RANKEN_RSVD | 31:18 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
RANKEN | 17:16 | rwNormal read/write | 0x3 | Rank Enable: Specifies the ranks that are enabled for data-training and write leveling. Bit 0 controls rank 0, bit 1 controls rank 1, etc. Setting the bit to 1b1 enables the rank, and setting it to 1b0 disables the rank. This setting also specifies the ranks that are enabled for DQS drift detection and compensation. |
Reserved | 15:14 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
DTRANK | 13:12 | rwNormal read/write | 0x0 | Data Training Rank: Selects the SDRAM rank to be used during data bit deskew. |
Reserved | 11 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
RDLVLGDIFF | 10:8 | rwNormal read/write | 0x2 | Read Leveling Gate Sampling Difference: width of DQS sampling window. Encoded as a fraction of the DDR clock period follows: 0b000: GDQSPRD/4 0b001: GDQSPRD/4 0b010: GDQSPRD/8 0b011: GDQSPRD/16 0b100: GDQSPRD/32 0b101: GDQSPRD/64 0b110: GDQSPRD/128 0b111: GDQSPRD/256 |
Reserved | 7 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
RDLVLGS | 6:4 | rwNormal read/write | 0x3 | Read Leveling Gate Shift: delay reduction to apply to gate after it has been aligned to DQS. Encoded as a fraction of the DDR clock period follows: 0b000: 0 0b001: GDQSPRD/4 0b010: GDQSPRD/8 0b011: GDQSPRD/16 0b100: GDQSPRD/32 0b101: GDQSPRD/64 0b110: GDQSPRD/128 0b111: GDQSPRD/256 |
Reserved | 3 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
RDPRMVL_TRN | 2 | rwNormal read/write | 0x1 | Read Preamble Training enable: engages read preamble training mode in DDR4 DRAM during gate training |
RDLVLEN | 1 | rwNormal read/write | 0x1 | Read Leveling Enable: Run a DQS sampling scheme using the gate to align the rising edges of DQS and the gate after which a delay reduction is applied to the gate (see RDLVLGS). Note: This bit should not be enabled when the gate is extended |
BSTEN | 0 | rwNormal read/write | 0x1 | Basic Gate Training Enable: Runs a trial and error algorithm to progressively evaluate gate positions and narrow down to a working one |