Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_WB0_TARGET_PIXEL_FORMAT (GPU) Register

PP1_WB0_TARGET_PIXEL_FORMAT (GPU) Register

PP1_WB0_TARGET_PIXEL_FORMAT (GPU) Register Description

Register NamePP1_WB0_TARGET_PIXEL_FORMAT
Relative Address0x000000A108
Absolute Address 0x00FD4BA108 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionWB0 Target Pixel Format Register

PP1_WB0_TARGET_PIXEL_FORMAT (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4rwNormal read/write0x0Reserved, write as zero, read undefined.
WB0_TARGET_PIXEL_FORMAT 3:0rwNormal read/write0x0Contains the pixel format of the target buffer