Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB15_PMCNTENSE (SMMU500) Register

SMMU_CB15_PMCNTENSE (SMMU500) Register

SMMU_CB15_PMCNTENSE (SMMU500) Register Description

Register NameSMMU_CB15_PMCNTENSE
Relative Address0x000001FF40
Absolute Address 0x00FD81FF40 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionProvides the equivalent of the PMCNTENSETx register, in the register map of a translation context bank. Enables any implemented event counters.

SMMU_CB15_PMCNTENSE (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P3 3woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2 2woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1 1woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P0 0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details