Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > PIDR7 (TSGEN) Register

PIDR7 (TSGEN) Register

PIDR7 (TSGEN) Register Description

Register NamePIDR7
Relative Address0x0000000FDC
Absolute Address 0x00FE900FDC (CORESIGHT_SOC_TSGEN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionReserved

PIDR7 (TSGEN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0reserved