Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > enable_legacy_int_n (PL390) Register
Register Name | enable_legacy_int_n |
---|---|
Relative Address | 0x0000000DD4 |
Absolute Address | 0x00F9000DD4 (RCPU_GIC) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Enables an external AMBA master to access the status of the: legacy_nirq_c<n> and legacy_nfiq_c<n> inputs for CPU Interface <n>, cfgsdisable tie-off signal. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
cfgsdisable | 2 | roRead-only | 0x0 | Returns the status of the cfgsdisable tie-off signal. |
legacy_nfiq_if_n | 1 | roRead-only | 0x0 | Returns the status of the legacy FIQ input signal for CPU Interface <n>. |
legacy_nirq_if_n | 0 | roRead-only | 0x0 | Returns the status of the legacy IRQ input signal for CPU Interface <n>. |