Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > MASK_DATA_1_LSW (GPIO) Register
Register Name | MASK_DATA_1_LSW |
---|---|
Relative Address | 0x0000000008 |
Absolute Address | 0x00FF0A0008 (GPIO) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) |
This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16 bits of bank1, which corresponds to MIO[41:26].
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
MASK_1_LSW | 31:16 | woWrite-only | 0x0 | Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW] |
DATA_1_LSW | 15:0 | rwNormal read/write | 0 | Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW] |