Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_PERF_CNT_0_ENABLE (GPU) Register

PP0_PERF_CNT_0_ENABLE (GPU) Register

PP0_PERF_CNT_0_ENABLE (GPU) Register Description

Register NamePP0_PERF_CNT_0_ENABLE
Relative Address0x0000009080
Absolute Address 0x00FD4B9080 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Counter 0 Enable Register

PP0_PERF_CNT_0_ENABLE (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2rwNormal read/write0x0Reserved, write as zero, read undefined.
PERF_CNT_0_LIM_EN 1rwNormal read/write0x0When set to 1, the PERF_CNT_0_LIMIT Register becomes active. If the
PERF_CNT_0_VALUE Register exceeds the Performance Counter 0 Limit
value, then an interrupt is asserted and the BUS_STOPPED mechanism stops the bus.
The PERF_CNT_0_VALUE Register is reset to zero if you write to
PERF_CNT_0_ENABLE while the counter is enabled, that is, the
PERF_CNT_0_ENABLE bit is 1.
PERF_CNT_0_ENABLE 0rwNormal read/write0x0When set to 1, the performance counter 0 is reset to zero and activated. The
PERF_CNT_0_SRC Register selects the event to be counted during a frame.