Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB14_TLBSYNC (SMMU500) Register

SMMU_CB14_TLBSYNC (SMMU500) Register

SMMU_CB14_TLBSYNC (SMMU500) Register Description

Register NameSMMU_CB14_TLBSYNC
Relative Address0x000001E7F0
Absolute Address 0x00FD81E7F0 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInitiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.

SMMU_CB14_TLBSYNC (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details