Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_ILL15 (SERDES) Register

L0_TM_ILL15 (SERDES) Register

L0_TM_ILL15 (SERDES) Register Description

Register NameL0_TM_ILL15
Relative Address0x00000019A8
Absolute Address 0x00FD4019A8 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_ILL15 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_ILL15_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
ill_cal_ref_ctr_msb_reg1 7:0rwNormal read/write0x0Value generated by PCW.