Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > RPLL_TO_FPD_CTRL (CRL_APB) Register

RPLL_TO_FPD_CTRL (CRL_APB) Register

RPLL_TO_FPD_CTRL (CRL_APB) Register Description

Register NameRPLL_TO_FPD_CTRL
Relative Address0x0000000048
Absolute Address 0x00FF5E0048 (CRL_APB)
Width16
TyperwNormal read/write
Reset Value0x00000400
DescriptionRPLL clock divider for distribution in FPD.

Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock generators.

RPLL_TO_FPD_CTRL (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15:14rwNormal read/write0x0reserved
DIVISOR013:8rwNormal read/write0x46-bit divider.
Reserved 7:0rwNormal read/write0x0reserved