Zynq UltraScale+ Devices Register Reference > Module Summary > SIOU Module > dp_stc_clkctrl (SIOU) Register

dp_stc_clkctrl (SIOU) Register

dp_stc_clkctrl (SIOU) Register Description

Register Namedp_stc_clkctrl
Relative Address0x0000000430
Absolute Address 0x00FD3D0430 (SIOU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000001
Descriptiondp_stc_ref_clk control register

dp_stc_clkctrl (SIOU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11roRead-only0x0Reserved
refsel10rwNormal read/write0x00 - bypass divider; 1 - Use divider output
lanesel 9:8rwNormal read/write0x0Select which lane refclk should be used as STC clock source
uptog 7rwNormal read/write0x0Pulse this bit after divisor value change
divisor 6:1rwNormal read/write0x0Divisor value for the divider
soft_rst 0rwNormal read/write0x1Reset for the clock divider