Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_MAIN Module > MSGF_MSI_MASK_HI (AXIPCIE_MAIN) Register

MSGF_MSI_MASK_HI (AXIPCIE_MAIN) Register

MSGF_MSI_MASK_HI (AXIPCIE_MAIN) Register Description

Register NameMSGF_MSI_MASK_HI
Relative Address0x000000044C
Absolute Address 0x00FD0E044C (AXIPCIE_MAIN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMSI Interrupt Mask[63:32].

MSGF_MSI_MASK_HI (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
msgf_msi_mask31:0rwNormal read/write0x0MSI Interrupt Per Vector Mask. An interrupt is generated on the int_msi[1] output port when (msgf_msi_status[63:32] & msgf_msi_mask[63:32]) != 0.