Zynq UltraScale+ Devices Register Reference > Module Summary > GIC400 Module > GICD_CIDR0 (GIC400) Register

GICD_CIDR0 (GIC400) Register

GICD_CIDR0 (GIC400) Register Description

Register NameGICD_CIDR0
Relative Address0x0000010FF0
Absolute Address 0x00F9010FF0 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x0000000D
DescriptionComponent ID0 Register

GICD_CIDR0 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0xDRefer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.