Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_DMA Module > DMA_CHANNEL_SCRATCH3 (AXIPCIE_DMA) Register

DMA_CHANNEL_SCRATCH3 (AXIPCIE_DMA) Register

DMA_CHANNEL_SCRATCH3 (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_SCRATCH3
Relative Address0x000000005C
Absolute Address 0x00FD0F005C (AXIPCIE_DMA0)
0x00FD0F00DC (AXIPCIE_DMA1)
0x00FD0F015C (AXIPCIE_DMA2)
0x00FD0F01DC (AXIPCIE_DMA3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionScratchpad Register

DMA_CHANNEL_SCRATCH3 (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
scratch331:0rwNormal read/write0x0Scratchpad Register. Intended to enable information to be passed between sofwtare. For example, applications with both an AXI CPU and an PCIe CPU may use this register to pass information between CPUs. The DMA Channel implementation does not use or alter this information.