Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > RPLL_CFG (CRL_APB) Register

RPLL_CFG (CRL_APB) Register

RPLL_CFG (CRL_APB) Register Description

Register NameRPLL_CFG
Relative Address0x0000000034
Absolute Address 0x00FF5E0034 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRPLL Integer Helper Data Configuration.

RPLL_CFG (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LOCK_DLY31:25rwNormal read/write0x0Lock circuit configuration settings for lock windowsize
Reserved24:23rwNormal read/write0x0reserved.
LOCK_CNT22:13rwNormal read/write0x0Lock circuit counter setting
Reserved12rwNormal read/write0x0reserved.
LFHF11:10rwNormal read/write0x0PLL loop filter high frequency capacitor control
Reserved 9rwNormal read/write0x0reserved.
CP 8:5rwNormal read/write0x0PLL charge pump control
Reserved 4rwNormal read/write0x0reserved.
RES 3:0rwNormal read/write0x0PLL loop filter resistor control