Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_presetvalue0 (SDIO) Register

reg_presetvalue0 (SDIO) Register

reg_presetvalue0 (SDIO) Register Description

Register Namereg_presetvalue0
Relative Address0x0000000060
Absolute Address 0x00FF160060 (SD0)
0x00FF170060 (SD1)
Width16
TyperoRead-only
Reset Value0x00000100
DescriptionThis register is used to read the SDCLK Frequency Select Value,Clock Generator Select Value,Driver Strength Select Value

reg_presetvalue0 (SDIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DriverStrengthSelectValue15:14roRead-only0x0Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
00 Driver Type B is Selected
01 Driver Type A is Selected
10 Driver Type C is Selected
11 Driver Type D is Selected
ClockGeneratorSelectValue10roRead-only0x0This bit is effective when Host Controller supports programmable clock
0
Host Controller Ver2.00 Compatible Clock Generator
1 Programmable Clock Generator
SDCLKFrequencySelectValue 9:0roRead-only0x10010-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.