Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_104 (PCIE_ATTRIB) Register

ATTR_104 (PCIE_ATTRIB) Register

ATTR_104 (PCIE_ATTRIB) Register Description

Register NameATTR_104
Relative Address0x00000001A0
Absolute Address 0x00FD4801A0 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x000003FF
DescriptionATTR_104

This register should only be written to during reset of the PCIe block

ATTR_104 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_vc0_rx_ram_limit12:0rwNormal read/write0x3FFthe receive ram limit address default is two brams
When UR_ATOMIC is 0 the equation to calculate bytes advertised in flow control credits is:
(ph * (rx_td_ecrc_trim ? 16: 24)) + (pd * 16) + (nph * (rx_td_ecrc_trim ? 16: 24)) + (npd*16) + (ch * 16) + (cd * 16)
When UR_ATOMIC is 1 the equation to calculate bytes advertiesed in flow control credits is:
The equation to calculate bytes advertised is (same as mont blanc):
(ph * (rx_td_ecrc_trim ? 16: 24)) + (pd * 16) + (nph * 24) + (ch * 16) + (cd * 16)
The equation to calculate bram bytes available is:
(vc0_rx_ram_limit + 1) * 8