Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module > GICP_PMU_IRQ_MASK (LPD_SLCR) Register

GICP_PMU_IRQ_MASK (LPD_SLCR) Register

GICP_PMU_IRQ_MASK (LPD_SLCR) Register Description

Register NameGICP_PMU_IRQ_MASK
Relative Address0x00000080A4
Absolute Address 0x00FF4180A4 (LPD_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x000000FF
DescriptionInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.

GICP_PMU_IRQ_MASK (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0Reserved for future use
Reserved 7roRead-only0x1reserved.
Reserved 6roRead-only0x1reserved.
Reserved 5roRead-only0x1reserved.
src4 4roRead-only0x1Create single interrupt source for PMU from GICP4
src3 3roRead-only0x1Create single interrupt source for PMU from GICP3
src2 2roRead-only0x1Create single interrupt source for PMU from GICP2
src1 1roRead-only0x1Create single interrupt source for PMU from GICP1
src0 0roRead-only0x1Create single interrupt source for PMU from GICP0