Zynq UltraScale+ Devices Register Reference > Module Summary > A53_PMU_1 Module > CCNTR_EL0_31to0 (A53_PMU_1) Register

CCNTR_EL0_31to0 (A53_PMU_1) Register

CCNTR_EL0_31to0 (A53_PMU_1) Register Description

Register NameCCNTR_EL0_31to0
Relative Address0x00000000F8
Absolute Address 0x00FED300F8 (CORESIGHT_A53_PMU_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Cycle Counter (low word)

CCNTR_EL0_31to0 (A53_PMU_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CCNT31:0rwNormal read/write0x0Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C.