Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TM_DIG_10 (SERDES) Register
Register Name | L3_TM_DIG_10 |
---|---|
Relative Address | 0x000000D07C |
Absolute Address | 0x00FD40D07C (SERDES) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000001 |
Description | Register value is generated by Vivado PCW. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
TM_DIG_10_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
Reserved | 7:4 | roRead-only | 0x0 | Value generated by PCW. |
cdr_bit_lock_time | 3:0 | rwNormal read/write | 0x1 | Value generated by PCW. |