Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TM_CALIB_DIG19 (SERDES) Register
Register Name | L3_TM_CALIB_DIG19 |
---|---|
Relative Address | 0x000000EC4C |
Absolute Address | 0x00FD40EC4C (SERDES) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Register value is generated by Vivado PCW. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
TM_CALIB_DIG19_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
PIPE_PSW_CODE_OR_1 | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
PIPE_PSW_CODE_OR_0 | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
TM_OR_PIPE_PSW_CODE | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
FORCE_EN_PIPE_PSW | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
TM_OR_EN_PIPE_PSW | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
PIPE_NSW_CODE_OR_5 | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
PIPE_NSW_CODE_OR_4 | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
PIPE_NSW_CODE_OR_3 | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |