Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > ENABLE (GPU) Register

ENABLE (GPU) Register

ENABLE (GPU) Register Description

Register NameENABLE
Relative Address0x000000101C
Absolute Address 0x00FD4B101C (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnable Register

ENABLE (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2rwNormal read/write0x0Reserved, read as zero
Permit_cache_read_allocate 1rwNormal read/write0x0Writing a 1 to the relevant bit enables:
[1] Permit_cache_read_allocate
[0] Permit_cacheable_accesses
Permit_cacheable_accesses 0rwNormal read/write0x0Writing a 1 to the relevant bit enables:
[1] Permit_cache_read_allocate
[0] Permit_cacheable_accesses