Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_GPV Module > rpuM1_intlpd_ar_p (LPD_GPV) Register

rpuM1_intlpd_ar_p (LPD_GPV) Register

rpuM1_intlpd_ar_p (LPD_GPV) Register Description

Register NamerpuM1_intlpd_ar_p
Relative Address0x0000043124
Absolute Address 0x00FE143124 (LPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAR channel peak rate

rpuM1_intlpd_ar_p (LPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_p31:24rwNormal read/write0x0channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.