Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_ITOP_CXT0TO31_RAM0 (SMMU500) Register
Register Name | SMMU_ITOP_CXT0TO31_RAM0 |
---|---|
Relative Address | 0x0000002010 |
Absolute Address | 0x00FD802010 (SMMU_GPV) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | Enable the context performance interrupts. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
RAM_DATA | 31:0 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |