Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_QOS_CTRL Module > DDRC_MRR_DATA2 (DDR_QOS_CTRL) Register

DDRC_MRR_DATA2 (DDR_QOS_CTRL) Register

DDRC_MRR_DATA2 (DDR_QOS_CTRL) Register Description

Register NameDDRC_MRR_DATA2
Relative Address0x0000000524
Absolute Address 0x00FD090524 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDDRC MRR Register Data

DDRC_MRR_DATA2 (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0Reserved for future use
ECC 7:0roRead-only0x0DDRC MRR Register ECC Data