Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > MASK_DATA_1_MSW (GPIO) Register
Register Name | MASK_DATA_1_MSW |
---|---|
Relative Address | 0x000000000C |
Absolute Address | 0x00FF0A000C (GPIO) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Maskable Output Data (GPIO Bank1, MIO, Upper 10 bits) |
This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 10 bits of bank1, which corresponds to MIO[51:42].
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
MASK_1_MSW | 25:16 | woWrite-only | 0x0 | Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW] |
Reserved | 15:10 | razRead as zero | 0x0 | Not used, read back as zero |
DATA_1_MSW | 9:0 | rwNormal read/write | 0 | Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW] |