Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > DCTL (USB3_XHCI) Register

DCTL (USB3_XHCI) Register

DCTL (USB3_XHCI) Register Description

Register NameDCTL
Relative Address0x000000C704
Absolute Address 0x00FE20C704 (USB3_0_XHCI)
0x00FE30C704 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDevice Control Register
Note:
When Hibernation is not enabled using GCTL.GblHibernationEn field,
- you can write any value to CSS, CRS, L1HibernationEn, and KeepConnect fields
- L1HibernationEn, and KeepConnect fields always return 0 when read in this hibernation-disabled state

DCTL (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RUN_STOP31rwNormal read/write0Run/Stop
The software writes 1 to this bit to start the device controller operation.
To stop the device controller operation, the software must remove any active transfers and write 0 to this bit. When the controller is stopped, it sets the DSTS.DevCtrlHlt bit when the core is idle and the lower layer finishes the disconnect process.
The Run/Stop bit must be used in following cases as specified:
- After power-on reset and CSR initialization, the software must write 1 to this bit to start the device controller. The controller does not signal connect to the host until this bit is set.
- The software uses this bit to control the device controller to perform a soft disconnect. When the software writes 0 to this bit, the host does not see that the device is connected. The device controller stays in the disconnected state until the software writes 1 to this bit. The minimum duration of keeping this bit cleared is specified in the Note below. If the software attempts a connect after the soft disconnect or detects a disconnect event, it must set DCTL[8:5] to 5 before reasserting the Run/Stop bit.
- When the USB or Link is in a lower power state and the Two Power Rails configuration is selected, software writes 0 to this bit to indicate that it is going to turn off the Core Power Rail. After the software turns on the Core Power Rail again and re-initializes the device controller, it must set this bit to start the device controller.
Note: The following is the minimum duration under various conditions for which the soft disconnect (SftDiscon) bit must be set for the USB host to detect a device disconnect:
30ms:
- For SuperSpeed, when the device state is Suspended, Idle, Transmit, or Receive.
10ms:
- For high-speed, when the device state is Suspended, Idle, or not Idle/Suspended (performing transactions)
- For full-speed/low-speed, when the device state is Suspended, Idle, or not Idle/Supended (performing transactions)
To accommodate clock jitter, it is recommended that the application add extra delay to the specified minimum duration.
CSFTRST30rwNormal read/write0Core Soft Reset
Resets the all clock domains as follows:
- This bit clears the interrupts and all the CSRs except GSTS, GSNPSID, GGPIO, GUID, GUSB2PHYCFGn registers, GUSB3PIPECTLn registers, DCFG, DCTL, DEVTEN, and DSTS registers.
- All module state machines (except the SoC Bus Slave Unit) are reset to the IDLE state, and all the TxFIFOs and the RxFIFO are flushed.
- Any transactions on the SoC bus Master are terminated as soon as possible, after gracefully completing the last data phase of a SoC bus transfer. Any transactions on the USB are terminated immediately.
The application can write this bit at any time to reset the core. This is a self-clearing bit; the core clears this bit after all necessary logic is reset in the core, which may take several clocks depending on the cores current state. Once this bit is cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). Typically, software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain must be reset for proper operation.
Note: Programming this field with random data causes side effect. Bit Bash register testing is not recommended.
Reserved29roRead-only0x0Reserved1
HIRDTHRES28:24rwNormal read/write0HIRD Threshold (HIRD_Thres)
The core asserts output signals utmi_l1_suspend_n and utmi_sleep_n on the basis of this signal:
The core asserts utmi_l1_suspend_n to put the PHY into Deep Low-Power mode in L1 when both of the following are true:
- HIRD value is greater than or equal to the value in DCTL.HIRD_Thres[3:0]
- HIRD_Thres[4] is set to 1b1.
The core asserts utmi_sleep_n on L1 when one of the following is true:
- If the HIRD value is less than HIRD_Thres[3:0] or
- HIRD_Thres[4] is set to 1b0.
Note: This field must be set to 0 during SuperSpeed mode of operation.
LPM_NYET_thres23:20rwNormal read/write0LPM NYET Threshold
When LPM Errata is enabled:
Bits [23:20]: LPM NYET Response Threshold (LPM_NYET_thres)
Handshake response to LPM token specified by device application. Response depends on DCFG.LPMCap.
- DCFG.LPMCap is 1b0 - The core always responds with Timeout (that is, no response).
- DCFG.LPMCap is 1b1 - The core responds with an ACK on successful LPM transaction, which requires that all of the following are satisfied:
- There are no PID or CRC5 errors in both the EXT token and the LPM token (if not true, inactivity results in a timeout ERROR).
- No data is pending in the Transmit FIFO and OUT endpoints not in flow controlled state (else NYET).
- The BESL value in the LPM token is less than or equal to LPM_NYET_thres[3:0]
KeepConnect19rwNormal read/write0When 1, this bit enables the save and restore programming model by preventing the core from disconnecting from the host when DCTL.RunStop is set to 0.
It also enables the Hibernation Request Event to be generated when the link goes to U3 or L2.
The device core disconnects from the host when DCTL.RunStop is set to 0.
This bit indicates whether to preserve this behavior (0), or if the core must not disconnect when RunStop is set to 0 (1).
This bit also prevents the LTSSM from automatically going to U0/L0 when the host requests resume from U3/L2.
L1HibernationEn18rwNormal read/write0When this bit is set along with KeepConnect, the device core generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL.HIRD_Thres.
The core does not exit the LPM L1 state until software writes Recovery into the DCTL.ULStChngReq field.
This prevents corner cases where the device is entering hibernation at the same time the host is attempting to exit L1.
CRS17rwNormal read/write0Controller Restore State (CRS)
This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to 1, the controller immediately sets DSTS.RSS to 1. When the controller has finished the restore process, it sets DSTS.RSS to 0.
Note: When read, this field always returns 0.
CSS16rwNormal read/write0Controller Save State (CSS)
This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to 1, the controller immediately sets DSTS.SSS to 1. When the controller has finished the save process, it sets DSTS.SSS to 0.
Note: When read, this field always returns 0.
Reserved15:13roRead-only0x0Reserved
INITU2ENA12rwNormal read/write0Initiate U2 Enable
- 1b0: May not initiate U2 (default)
- 1b1: May initiate U2
On USB reset, hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U2_ENABLE), and clears this bit when ClearFeature(U2_ENABLE) is received.
If DCTL[11] (AcceptU2Ena) is 0, the link immediately exits U2 state.
ACCEPTU2ENA11rwNormal read/write0Accept U2 Enable
- 1b0: Reject U2 except when Force_LinkPM_Accept bit is set (default)
- 1b1: Core accepts transition to U2 state if nothing is pending on the application side.
On USB reset, hardware clears this bit to 0. Software sets this bit after receiving a SetConfiguration command.
INITU1ENA10rwNormal read/write0Initiate U1 Enable
- 1b0: May not initiate U1 (default);
- 1b1: May initiate U1.
On USB reset, hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U1_ENABLE), and clears this bit when ClearFeature(U1_ENABLE) is received.
If DCTL[9] (AcceptU1Ena) is 0, the link immediately exits U1 state.
ACCEPTU1ENA 9rwNormal read/write0Accept U1 Enable
- 1b0: Core rejects U1 except when Force_LinkPM_Accept bit is set (default)
- 1b1: Core accepts transition to U1 state if nothing is pending on the application side.
On USB reset, hardware clears this bit to 0. Software sets this bit after receiving a SetConfiguration command.
ULSTCHNGREQ 8:5woWrite-only0ULSTCHNGREQ
Software writes this field to issue a USB/Link state change request. A change in this field indicates a new request to the core.
If software wants to issue the same request back-to-back, it must write a 0 to this field between the two requests. The result of the state change request is reflected in the USB/Link State in DSTS. These bits are self-cleared on the MAC Layer exiting suspended state.
If software is updating other fields of the DCTL register and not intending to force any link state change, then it must write a 0 to this field.
SS Compliance mode is normally entered and controlled by the remote link partner. Refer to the USB 3.0 specification.
Alternatively, you can force the local link directly into compliance mode, by resetting the SS link with the RUN/STOP bit set to zero.
If you then write 10 to the USB/Link State Change field and 1 to RUN/STOP, the link goes to compliance mode.
Once you are in compliance, you may alternately write zero and 10 to this field to advance the compliance pattern.
In SS mode:
- Value Requested Link State Transition/Action
- 0
No Action
- 4
SS.Disabled
- 5
Rx.Detect
- 6
SS.Inactive
- 8
Recovery
- 10
Compliance
- Others:
Reserved
In HS/FS/LS mode:
- ValueRequested USB state transition
- 8
Remote wakeup request
- Others: Reserved
The Remote wakeup request must be issued 2us after the device goes into suspend state (DSTS[21:18] is 3.
Note: After coming out of hibernation, software must write 8 (Recovery) into this field to confirm exit from the suspended state.
TSTCTL 4:1rwNormal read/write0Test Control
- 4b000: Test mode disabled
- 4b001: Test_J mode
- 4b010: Test_K mode
- 4b011: Test_SE0_NAK mode
- 4b100: Test_Packet mode
- 4b101: Test_Force_Enable
- Others: Reserved
Reserved 0roRead-only0x0Reserved