Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TM_PLL_DIG21 (SERDES) Register

L3_TM_PLL_DIG21 (SERDES) Register

L3_TM_PLL_DIG21 (SERDES) Register Description

Register NameL3_TM_PLL_DIG21
Relative Address0x000000E054
Absolute Address 0x00FD40E054 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000020
DescriptionRegister value is generated by Vivado PCW.

L3_TM_PLL_DIG21 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_PLL_DIG21_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
tm_force_en_pll_ldo_0p9_ref 7rwNormal read/write0x0Value generated by PCW.
ana_tm_en_pll_0p9_force_sw 6rwNormal read/write0x0Value generated by PCW.
tm_pll_pd_opdiv_sym 5rwNormal read/write0x1Value generated by PCW.
tm_force_pll_pd_opdiv_sym 4rwNormal read/write0x0Value generated by PCW.
tm_pll_rsvd_1 3roRead-only0x0Value generated by PCW.
tm_pll_rsvd_2 2roRead-only0x0Value generated by PCW.
tm_pll_en 1rwNormal read/write0x0Value generated by PCW.
tm_force_pll_en 0rwNormal read/write0x0Value generated by PCW.