Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > control_n_integ_en_c_n (PL390) Register

control_n_integ_en_c_n (PL390) Register

control_n_integ_en_c_n (PL390) Register Description

Register Namecontrol_n_integ_en_c_n
Relative Address0x0000001040
Absolute Address 0x00F9001040 (RCPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnables the integration test logic to modify the status of the
nfiq_c<n> and nirq_c<n> signals.

control_n_integ_en_c_n (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
integ_en 0rwNormal read/write0Enables the integration test logic.