Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > BANK3_STATUS (CRL_APB) Register
Register Name | BANK3_STATUS |
---|---|
Relative Address | 0x0000000288 |
Absolute Address | 0x00FF5E0288 (CRL_APB) |
Width | 10 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Voltage mode status for DIO bank 3 |
Voltage Status: 0 = 2.5/3.3v mode. 1 = 1.8v mode. Note: Each bit applies to a single I/O pin.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
vmode_1p8_3p3_n | 9:0 | roRead-only | 0 | Bit[9]: TCK Bit[8]: TDI Bit[7]: TMS Bit[6]: TDO Bit[5]: SRST Bit[4]: PROG Bit[3]: INIT Bit[2]: DONE Bit[1]: ERROR_OUT Bit[0]: ERROR_STS |