Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > GQSPI_LPBK_DLY_ADJ (QSPI) Register

GQSPI_LPBK_DLY_ADJ (QSPI) Register

GQSPI_LPBK_DLY_ADJ (QSPI) Register Description

Register NameGQSPI_LPBK_DLY_ADJ
Relative Address0x0000000138
Absolute Address 0x00FF0F0138 (QSPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000033
DescriptionGQSPI Loopback clock delay adjustment Register

Register for adjusting the internal loopback clock delay for read data capturing. This feature is only active if bit 5 is set AND if the baud rate divisor is programmed to 2 (i.e., 000).

GQSPI_LPBK_DLY_ADJ (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:6razRead as zero0x0reserved
USE_LPBK 5rwNormal read/write0x1Use internal loopback master clock for read data capturing when baud rate divisor is 2.
Note: Change this value only when controller is not communicating with the memory device.
DLY1 4:3rwNormal read/write0x2Must be set to 00 if Loopback clk used.
Note: Change this value only when controller is not communicating with the memory device.
DLY0 2:0rwNormal read/write0x3Must be set to 00 if Loopback clk used.
Note: Change this value only when controller is not communicating with the memory device.