Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_SIDR2 (SMMU500) Register

SMMU_SIDR2 (SMMU500) Register

SMMU_SIDR2 (SMMU500) Register Description

Register NameSMMU_SIDR2
Relative Address0x0000000028
Absolute Address 0x00FD800028 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00005555
DescriptionProvides SMMU capability information.

SMMU_SIDR2 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PTFSV8_64Kb14roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PTFSV8_16Kb13roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TFSV8_4Kb12roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
UBS11:8roRead-only0x5Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
OAS 7:4roRead-only0x5Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IAS 3:0roRead-only0x5Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details