Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_WB0_MRT_ENABLE (GPU) Register
Register Name | PP0_WB0_MRT_ENABLE |
---|---|
Relative Address | 0x000000811C |
Absolute Address | 0x00FD4B811C (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | WB0 MRT Enable Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:4 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
WB0_MRT_ENABLE | 3:0 | rwNormal read/write | 0x0 | 0 MRT 0 enabled 1 MRT 1 enabled 2 MRT 2 enabled 3 MRT 3 enabled |