Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM1_RESULT0 (VCU_SLCR) Register

APM1_RESULT0 (VCU_SLCR) Register

APM1_RESULT0 (VCU_SLCR) Register Description

Register NameAPM1_RESULT0
Relative Address0x000000020C
Absolute Address 0x00A004020C (VCU_SLCR)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAPM1_RESULT0

APM1_RESULT0 (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
wr_transac_count31:0roRead-only0x0Number of write transactions happened in configured timing window.