Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_capabilities (SDIO) Register

reg_capabilities (SDIO) Register

reg_capabilities (SDIO) Register Description

Register Namereg_capabilities
Relative Address0x0000000040
Absolute Address 0x00FF160040 (SD0)
0x00FF170040 (SD1)
Width64
TyperoRead-only
Reset Value0x280737EC6481
DescriptionHost controller implementation.

This register provides the host driver with information specific to the host controller implementation

reg_capabilities (SDIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
corecfg_spiblkmode57roRead-only0x0SPI Block Mode is not supported.
corecfg_spisupport56roRead-only0x0SPI Mode is not supported.
corecfg_clockmultiplier55:48roRead-only0x0Clock multiplier is not supported.
corecfg_retuningmodes47:46roRead-only0x0This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver.
00: Mode 1
01: Mode 2
10: Mode 3
11: reserved.
There are two re-tuning timings:Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue.
corecfg_tuningforsdr5045roRead-only0x1SDR50 requires tuning.
corecfg_retuningtimercnt43:40roRead-only0x8This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3.
0h: Get information via other source
1h: 1 seconds
2h: 2 seconds
3h: 4 seconds
4h: 8 seconds
------
nh: 2 (n-1) seconds
------
Bh:
1024 seconds
Others: reserved
corecfg_ddriversupport38roRead-only0x0Driver Type D (1.8 Signaling) is not supported.
corecfg_cdriversupport37roRead-only0x0Driver Type C (1.8 Signaling) is not supported.
corecfg_adriversupport36roRead-only0x0Driver Type A (for 1.8 Signaling) is not supported.
corecfg_ddr50support34roRead-only0x1DDR50 is supported.
corecfg_sdr104support33roRead-only0x1SDR104 is supported (requires tuning).
corecfg_sdr50support32roRead-only0x1SDR50 is supported; bit 45 indicates SDR50 requires tuning.
corecfg_slottype31:30roRead-only0x0This field indicates usage of a slot by a specific Host System. (A host controller register set is defined perslot.) Embedded slot for one device (01b) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (10b) can be set if Host Controller supports Shared Bus Control register. The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (10b), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System.
00 Removable Card Slot
01 Embedded Slot for One Device
10 Shared Bus Slot
11 Reserved
corecfg_asynchintrsupport29roRead-only0x1Asynchronous Interrupt is supported; refer to SDIO Specification Version 3.00.
corecfg_64bitsupport28roRead-only0x1Host controller supports 64-bit system address.
corecfg_1p8voltsupport26roRead-only0x1Host controller supports 1.8V I/O.
corecfg_3p0voltsupport25roRead-only0x1Host controller supports 3.0V I/O.
corecfg_3p3voltsupport24roRead-only0x1Host controller supports 3.3V I/O.
corecfg_suspressupport23roRead-only0x1Host controller supports Suspend / Resume functionality.
corecfg_sdmasupport22roRead-only0x1SMDA is supported; transfers data between system memory and the host controller.
corecfg_highspeedsupport21roRead-only0x1This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).
0 High Speed Not Supported
1 High Speed Supported
corecfg_adma2support19roRead-only0x1ADMA2 is supported
corecfg_8bitsupport18roRead-only0x1This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case, refer to Bus Width Preset in the Shared Bus resister.
0 Extended Media Bus Not Supported
1 Extended Media Bus Supported
corecfg_maxblklength17:16roRead-only0x0This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.
00 512byte
01 1024byte
10 2048byte
11 4096byte
corecfg_baseclkfreq15:8roRead-only0x64(1)6-bit Base Clock Frequency:
This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz.
11xx xxxxb Not Supported
0011 1111b 63MHz
0000 0010b 2MHz
0000 0001b 1MHz
0000 0000bGet Information via another method
(2)8-bit Base Clock Frequency:
This mode is supported by the Host Controller Version 3.00.Unit values are 1MHz. The supported clock range is 10MHz to 255MHz.
FFh 255MHz
02h 2MHz
01h 1MHz
00h Get Information via another method.
If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to the SDCLK Frequency Select in the Clock Control register.) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method.
corecfg_timeoutclkunit 7roRead-only0x1Base clock frequency to detect Data Timeout Error is measured in MHz.
corecfg_timeoutclkfreq 5:0roRead-only0x1Base clock frequency to detect the Data Timeout Error is 1 to 63 MHz