Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DTCR1 (DDR_PHY) Register

DTCR1 (DDR_PHY) Register

DTCR1 (DDR_PHY) Register Description

Register NameDTCR1
Relative Address0x0000000204
Absolute Address 0x00FD080204 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00030237
DescriptionData Training Configuration Register 1

DTCR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RANKEN_RSVD31:18roRead-only0x0Reserved. Return zeros on reads.
RANKEN17:16rwNormal read/write0x3Rank Enable: Specifies the ranks that are enabled for data-training
and write leveling. Bit 0 controls rank 0, bit 1 controls rank 1, etc.
Setting the bit to 1b1 enables the rank, and setting it to 1b0 disables
the rank. This setting also specifies the ranks that are enabled for
DQS drift detection and compensation.
Reserved15:14roRead-only0x0Reserved. Return zeros on reads.
DTRANK13:12rwNormal read/write0x0Data Training Rank: Selects the SDRAM rank to be used during data
bit deskew.
Reserved11roRead-only0x0Reserved. Return zeros on reads.
RDLVLGDIFF10:8rwNormal read/write0x2Read Leveling Gate Sampling Difference: width of DQS sampling
window. Encoded as a fraction of the DDR clock period follows:
0b000: GDQSPRD/4
0b001: GDQSPRD/4
0b010: GDQSPRD/8
0b011: GDQSPRD/16
0b100: GDQSPRD/32
0b101: GDQSPRD/64
0b110: GDQSPRD/128
0b111: GDQSPRD/256
Reserved 7roRead-only0x0Reserved. Return zeros on reads.
RDLVLGS 6:4rwNormal read/write0x3Read Leveling Gate Shift: delay reduction to apply to gate after it has
been aligned to DQS. Encoded as a fraction of the DDR clock period
follows:
0b000: 0
0b001: GDQSPRD/4
0b010: GDQSPRD/8
0b011: GDQSPRD/16
0b100: GDQSPRD/32
0b101: GDQSPRD/64
0b110: GDQSPRD/128
0b111: GDQSPRD/256
Reserved 3roRead-only0x0Reserved. Return zeros on reads.
RDPRMVL_TRN 2rwNormal read/write0x1Read Preamble Training enable: engages read preamble training
mode in DDR4 DRAM during gate training
RDLVLEN 1rwNormal read/write0x1Read Leveling Enable: Run a DQS sampling scheme using the gate
to align the rising edges of DQS and the gate after which a delay
reduction is applied to the gate (see RDLVLGS).
Note: This bit should not be enabled when the gate is extended
BSTEN 0rwNormal read/write0x1Basic Gate Training Enable: Runs a trial and error algorithm to
progressively evaluate gate positions and narrow down to a working
one