Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > DLL_REF_CTRL (CRL_APB) Register

DLL_REF_CTRL (CRL_APB) Register

DLL_REF_CTRL (CRL_APB) Register Description

Register NameDLL_REF_CTRL
Relative Address0x0000000104
Absolute Address 0x00FF5E0104 (CRL_APB)
Width 8
TyperwNormal read/write
Reset Value0x00000000
DescriptionClock Generator Control.

DLL_REF_CTRL (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved 7:3rwNormal read/write0x0reserved
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: IOPLL
001: RPLL