Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > HCSPARAMS1 (USB3_XHCI) Register

HCSPARAMS1 (USB3_XHCI) Register

HCSPARAMS1 (USB3_XHCI) Register Description

Register NameHCSPARAMS1
Relative Address0x0000000004
Absolute Address 0x00FE200004 (USB3_0_XHCI)
0x00FE300004 (USB3_1_XHCI)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionStructural Parameters 1 Register
For register definitions, refer to the xHCI specification.

HCSPARAMS1 (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MAXPORTS31:24roRead-only0Number of Ports (MaxPorts)
- Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS)
- Number of ports enabled is controlled by the core input signals host_num_u2_port[3:0]+host_num_u3_port[3:0]
Note:
In USB 2.0-only mode, the host_num_u3_port signal is zero.
Reserved23:19roRead-only0x0Reserved
MAXINTRS18:8roRead-only0Number of Interrupters (MaxIntrs)
Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT
MAXSLOTS 7:0roRead-only0Number of device slots (MaxSlots)
Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT