Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > SD_OTAPDLYSEL (IOU_SLCR) Register

SD_OTAPDLYSEL (IOU_SLCR) Register

SD_OTAPDLYSEL (IOU_SLCR) Register Description

Register NameSD_OTAPDLYSEL
Relative Address0x0000000318
Absolute Address 0x00FF180318 (IOU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionOutput Tap Delay Select

SD_OTAPDLYSEL (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:23razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD1_OTAPDLYENA22rwNormal read/write0x0Reserved. Leave this bit set = 0.
SD1_OTAPDLYSEL21:16rwNormal read/write0x0Selects optimal number of taps on the SD_CLK. This is
effective only when corectrl_otapdlyena is asserted. For the SD frequency od -
200 MHz: 8 taps are available
100 MHz: 15 taps are available
50 MHz: 30 taps are available
33 MHz: 45 taps are available
Reserved15:7razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD0_OTAPDLYENA 6rwNormal read/write0x0Reserved. Leave this bit set = 0.
SD0_OTAPDLYSEL 5:0rwNormal read/write0x0Selects optimal number of taps on the SD_CLK. This is effective only when [SD_OTAPDLYENA] is asserted. For the SD frequency od -
200 MHz: 8 taps are available
100 MHz: 15 taps are available
50 MHz: 30 taps are available
33 MHz: 45 taps are available