Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_TBUQOS0 (SMMU500) Register

SMMU_TBUQOS0 (SMMU500) Register

SMMU_TBUQOS0 (SMMU500) Register Description

Register NameSMMU_TBUQOS0
Relative Address0x0000002100
Absolute Address 0x00FD802100 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSpecify the QoS for TBUs,when the TBUn is in the range of 0-7.

SMMU_TBUQOS0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
QOSTBU523:20rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
QOSTBU419:16rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
QOSTBU315:12rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
QOSTBU211:8rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
QOSTBU1 7:4rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
QOSTBU0 3:0rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details