Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM0_RESULT18 (VCU_SLCR) Register

APM0_RESULT18 (VCU_SLCR) Register

APM0_RESULT18 (VCU_SLCR) Register Description

Register NameAPM0_RESULT18
Relative Address0x0000000154
Absolute Address 0x00A0040154 (VCU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAPM0_RESULT18

APM0_RESULT18 (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
validity_check31roRead-only0x0This signal will toggle in alternate timing window. This is required for safe reading of accumulated read and write latencies parameters which requires more then one APM access. This bit field is read with all the latency related APB registers and this is expected to be same for all those registers.
Reserved30:16razRead as zero0x0reserved
count_rd_lat115:0roRead-only0x015 LSBs of number of latencies added to get 'accum_rd_lat1