Zynq UltraScale+ Devices Register Reference > Module Summary > AFIFM Module
Module Name | AFIFM Module |
---|---|
Modules of this Type | AFIFM0, AFIFM1, AFIFM2, AFIFM3, AFIFM4, AFIFM5, AFIFM6 |
Base Address | 0x00FD360000 (AFIFM0) 0x00FD370000 (AFIFM1) 0x00FD380000 (AFIFM2) 0x00FD390000 (AFIFM3) 0x00FD3A0000 (AFIFM4) 0x00FD3B0000 (AFIFM5) 0x00FF9B0000 (AFIFM6) |
Description | PL-PS AXI Channel Configuration, QoS and FIFO Configuration; S_AXI_HPC0_FPD |
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
RDCTRL | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x000003B0 | Read Channel Control Register |
RDISSUE | 0x0000000004 | 32 | mixedMixed types. See bit-field details. | 0x00000007 | Read Issuing Capability Register |
RDQoS | 0x0000000008 | 32 | mixedMixed types. See bit-field details. | 0x00000007 | QoS Read Channel Register |
RDDEBUG | 0x0000000010 | 32 | mixedMixed types. See bit-field details. | 0x40000000 | Read Channel Debug Register |
WRCTRL | 0x0000000014 | 32 | mixedMixed types. See bit-field details. | 0x000003B0 | Write Channel Control Register |
WRISSUE | 0x0000000018 | 32 | mixedMixed types. See bit-field details. | 0x00000007 | Write Issuing Capability Register |
WRQoS | 0x000000001C | 32 | mixedMixed types. See bit-field details. | 0x00000007 | QoS Write Channel Register |
I_STS | 0x0000000E00 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register |
I_EN | 0x0000000E04 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable |
I_DIS | 0x0000000E08 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable |
I_MASK | 0x0000000E0C | 32 | mixedMixed types. See bit-field details. | 0x00000001 | Interrupt Mask |
CONTROL | 0x0000000F04 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | General Control Register |
SAFETY_CHK | 0x0000000F0C | 32 | rwNormal read/write | 0x00000000 | Safety endpoint connectivity check Register |