Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > TX_PROT_BUS_WIDTH (SERDES) Register

TX_PROT_BUS_WIDTH (SERDES) Register

TX_PROT_BUS_WIDTH (SERDES) Register Description

Register NameTX_PROT_BUS_WIDTH
Relative Address0x0000010040
Absolute Address 0x00FD410040 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000055
DescriptionRegister value is generated by Vivado PCW.

TX_PROT_BUS_WIDTH (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TX_PROT_BUS_WIDTH_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
L3_TX_Prot_BusWidth 7:6rwNormal read/write0x1Value generated by PCW.
L2_TX_Prot_BusWidth 5:4rwNormal read/write0x1Value generated by PCW.
L1_TX_Prot_BusWidth 3:2rwNormal read/write0x1Value generated by PCW.
L0_TX_Prot_BusWidth 1:0rwNormal read/write0x1Value generated by PCW.