Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_BOUNDING_BOX_LEFT_RIGHT (GPU) Register
Register Name | PP0_BOUNDING_BOX_LEFT_RIGHT |
---|---|
Relative Address | 0x0000008028 |
Absolute Address | 0x00FD4B8028 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Bounding Box Left Right Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:20 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
BOUNDING_BOX_LEFT | 19:16 | rwNormal read/write | 0x0 | Bits [3:0] of the number of pixels from the left initial framebuffer edge to exclude from write-back, if the bounding box is honored. Bits [13:4] are always 0. If a greater bounding box than 16 is required, the modulo 16 of the bounding box is placed in this register. The remaining part is subtracted from all vertices. |
Reserved | 15:14 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
BOUNDING_BOX_RIGHT | 13:0 | rwNormal read/write | 0x0 | The number of pixels from the left initial framebuffer edge - 1 to include in write-back if the bounding box is honored. |