Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_PLIST_CONFIG (GPU) Register

PP1_PLIST_CONFIG (GPU) Register

PP1_PLIST_CONFIG (GPU) Register Description

Register NamePP1_PLIST_CONFIG
Relative Address0x000000A050
Absolute Address 0x00FD4BA050 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPolygon List Format Register

PP1_PLIST_CONFIG (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30rwNormal read/write0x0Reserved, write as zero, read undefined.
LIST_FORMAT29:28rwNormal read/write0x0The polygon list format is as follows:
0: Legacy format, 1x1 tile coverage = default
1: 2x2 supertiling
2: 4x4 supertiling
3: undefined
Reserved27:22rwNormal read/write0x0Reserved, write as zero, read undefined.
SCALE_Y21:16rwNormal read/write0x0Log2 of the number of tiles in the y direction for a supertile.
Reserved15:6rwNormal read/write0x0Reserved, write as zero, read undefined.
SCALE_X 5:0rwNormal read/write0x0Log2 of the number of tiles in the x direction for a supertile.