Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > ERR_CTRL (CRL_APB) Register

ERR_CTRL (CRL_APB) Register

ERR_CTRL (CRL_APB) Register Description

Register NameERR_CTRL
Relative Address0x0000000000
Absolute Address 0x00FF5E0000 (CRL_APB)
Width 1
TyperwNormal read/write
Reset Value0x00000000
DescriptionSLVERR Error Signal Enable.

ERR_CTRL (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
slverr_enable 0rwNormal read/write0x0Accesses to an unimplemented register
asserts the SLVERR error signal on the APB bus interface and generates an interrupt.
0: disable.
1: enable.
Regardless of the setting of the [slverr_enable] bit setting:
* The [addr_decode_err] interrupt bit is set in the interrupt status register.
* APB writes are ignored and reads returns 0.