Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_NSACR (SMMU500) Register

SMMU_NSACR (SMMU500) Register

SMMU_NSACR (SMMU500) Register Description

Register NameSMMU_NSACR
Relative Address0x0000000410
Absolute Address 0x00FD800410 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x0400001C
DescriptionProvides IMPLEMENTATION DEFINED functionality.

SMMU_NSACR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CACHE_LOCK26rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
DP4K_TBUDISB25rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
DP4K_TCUDISB24rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S2CRB_TLBEN10rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MMUDISB_TLBEN 9rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMTNMB_TLBEN 8rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IPA2PA_CEN 4rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S2WC2EN 3rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S1WC2EN 2rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details