Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank2_ctrl3 (IOU_SLCR) Register

bank2_ctrl3 (IOU_SLCR) Register

bank2_ctrl3 (IOU_SLCR) Register Description

Register Namebank2_ctrl3
Relative Address0x0000000178
Absolute Address 0x00FF180178 (IOU_SLCR)
Width26
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Bank 2, CMOS input type control.

bank2_ctrl3 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
schmitt_cmos_n25:0rwNormal read/write0x0Select between Schmitt Trigger or CMOS input for MIO pins [52:77].
0 = CMOS.
1 = Schmitt (hysteresis).
Bit [0] controls MIO pin 52.
..
Bit [25] controls MIO pin 77.
Bits [26] to [31] are reserved.