Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_0 (PCIE_ATTRIB) Register
Register Name | ATTR_0 |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FD480000 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000003 |
Description | ATTR_0 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_aer_cap_ecrc_gen_capable | 1 | rwNormal read/write | 0x1 | Indicates that the core is capable of generating ECRC. Value transferred to bit 5 of the AER Capabilities and Control Register. |
attr_aer_cap_ecrc_check_capable | 0 | rwNormal read/write | 0x1 | Indicates that the core is capable of checking ECRC. Value transferred to bit 7 of the AER Capabilities and Control Register. |