Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ERROR_EN_1 (PMU_GLOBAL) Register
Register Name | ERROR_EN_1 |
---|---|
Relative Address | 0x00000005A0 |
Absolute Address | 0x00FFD805A0 (PMU_GLOBAL) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | System Error Enables, Reg 1. |
Individual errors can be: 0: blocked. 1: propagated. If an error is blocked, it is blocked before the ERROR_STATUS_{1, 2} read registers and does not propogate to the error interrupt logic: ERROR_INT*, ERROR_POR*, ERROR_SRST*, or ERROR_SIG* registers. For details on the bit fields, refer to the ERROR_STATUS_1 register description.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31 | rwNormal read/write | 0x0 | reserved. |
Reserved | 30 | rwNormal read/write | 0x0 | reserved. |
Reserved | 29 | rwNormal read/write | 0x0 | reserved. |
Reserved | 28 | rwNormal read/write | 0x0 | reserved. |
CSU_SWDT | 27 | rwNormal read/write | 0x0 | CSU_SWDT timeout. |
CLK_MON | 26 | rwNormal read/write | 0x0 | Clock Monitor (ClkMon). |
XMPU | 25:24 | rwNormal read/write | 0x0 | XMPU and XPPU error signals. |
PWR_SUPPLY | 23:16 | rwNormal read/write | 0x0 | Eight (8) PS VCC and VCCO power supplies. |
Reserved | 15:14 | rwNormal read/write | 0x0 | reserved |
FPD_SWDT | 13 | rwNormal read/write | 0x0 | FPD_SWDT timeout. |
LPD_SWDT | 12 | rwNormal read/write | 0x0 | LPD_SWDT timeout. |
Reserved | 11:10 | rwNormal read/write | 0x0 | reserved |
RPU_CCF | 9 | rwNormal read/write | 0x0 | RPU common cause failures. |
Reserved | 8 | rwNormal read/write | 0x0 | reserved |
RPU_LS | 7:6 | rwNormal read/write | 0x0 | RPU lockstep error. |
FPD_TEMP | 5 | rwNormal read/write | 0x0 | FPD over tempurature alarm. |
LPD_TEMP | 4 | rwNormal read/write | 0x0 | LPD over tempurature alarm. |
RPU1 | 3 | rwNormal read/write | 0x0 | RPU1 RAM (all ECC errors). |
RPU0 | 2 | rwNormal read/write | 0x0 | RPU0 RAM (all ECC errors). |
OCM_ECC | 1 | rwNormal read/write | 0x0 | OCM (uncorrectable only). |
DDR_ECC | 0 | rwNormal read/write | 0x0 | DDR (uncorrectable only). |