Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > USBCMD (USB3_XHCI) Register
Register Name | USBCMD |
---|---|
Relative Address | 0x0000000020 |
Absolute Address |
0x00FE200020 (USB3_0_XHCI) 0x00FE300020 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:14 | roRead-only | 0x0 | Reserved |
CME | 13 | rwNormal read/write | 0 | CEM Enable For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
Reserved | 12 | roRead-only | 0 | Reserved |
EU3S | 11 | rwNormal read/write | 0 | EU3S For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
EWE | 10 | rwNormal read/write | 0 | EWE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
CRS | 9 | rwNormal read/write | 0 | Controller Restore State This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to 1, the controller immediately sets DSTS.RSS to 1. When the controller has finished the restore process, it sets DSTS.RSS to 0. Note: When read, this field always returns 0. |
CSS | 8 | rwNormal read/write | 0 | Controller Save State This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to 1, the controller immediately sets DSTS.SSS to 1. When the controller has finished the save process, it sets DSTS.SSS to 0. Note: When read, this field always returns 0. |
LHCRST | 7 | rwNormal read/write | 0 | Light Host Controller Reset For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. The following bits reset the internal logic of the host controller. Under soft reset, some CSR accesses may fail (Timeout). - HCRST - LHCRST Bit Bash register testing is not recommended. |
Reserved | 6:4 | roRead-only | 0x0 | Reserved |
HSEE | 3 | rwNormal read/write | 0 | HSEE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
INTE | 2 | rwNormal read/write | 0 | INTE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
HCRST | 1 | rwNormal read/write | 0 | HCRST The following bits reset the internal logic of the host controller. Under soft reset, some CSR accesses may fail (Timeout). - HCRST - LHCRST Bit Bash register testing is not recommended. |
R_S | 0 | rwNormal read/write | 0 | R_S For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Due to side-effects this reguster field is not recommended for Bit-Bash testing. |