Zynq UltraScale+ Devices Register Reference > Module Summary > A53_DBG_2 Module > EDRCR (A53_DBG_2) Register

EDRCR (A53_DBG_2) Register

EDRCR (A53_DBG_2) Register Description

Register NameEDRCR
Relative Address0x0000000090
Absolute Address 0x00FEE10090 (CORESIGHT_A53_DBG_2)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionExternal Debug Reserve Control Register

EDRCR (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CBRRQ 4woWrite-only0x0Allow imprecise entry to Debug state. The actions on writing to this bit are:Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1.This feature is optional. If this feature is not implemented, writes to this bit are ignored.
CSPA 3woWrite-only0x0Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:
CSE 2woWrite-only0x0Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: