Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > REQ_SWRST_INT_MASK (PMU_GLOBAL) Register
Register Name | REQ_SWRST_INT_MASK |
---|---|
Relative Address | 0x0000000414 |
Absolute Address | 0x00FFD80414 (PMU_GLOBAL) |
Width | 32 |
Type | roRead-only |
Reset Value | 0xFBF717DF |
Description | Reset Request; Interrupt Mask. Check the REQ_SWRST_STATUS register bits for more information. |
0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PL | 31 | roRead-only | 0x1 | Programmable Logic, PL reset request. |
FP | 30 | roRead-only | 0x1 | Full Power Domain, FPD reset request. |
LP | 29 | roRead-only | 0x1 | Low Power Domain, LPD reset request. |
PS_ONLY | 28 | roRead-only | 0x1 | PS-only reset request. |
IOU | 27 | roRead-only | 0x1 | IOP reset request. |
Reserved | 26 | roRead-only | 0x0 | reserved |
USB1 | 25 | roRead-only | 0x1 | USB controller 1 reset request. |
USB0 | 24 | roRead-only | 0x1 | USB controller 0 reset request. |
GEM3 | 23 | roRead-only | 0x1 | GEM3 reset request. |
GEM2 | 22 | roRead-only | 0x1 | GEM2 reset request. |
GEM1 | 21 | roRead-only | 0x1 | GEM1 reset request. |
GEM0 | 20 | roRead-only | 0x1 | GEM0 reset request. |
Reserved | 19 | roRead-only | 0x0 | reserved |
LS_R5 | 18 | roRead-only | 0x1 | RPU Lockstep reset request. |
R5_1 | 17 | roRead-only | 0x1 | RPU core 1 reset request. |
R5_0 | 16 | roRead-only | 0x1 | RPU core 0 reset request. |
Reserved | 15:13 | roRead-only | 0x0 | reserved |
Display_Port | 12 | roRead-only | 0x1 | Display Port. |
Reserved | 11 | roRead-only | 0x0 | reserved |
SATA | 10 | roRead-only | 0x1 | SATA reset request. |
PCIe | 9 | roRead-only | 0x1 | PCIe reset request. |
GPU | 8 | roRead-only | 0x1 | Both GPU Pixel Processors reset request. |
PP1 | 7 | roRead-only | 0x1 | GPU Pixel Processor 1 reset request. |
PP0 | 6 | roRead-only | 0x1 | GPU Pixel Processor 0 reset request. |
Reserved | 5 | roRead-only | 0x0 | reserved |
APU | 4 | roRead-only | 0x1 | APU MPCore reset request |
ACPU3 | 3 | roRead-only | 0x1 | APU3 processor reset request. |
ACPU2 | 2 | roRead-only | 0x1 | APU2 processor reset request. |
ACPU1 | 1 | roRead-only | 0x1 | APU1 processor reset request. |
ACPU0 | 0 | roRead-only | 0x1 | APU0 processor reset request. |