Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_VENDOR Module > PPCFG (SATA_AHCI_VENDOR) Register

PPCFG (SATA_AHCI_VENDOR) Register

PPCFG (SATA_AHCI_VENDOR) Register Description

Register NamePPCFG
Relative Address0x0000000008
Absolute Address 0x00FD0C00A8 (SATA_AHCI_VENDOR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0xA001FFFE
DescriptionPhy Control Layer 1 configuration for port 0 or 1.

Port Phy1Cfg. Controls the configuration of the Phy Control Layer 1 register for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.

PPCFG (SATA_AHCI_VENDOR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ESDF31rwNormal read/write0x1ESDF: Enable signal det filter, if set the a single de-assertion of signal detect or the coreRxDataValid when the Phy Init state machine is in the PhyReady state will cause the state machine to exit the PhyReady state and return to a PhyNotReady state,
this will result in the OOB and speed negotiation running again.
ERSN30rwNormal read/write0x0Enable reset speed negotiation (ERSN): If enabled then the Phy control layer will enable only a single speed on the Rx path during speed negotiation.
This speed is determined as the fastest support for the first round falling to the lowest speed for the final round. Each round of speed negotiation is terminated by the host issuing a COMRESET and rerunning OOB before beginning the next round of speed negotiation as detailed in RSN Reset Speed Negotiation
PSS29rwNormal read/write0x1PSS: PhyControl select SERDES Slumber CMU during Link Slumber.
When the controller enters slumber if this bit is set an extra control signal is applied to the Serdes to slumber the Clock block within the Serdes.
This will yield extra power savings but is Serdes specific.
PSSO28rwNormal read/write0x0PSSO: PhyControl select SERDES OOB or internally decoded OOB signaling as inputs.
0: INT_OOB.
1: SER_OOB.
STB27roRead-only0x0STB: Status Bit. Reading this bit will show that status of the Gen Fixed clocks parameter.
This bit indicates if the Phy Control layer is running from a fixed frequency clock or a variable clock derived from the tx clock of the SERDES.
PBPNA26rwNormal read/write0x0PBPNA: PhyControl BIST Pattern no Aligns. Setting this bit will cause the Phy Ctrl Pattern generator to transmit each pattern continuously.
PBCE25rwNormal read/write0x0PBCE: PhyControl BIST Clear Error. Setting this bit to 1 clears the pattern match error bit. When a pattern mismatch occurs this bit needs to be set then negated to clear the error.
PBPE24rwNormal read/write0x0PBPE: PhyControl BIST Pattern Enable. Setting this bit to 1 enables the Phy Control Test Pattern generation.
PBPS23:21rwNormal read/write0x0PBPS: PhyControl BIST Pattern Select
0: LBP.
1: LFTP.
2: MFTP.
3: HFTP.
4: PRBS.
5: BIST.
FPR20rwNormal read/write0x0FPR: Force PHY Ready signal level.
0: Normal.
1: frcPhyRdy.
Reserved19roRead-only0x0Reserved
SNR18rwNormal read/write0x0SNR: Speed Negotiation Rate, when set to 1 the speed negotiation is run only at the rate programmed in the SPD field of the SControl register.
SNM17rwNormal read/write0x0SNM: Speed Negotiation Method, when set to 1 the speed negotiation is run starting at gen1 speed up to fastest supported speed, when cleared to o the speed negotiation is run starting at the fastest supported speed down to gen1 speed.
TTA16:0rwNormal read/write0x1FFFETTA: This value determines the time period the Controller transmits and waits for ALIGNp during speed negotiation. This value is derived for the PM_CLK period.