Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > MASK_DATA_0_LSW (GPIO) Register
Register Name | MASK_DATA_0_LSW |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FF0A0000 (GPIO) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) |
This register enables software to change the value being output on up to 16bits at one time selectively. Only data values with a corresponding deasserted mask bit will be changed. Output data values are unchanged and hold their previous value for bits which are masked. This register avoids the need for a read-modify-write sequence for unchanged bits. NOTE: This register does not affect the enabling of the output driver. See the DIRM_0 and OEN_0 registers. This register controls the output values for the lower 16bits of bank0, which corresponds to MIO[15:0].
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
MASK_0_LSW | 31:16 | woWrite-only | 0x0 | On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0s. |
DATA_0_LSW | 15:0 | rwNormal read/write | 0 | On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. |