Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > CONFIG (USB3_XHCI) Register
Register Name | CONFIG |
---|---|
Relative Address | 0x0000000058 |
Absolute Address |
0x00FE200058 (USB3_0_XHCI) 0x00FE300058 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Configure Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:10 | roRead-only | 0x0 | Reserved |
CIE | 9 | rwNormal read/write | 0 | U3 Entry Enable For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
U3E | 8 | rwNormal read/write | 0 | U3 Entry Enable For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
MAXSLOTSEN | 7:0 | rwNormal read/write | 0 | MAXSLOTSEN For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |