Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_PORTCNTRL Module > PxIS (SATA_AHCI_PORTCNTRL) Register

PxIS (SATA_AHCI_PORTCNTRL) Register

PxIS (SATA_AHCI_PORTCNTRL) Register Description

Register NamePxIS
Relative Address0x0000000010
Absolute Address 0x00FD0C0110 (SATA_AHCI_PORT0_CNTRL)
0x00FD0C0190 (SATA_AHCI_PORT1_CNTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPort x Interupt Status (PxIS)

PxIS (SATA_AHCI_PORTCNTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CPDS31wtcReadable, write a 1 to clear0x0Cold Port Detect Status (CPDS): When set, a device status has changed as detected by the cold presence detect logic.
This bit can either be set due to a non-connected port receiving a device, or a connected port having its device removed.
This bit is only valid if the port supports cold presence detect as indicated by PxCMD.CPD set to 1.
TFES30wtcReadable, write a 1 to clear0x0Task File Error Status (TFES):
This bit is set whenever the status register is updated by the device and the error bit (bit 0 of the Status field in the received FIS) is set.
HBFS29wtcReadable, write a 1 to clear0x0Host Bus Fatal Error Status (HBFS):
Indicates that the HBA encountered a host bus error that it cannot recover from, such as a bad software pointer.
In PCI, such an indication would be a target or master abort.
HBDS28wtcReadable, write a 1 to clear0x0Host Bus Data Error Status (HBDS):
Indicates that the HBA encountered a data error (uncorrectable ECC / parity) when reading from or writing to system memory.
IFS27wtcReadable, write a 1 to clear0x0Interface Fatal Error Status (IFS):
Indicates that the HBA encountered an error on the Serial ATA interface which caused the transfer to stop.
Refer to section 6.1.2.
INFS26wtcReadable, write a 1 to clear0x0Interface Non-fatal Error Status (INFS):
Indicates that the HBA encountered an error on the Serial ATA interface but was able to continue operation.
Refer to section 6.1.2.
Reserved25roRead-only0x0Reserved
OFS24wtcReadable, write a 1 to clear0x0Overflow Status (OFS):
Indicates that the HBA received more bytes from a device than was specified in the PRD table for the command.
IPMS23wtcReadable, write a 1 to clear0x0Incorrect Port Multiplier Status (IPMS):
Indicates that the HBA received a FIS from a device that did not have a command outstanding.
The IPMS bit may be set during enumeration of devices on a Port Multiplier due to the normal Port Multiplier enumeration process.
It is recommended that IPMS only be used after enumeration is complete on the Port Multiplier.
IPMS is not set when an asynchronous notification is received (a Set Device Bits FIS with the Notification N bit set to 1).
PRCS22roRead-only0x0PhyRdy Change Status (PRCS): When set to 1 indicates the internal PhyRdy signal changed state.
This bit reflects the state of PxSERR.DIAG.N.
To clear this bit, software must clear PxSERR.DIAG.N to 0.
Reserved21:8roRead-only0x0Reserved
DMPS 7wtcReadable, write a 1 to clear0x0Device Mechanical Presence Status (DMPS): When set, indicates that a mechanical presence switch associated with this port has been opened or closed, which may lead to a change in the connection state of the device.
This bit is only valid if both CAP.SMPS and PxCMD.MPSP are set to 1.
PCS 6roRead-only0x0Port Connect Change Status (PCS): 1=Change in Current Connect Status. 0=No change in Current Connect Status.
This bit reflects the state of PxSERR.DIAG.X.
This bit is only cleared when PxSERR.DIAG.X is cleared.
DPS 5wtcReadable, write a 1 to clear0x0Descriptor Processed (DPS):
A PRD with the I bit set has transferred all of its data.
Refer to section 5.4.2.
UFS 4roRead-only0x0Unknown FIS Interrupt (UFS): When set to 1, indicates that an unknown FIS was received and has been copied into system memory.
This bit is cleared to 0 by software clearing the PxSERR.DIAG.F bit to 0.
Note that this bit does not directly reflect the PxSERR.DIAG.F bit.
PxSERR.DIAG.F is set immediately when an unknown FIS is detected, whereas this bit is set when that FIS is posted to memory.
Software should wait to act on an unknown FIS until this bit is set to 1 or the two bits may become out of sync.
SDBS 3wtcReadable, write a 1 to clear0x0Set Device Bits Interrupt (SDBS):
A Set Device Bits FIS has been received with the I bit set and has been copied into system memory.
DSS 2wtcReadable, write a 1 to clear0x0DMA Setup FIS Interrupt (DSS):
A DMA Setup FIS has been received with the I bit set and has been copied into system memory.
PSS 1wtcReadable, write a 1 to clear0x0PIO Setup FIS Interrupt (PSS):
A PIO Setup FIS has been received with the I bit set, it has been copied into system memory, and the data related to that FIS has been transferred.
This bit shall be set even if the data transfer resulted in an error.
DHRS 0wtcReadable, write a 1 to clear0x0Device to Host Register FIS Interrupt (DHRS):
A D2H Register FIS has been received with the I bit set, and has been copied into system memory.