Zynq UltraScale+ Devices Register Reference > Module Summary > TPIU Module > FFCR (TPIU) Register

FFCR (TPIU) Register

FFCR (TPIU) Register Description

Register NameFFCR
Relative Address0x0000000304
Absolute Address 0x00FE980304 (CORESIGHT_SOC_TPIU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThis register controls the generation of stop, trigger, and flush events.To disable formatting and put the formatter into bypass mode, bits 1 and 0 must be clear. Setting both bits is the same as setting bit 1.All three flush generating conditions can be enabled together. However, if a second or third flush event is generated from another condition then the current flush completes before the next flush is serviced. Flush from flushin takes priority over flush from Trigger, which in turn completes before a manually activated flush. All Trigger indication conditions can be enabled simultaneously although this can cause the appearance of multiple triggers if flush using trigger is also enabled.Both Stop On settings can be enabled, although if flush on trigger is set up then none of the flushed data is stored. When the system stops, it returns atreadys and does not store the accepted data packets. This is to avoid stalling of any other devices that are connected to a Trace Replicator.If an event in the Formatter and Flush Control Register is required, it must be enabled before the originating event starts. Because requests from flushes and triggers can originate in an asynchronous clock domain, the exact time the component acts on the request cannot be determined with respect to configuring the control.Note - It is recommended that the Trace Port width is changed without enabling continuous mode. Enabling continuous mode causes data to be output from the Trace Port and modifying the port size can result in data not being aligned for power2 port widths.- To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required: one to enable the stop event, if it is not already enabled; one to generate the manual flush.

FFCR (TPIU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
StopTrig13rwNormal read/write0x0Stop the formatter after a Trigger Event is observed. Reset to disabled, or zero.
StopFl12rwNormal read/write0x0This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset, or disabled.
TrigFl10rwNormal read/write0x0Indicates a trigger on Flush completion on afreadys being returned.
TrigEvt 9rwNormal read/write0x0Indicate a trigger on a Trigger Event.
TrigIn 8rwNormal read/write0x0Indicate a trigger on trigin being asserted.
FOnMan 6rwNormal read/write0x0Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit is clear on reset.
FOnTrig 5rwNormal read/write0x0Set this bit to cause a flush of data in the system when a Trigger Event occurs. On reset this bit is clear. A Trigger Event is defined as when the Trigger counter reaches zero or, in the case of the Trigger counter being zero, when trigin is HIGH.
FOnFlIn 4rwNormal read/write0x0Set this bit to enable use of the flushin connection. This is clear on reset.
EnFCont 1rwNormal read/write0x0Embed in trigger packets and indicate null cycles using Sync packets. Reset value is this bit clear. Can only be changed when FtStopped is HIGH.
EnFTC 0rwNormal read/write0x0Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where fitted. On Reset this bit clear. Can only be changed when FtStopped is HIGH.