Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > GQSPI_IER (QSPI) Register
Register Name | GQSPI_IER |
---|---|
Relative Address | 0x0000000108 |
Absolute Address | 0x00FF0F0108 (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | GQSPI Interrupt Enable |
Writing a 1 to this register sets the corresponding bits of the interrupt mask register.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:12 | razRead as zero | 0x0 | reserved |
RX_FIFO_EMPTY | 11 | woWrite-only | 0x0 | RX FIFO Empty interrupt enable 1: enable the interrupt 0: no effect |
Gen_FIFO_full | 10 | woWrite-only | 0x0 | Generic FIFO full interrupt enable 1: enable the interrupt 0: no effect |
Gen_FIFO_not_full | 9 | woWrite-only | 0x0 | Generic FIFO not full interrupt enable 1: enable the interrupt 0: no effect |
TX_FIFO_EMPTY | 8 | woWrite-only | 0x0 | TX FIFO Empty interrupt enable 1: enable the interrupt 0: no effect |
Gen_FIFO_Empty | 7 | woWrite-only | 0x0 | Generic FIFO Empty interrupt enable 1: enable the interrupt 0: no effect |
Reserved | 6 | razRead as zero | 0x0 | Reserved, read as zero, ignored on write. |
RX_FIFO_full | 5 | woWrite-only | 0x0 | RX FIFO full enable 1: enable the interrupt 0: no effect |
RX_FIFO_not_empty | 4 | woWrite-only | 0x0 | RX FIFO not empty enable 1: enable the interrupt 0: no effect |
TX_FIFO_full | 3 | woWrite-only | 0x0 | TX FIFO full enable 1: enable the interrupt 0: no effect |
TX_FIFO_not_full | 2 | woWrite-only | 0x0 | TX FIFO not full enable 1: enable the interrupt 0: no effect |
Poll_Time_Expire | 1 | woWrite-only | 0x0 | Poll Time out counter expire interrupt enable 1: enable the interrupt 0: no effect |
Reserved | 0 | razRead as zero | 0x0 | Reserved, read as zero, ignored on write. |