Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > MASK_DATA_3_LSW (GPIO) Register

MASK_DATA_3_LSW (GPIO) Register

MASK_DATA_3_LSW (GPIO) Register Description

Register NameMASK_DATA_3_LSW
Relative Address0x0000000018
Absolute Address 0x00FF0A0018 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMaskable Output Data (GPIO Bank3, EMIO, Lower 16bits)

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16 bits of bank3, which corresponds to MIO[15:0].

MASK_DATA_3_LSW (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MASK_3_LSW31:16woWrite-only0x0Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW]
DATA_3_LSW15:0rwNormal read/write0x0Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW]