Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_51 (PCIE_ATTRIB) Register

ATTR_51 (PCIE_ATTRIB) Register

ATTR_51 (PCIE_ATTRIB) Register Description

Register NameATTR_51
Relative Address0x00000000CC
Absolute Address 0x00FD4800CC (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00004021
DescriptionATTR_51

This register should only be written to during reset of the PCIe block

ATTR_51 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_pm_base_ptr15:8rwNormal read/write0x40Byte address of the base of the Power Management (PM) Capability Structure. Any access to this structure (via either the link or the management port) is relative to this address.
attr_pcie_revision 7:4rwNormal read/write0x2Not currently in use.
Need to correct this definition: 2 specifies PCI Express v2.0 compliance. 1 specifies PCI Express v1.1 compliance.
0 specifies PCI Express v1.0a compliance.
1 should be used.
Not acted upon.
attr_pcie_cap_slot_implemented 3rwNormal read/write0x0Slot Implemented.
When TRUE, indicates that the PCI Express Link associated with this Port is connected to a slot (rather than to an integrated component).
Valid only for Root Port of Root Complex and Downstream Port of Switch.
Transferred to the PCI Express Capabilities register.
attr_pcie_cap_rsvd_15_14 2:1rwNormal read/write0x0This sets the Reserved bits [15:14] of the PCIE Capability register. These should only be set to 0.
attr_pcie_cap_on 0rwNormal read/write0x1Indicates that the PCIE structures exists. If this is FALSE, then the PCIE structure cannot be accessed via either the link or the management port.