Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DP_STC_REF_CTRL (CRF_APB) Register

DP_STC_REF_CTRL (CRF_APB) Register

DP_STC_REF_CTRL (CRF_APB) Register Description

Register NameDP_STC_REF_CTRL
Relative Address0x000000007C
Absolute Address 0x00FD1A007C (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x01203200
DescriptionDisplayPort System Time Clock Generator Control.

DP_STC_REF_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25rwNormal read/write0x0reserved.
CLKACT24rwNormal read/write0x1Clock active control.
0: disable. Clock stop.
1: enable.
Reserved23:22rwNormal read/write0x0reserved.
DIVISOR121:16rwNormal read/write0x206-bit divider.
Reserved15:14rwNormal read/write0x0reserved.
DIVISOR013:8rwNormal read/write0x326-bit divider.
Reserved 7:3rwNormal read/write0x0reserved.
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: VPLL
010: DPLL
011: RPLL_TO_FPD