Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_REGS Module > host (USB3_REGS) Register
Register Name | host |
---|---|
Relative Address | 0x0000000050 |
Absolute Address |
0x00FF9D0050 (USB3_0) 0x00FF9E0050 (USB3_1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x000007E8 |
Description | Current BELT value |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:12 | razRead as zero | 0x0 | reserved for future |
cur_belt | 11:0 | roRead-only | 0x7E8 | This signal indicates minimum value if all received Tolerance values. This is valid only in Host mode |