Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AV_CHBUF4 (DISPLAY_PORT) Register

AV_CHBUF4 (DISPLAY_PORT) Register

AV_CHBUF4 (DISPLAY_PORT) Register Description

Register NameAV_CHBUF4
Relative Address0x000000B020
Absolute Address 0x00FD4AB020 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAV_CHBUF4

AV_CHBUF4 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:7razRead as zero0x0
BURST_LEN 6:2rwNormal read/write0x0Burst length. Allowable values are 0,1,3(actual burst length will be 1,2,4)
FLUSH 1rwNormal read/write0x0Flush
EN 0rwNormal read/write0x0Enable