Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DQMAP3 (DDRC) Register
Register Name | DQMAP3 |
---|---|
Relative Address | 0x000000028C |
Absolute Address | 0x00FD07028C (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | DQ Map Register 3 |
This register is static. Static registers can only be written when the controller is in reset.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
dq_nibble_map_60_63 | 31:24 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [60-63] |
dq_nibble_map_56_59 | 23:16 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [56-59] |
dq_nibble_map_52_55 | 15:8 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [52-55] |
dq_nibble_map_48_51 | 7:0 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [48-51] |