Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_101 (PCIE_ATTRIB) Register

ATTR_101 (PCIE_ATTRIB) Register

ATTR_101 (PCIE_ATTRIB) Register Description

Register NameATTR_101
Relative Address0x0000000194
Absolute Address 0x00FD480194 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionATTR_101

This register should only be written to during reset of the PCIe block

ATTR_101 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_enable_msg_route15:5rwNormal read/write0x0Enable the routing of message TLPs to the user through the TRN RX interface.
A bit value of 1 enables routing of the message TLP to the user.
Messages are always decoded by the message decoder.
Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off
attr_disable_rx_poisoned_resp 4rwNormal read/write0x0Disable error message and status bit response due to receiving a Poisoned TLP.
attr_disable_rx_tc_filter 3rwNormal read/write0x0Disable TC filtering of received TLPs
attr_disable_id_check 2rwNormal read/write0x0Disable checking for Requester ID of received completions
attr_disable_bar_filtering 1rwNormal read/write0x0Disable BAR filtering.
Does not change the behavior of the bar hit outputs
attr_disable_aspm_l1_timer 0rwNormal read/write0x0Disables the internal timer that causes an Upstream Port enter into ASPM L1.