Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_ITCTRL (SMMU500) Register

SMMU_ITCTRL (SMMU500) Register

SMMU_ITCTRL (SMMU500) Register Description

Register NameSMMU_ITCTRL
Relative Address0x0000002000
Absolute Address 0x00FD802000 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThis register enables the component to switch from functional mode to integration mode. You can directly control the inputs and outputs in integration mode.

SMMU_ITCTRL (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
tbu_index 6:4rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MODULE 3rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
RAM_DATA 2rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
RAM_MODE 1rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
INTGMODE 0rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details