Zynq UltraScale+ Devices Register Reference > Access Types Legend

Access Types Legend

Access TypesDescription
clronrdReadable, clears value on read
clronwrReadable, clears value on write
nsnsroDuring non-secure access, if thread is non-secure, it is read only
nsnsrwDuring non-secure access, if thread is non-secure, it is read write
nsnswoDuring non-secure access, if thread is non-secure, it is write only
nssrazDuring non-secure access, if thread is secure, it is read as zero
razRead as zero
roRead-only
rsw: no effect, r: sets all bits
rudRead undefined
rwNormal read/write
rwsoRead/write, set only
sroDuring secure access, it is read only
srwDuring secure access, it is read write
swoDuring secure access, it is write only
w0cw: 1/0 no effect on/clears matching bit, r: no effect
w0crsw: 1/0 no effect on/clears matching bit, r: sets all bits
w0sw: 1/0 no effect on/sets matching bit, r: no effect
w0srcw: 1/0 no effect on/sets matching bit, r: clears all bits
w0tw: 1/0 no effect on/toggles matching bit, r: no effect
w1w: first one after ~hard~ reset is as-is, other w have no effects, r: no effect
w1crsw: 1/0 clears/no effect on matching bit, r: sets all bits
w1srcw: 1/0 sets/no effect on matching bit, r: clears all bits
w1tw: 1/0 toggles/no effect on matching bit, r: no effect
wazWrite as zero
wcrsw: clears all bits, r: sets all bits
woWrite-only
wo1w: first one after ~hard~ reset is as-is, other w have no effects, r: error
wocw: clears all bits, r: error
wosw: sets all bits, r: error
wrcw: as-is, r: clears all bits
wrsw: as-is, r: sets all bits
wsw: sets all bits, r: no effect
wsrcw: sets all bits, r: clears all bits
wtcReadable, write a 1 to clear
zAccess (read or write) as zero