Zynq UltraScale+ Devices Register Reference > Module Summary > TTC Module
Module Name | TTC Module |
---|---|
Modules of this Type | TTC0, TTC1, TTC2, TTC3 |
Base Address | 0x00FF110000 (TTC0) 0x00FF120000 (TTC1) 0x00FF130000 (TTC2) 0x00FF140000 (TTC3) |
Description | Triple Timer Counter, Triple Timer Counter |
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
Clock_Control_1 | 0x0000000000 | 7 | rwNormal read/write | 0x00000000 | Clock Control register |
Clock_Control_2 | 0x0000000004 | 7 | rwNormal read/write | 0x00000000 | Clock Control register |
Clock_Control_3 | 0x0000000008 | 7 | rwNormal read/write | 0x00000000 | Clock Control register |
Counter_Control_1 | 0x000000000C | 7 | rwNormal read/write | 0x00000021 | Operational mode and reset |
Counter_Control_2 | 0x0000000010 | 7 | rwNormal read/write | 0x00000021 | Operational mode and reset |
Counter_Control_3 | 0x0000000014 | 7 | rwNormal read/write | 0x00000021 | Operational mode and reset |
Counter_Value_1 | 0x0000000018 | 32 | roRead-only | 0x00000000 | Current counter value |
Counter_Value_2 | 0x000000001C | 32 | roRead-only | 0x00000000 | Current counter value |
Counter_Value_3 | 0x0000000020 | 32 | roRead-only | 0x00000000 | Current counter value |
Interval_Counter_1 | 0x0000000024 | 32 | rwNormal read/write | 0x00000000 | Interval value |
Interval_Counter_2 | 0x0000000028 | 32 | rwNormal read/write | 0x00000000 | Interval value |
Interval_Counter_3 | 0x000000002C | 32 | rwNormal read/write | 0x00000000 | Interval value |
Match_1_Counter_1 | 0x0000000030 | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_1_Counter_2 | 0x0000000034 | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_1_Counter_3 | 0x0000000038 | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_2_Counter_1 | 0x000000003C | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_2_Counter_2 | 0x0000000040 | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_2_Counter_3 | 0x0000000044 | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_3_Counter_1 | 0x0000000048 | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_3_Counter_2 | 0x000000004C | 32 | rwNormal read/write | 0x00000000 | Match value |
Match_3_Counter_3 | 0x0000000050 | 32 | rwNormal read/write | 0x00000000 | Match value |
Interrupt_Register_1 | 0x0000000054 | 6 | clronrdReadable, clears value on read | 0x00000000 | Counter 1 Interval, Match, Overflow and Event interrupts |
Interrupt_Register_2 | 0x0000000058 | 6 | clronrdReadable, clears value on read | 0x00000000 | Counter 2 Interval, Match, Overflow and Event interrupts |
Interrupt_Register_3 | 0x000000005C | 6 | clronrdReadable, clears value on read | 0x00000000 | Counter 3 Interval, Match, Overflow and Event interrupts |
Interrupt_Enable_1 | 0x0000000060 | 6 | rwNormal read/write | 0x00000000 | ANDed with corresponding Interrupt Register |
Interrupt_Enable_2 | 0x0000000064 | 6 | rwNormal read/write | 0x00000000 | ANDed with corresponding Interrupt Register |
Interrupt_Enable_3 | 0x0000000068 | 6 | rwNormal read/write | 0x00000000 | ANDed with corresponding Interrupt Register |
Event_Control_Timer_1 | 0x000000006C | 4 | rwNormal read/write | 0x00000000 | Enable, pulse and overflow |
Event_Control_Timer_2 | 0x0000000070 | 4 | rwNormal read/write | 0x00000000 | Enable, pulse and overflow |
Event_Control_Timer_3 | 0x0000000074 | 4 | rwNormal read/write | 0x00000000 | Enable, pulse and overflow |
Event_Register_1 | 0x0000000078 | 32 | roRead-only | 0x00000000 | LPD_LSBUS_CLK clock count for event |
Event_Register_2 | 0x000000007C | 32 | roRead-only | 0x00000000 | LPD_LSBUS_CLK clock count for event |
Event_Register_3 | 0x0000000080 | 32 | roRead-only | 0x00000000 | LPD_LSBUS_CLK clock count for event |