Zynq UltraScale+ Devices Register Reference > Module Summary > RPU Module > RPU1_CFG (RPU) Register

RPU1_CFG (RPU) Register

RPU1_CFG (RPU) Register Description

Register NameRPU1_CFG
Relative Address0x0000000200
Absolute Address 0x00FF9A0200 (RPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000005
DescriptionConfiguration Parameters specific to RPU1

RPU1_CFG (RPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4razRead as zero0x0Reserved for future use
CFGNMFI1 3rwNormal read/write0x0Enables non-maskable fast interrupts for R5 _1,
Low = en FIQ masking by software
High = disable FIQ masking by software
VINITHI 2rwNormal read/write0x1High = Start executing form 0xFFFF0000 (OCM) out of reset.
Low = Start executing from 0x00000000 (ATCM) out of reset.
COHERENT 1rwNormal read/write0x0High = All accesses to peripherals will be through APU Cache Controller.
Low = All accesses to peripherals will be direct and without any Cache Choerency with APU.
nCPUHALT 0rwNormal read/write0x1nCPUHALT bit can be asserted while the processor is in reset to stop the processor from fetching and executing instructions after coming out of reset.When nCPUHALT has been deasserted to start the processor fetching, nCPUHALT must not be asserted again except when the processor is under processor or power-on reset, that is, nRESET asserted. The processor does not halt if the nCPUHALT pin is asserted while the processor is running
low = stops CPU from fetching instructions out of reset, processor is halted
High = Processor is running