Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TXPMA_ST_3 (SERDES) Register

L0_TXPMA_ST_3 (SERDES) Register

L0_TXPMA_ST_3 (SERDES) Register Description

Register NameL0_TXPMA_ST_3
Relative Address0x0000000B0C
Absolute Address 0x00FD400B0C (SERDES)
Width32
TyperoRead-only
Reset Value0x00000020
DescriptionRegister value is generated by Vivado PCW.

L0_TXPMA_ST_3 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TXPMA_ST_3_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
ana_st3_7_6_spare 7:6roRead-only0x0Value generated by PCW.
TX_lseg_dn_rescal_code 5:0roRead-only0x20Value generated by PCW.