Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > ACPU_CTRL (CRF_APB) Register
Register Name | ACPU_CTRL |
---|---|
Relative Address | 0x0000000060 |
Absolute Address | 0x00FD1A0060 (CRF_APB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x03000400 |
Description | APU MPCore Clock Generator Control. |
Register is write protected by crf_apb.crf_wprot [active].
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:28 | rwNormal read/write | 0x0 | reserved. |
Reserved | 27 | rwNormal read/write | 0x0 | reserved. |
Reserved | 26 | rwNormal read/write | 0x0 | reserved. |
CLKACT_HALF | 25 | rwNormal read/write | 0x1 | Clock active control for half-speed APU Clock. 0: disable. Clock stop. 1: enable. |
CLKACT_FULL | 24 | rwNormal read/write | 0x1 | Clock active control for full-speed APU Clock. 0: disable. Clock stop. 1: enable. |
Reserved | 23:14 | rwNormal read/write | 0x0 | reserved. |
DIVISOR0 | 13:8 | rwNormal read/write | 0x4 | 6-bit divider. |
Reserved | 7:3 | rwNormal read/write | 0x0 | reserved. |
SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: APLL 010: DPLL 011: VPLL |