Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX5BDLR5 (DDR_PHY) Register
Register Name | DX5BDLR5 |
---|---|
Relative Address | 0x0000000C58 |
Absolute Address | 0x00FD080C58 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | DATX8 n Bit Delay Line Register 5 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:6 | roRead-only | 0x0 | Return zeroes on reads. |
DMRBD | 5:0 | rwNormal read/write | 0x0 | DM Read Bit Delay: Delay select for the BDL on DM read path. |