Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_COMP_PATTERN_80BIT_3 (DISPLAY_PORT) Register
Register Name | DP_COMP_PATTERN_80BIT_3 |
---|---|
Relative Address | 0x0000000028 |
Absolute Address | 0x00FD4A0028 (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Description same as DP_COMP_PATTERN_80BIT_1 (0x20) |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:16 | razRead as zero | 0x0 | |
BITS_79_64 | 15:0 | rwNormal read/write | 0x0 | Bits [79:64] of 80bit custom pattern |