Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_ITOP_CXT0TO31_RAM0 (SMMU500) Register

SMMU_ITOP_CXT0TO31_RAM0 (SMMU500) Register

SMMU_ITOP_CXT0TO31_RAM0 (SMMU500) Register Description

Register NameSMMU_ITOP_CXT0TO31_RAM0
Relative Address0x0000002010
Absolute Address 0x00FD802010 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionEnable the context performance interrupts.

SMMU_ITOP_CXT0TO31_RAM0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RAM_DATA31:0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details