Zynq UltraScale+ Devices Register Reference > Module Summary > UART Module > Intrpt_dis (UART) Register
Register Name | Intrpt_dis |
---|---|
Relative Address | 0x000000000C |
Absolute Address |
0x00FF00000C (UART0) 0x00FF01000C (UART1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Disable Register |
This write only register is used to disable interrupts. When any bit is written high, the corresponding interrupt is disabled. Writing a low to any bit has no effect.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:14 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
RBRK | 13 | woWrite-only | 0x0 | Receiver break detect interrupt: 0: no effect 1: When set to 1, the Receiver break detect interrupt is disabled |
TOVR | 12 | woWrite-only | 0x0 | Transmitter FIFO Overflow interrupt: 0: no effect 1: disable (sets mask = 1) |
TNFUL | 11 | woWrite-only | 0x0 | Transmitter FIFO Nearly Full interrupt: 0: no effect 1: disable (sets mask = 1) |
TTRIG | 10 | woWrite-only | 0x0 | Transmitter FIFO Trigger interrupt: 0: no effect 1: disable (sets mask = 1) |
DMSI | 9 | woWrite-only | 0x0 | Delta Modem Status Indicator interrupt: 0: no effect 1: disable (sets mask = 1) |
TIMEOUT | 8 | woWrite-only | 0x0 | Receiver Timeout Error interrupt: 0: no effect 1: disable (sets mask = 1) |
PARE | 7 | woWrite-only | 0x0 | Receiver Parity Error interrupt: 0: no effect 1: disable (sets mask = 1) |
FRAME | 6 | woWrite-only | 0x0 | Receiver Framing Error interrupt: 0: no effect 1: disable (sets mask = 1) |
ROVR | 5 | woWrite-only | 0x0 | Receiver Overflow Error interrupt: 0: no effect 1: disable (sets mask = 1) |
TFUL | 4 | woWrite-only | 0x0 | Transmitter FIFO Full interrupt: 0: no effect 1: disable (sets mask = 1) |
TEMPTY | 3 | woWrite-only | 0x0 | Transmitter FIFO Empty interrupt: 0: no effect 1: disable (sets mask = 1) |
RFUL | 2 | woWrite-only | 0x0 | Receiver FIFO Full interrupt: 0: no effect 1: disable (sets mask = 1) |
REMPTY | 1 | woWrite-only | 0x0 | Receiver FIFO Empty interrupt: 0: no effect 1: disable (sets mask = 1) |
RTRIG | 0 | woWrite-only | 0x0 | Receiver FIFO Trigger interrupt: 0: no effect 1: disable (sets mask = 1) |