Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CBAR8 (SMMU500) Register

SMMU_CBAR8 (SMMU500) Register

SMMU_CBAR8 (SMMU500) Register Description

Register NameSMMU_CBAR8
Relative Address0x0000001020
Absolute Address 0x00FD801020 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00020000
DescriptionSpecifies configuration attributes for translation context bank.

SMMU_CBAR8 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
IRPTNDX31:24roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
WACFG23:22rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
RACFG21:20rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
BSU19:18rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TYPE17:16rwNormal read/write0x2Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MEMATTR_CBNDX_7_415:12rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
FB_CBNDX_311rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
HYPC_CBNDX_210rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
BPSHCFG_CBNDX_1_0 9:8rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
VMID 7:0rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details