Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > CIDR1 (TSGEN) Register

CIDR1 (TSGEN) Register

CIDR1 (TSGEN) Register Description

Register NameCIDR1
Relative Address0x0000000FF4
Absolute Address 0x00FE900FF4 (CORESIGHT_SOC_TSGEN)
Width32
TyperoRead-only
Reset Value0x000000F0
DescriptionA component identification register, that indicates that the identification registers are present. This register also indicates the component class.

CIDR1 (TSGEN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLASS 7:4roRead-only0xFClass of the component, for example, ROM table or CoreSight component.
PRMBL_1 3:0roRead-only0x0Contains bits[11:8] of the component identification code.