Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DDR_CTRL (CRF_APB) Register

DDR_CTRL (CRF_APB) Register

DDR_CTRL (CRF_APB) Register Description

Register NameDDR_CTRL
Relative Address0x0000000080
Absolute Address 0x00FD1A0080 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x01000500
DescriptionDDR Memory Controller Clock Generator Control.

DDR_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25rwNormal read/write0x0reserved.
Reserved24rwNormal read/write0x1reserved.
Reserved23:14rwNormal read/write0x0reserved.
DIVISOR013:8rwNormal read/write0x56-bit divider.
Reserved 7:3rwNormal read/write0x0reserved.
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: DPLL
001: VPLL