Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > DCCP_LO (USB3_XHCI) Register
Register Name | DCCP_LO |
---|---|
Relative Address | 0x0000000940 |
Absolute Address |
0x00FE200940 (USB3_0_XHCI) 0x00FE300940 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | DCCP_LO |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DCCPR | 31:4 | rwNormal read/write | 0 | DCCPR |
Reserved | 3:0 | roRead-only | 0x0 | Reserved |