Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L1_TM_MISC1 (SERDES) Register
Register Name | L1_TM_MISC1 |
---|---|
Relative Address | 0x0000005898 |
Absolute Address | 0x00FD405898 (SERDES) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Register value is generated by Vivado PCW. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | roRead-only | 0x0 | reserved. |
hsrx_polarity_flip | 7 | rwNormal read/write | 0x0 | Value generated by PCW. |
Reserved | 6:3 | rwNormal read/write | 0x0 | reserved. |
Reserved | 2 | rwNormal read/write | 0x0 | reserved. |
Reserved | 1 | rwNormal read/write | 0x0 | reserved. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved. |