Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM1_TIMER (VCU_SLCR) Register
Register Name | APM1_TIMER |
---|---|
Relative Address | 0x0000000204 |
Absolute Address | 0x00A0040204 (VCU_SLCR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | APM1_TIMER |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
burst_max_val | 31:0 | rwNormal read/write | 0x0 | Maximum value of clock ticks in timing mode window in case of Mode 2. This is number of AXI clock cycles. Timing window counter will restart once it attains the maximum value. A new timing window start after that. |