Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PIDR3 (SMMU500) Register
Register Name | SMMU_PIDR3 |
---|---|
Relative Address | 0x0000000FEC |
Absolute Address | 0x00FD800FEC (SMMU_GPV) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Peripheral Identificaation register 3 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
RevAnd | 7:4 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
Customer_modified | 3:0 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |