Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU_SINK Module > err_ctrl (XPPU_SINK) Register
Register Name | err_ctrl |
---|---|
Relative Address | 0x000000FFEC |
Absolute Address | 0x00FF9CFFEC (LPD_XPPU_SINK) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Error Control. APB error signal SLVERR. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | rwNormal read/write | 0x0 | reserved. |
pslverr | 0 | rwNormal read/write | 0x0 | Enable the PSLVERR error signal back to APB interconnect when an access violation occurs. 0: disable error signal. 1: assert error signal for access violations. Note: The [addr_decode_err] interrupt bit is set in the ISR regardless of the setting of this bit. |