Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_PIN_5 (IOU_SLCR) Register

MIO_PIN_5 (IOU_SLCR) Register

MIO_PIN_5 (IOU_SLCR) Register Description

Register NameMIO_PIN_5
Relative Address0x0000000014
Absolute Address 0x00FF180014 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionConfigures MIO Pin 5 peripheral interface mapping

MIO_PIN_5 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [5] input/output bank 0.
1: CAN1 RX input.
2: I2C1 SDA input/output clock.
3: FPD SWDT reset output.
4: SPI0 MOSI input/output.
5: TTC1 waveform output.
6: UART1 RxD input.
7: TracePort DQ[3] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: reserved
2: Scan Test [5] input/output.
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: reserved
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: Quad SPI0 SS output.
Reserved 0rwNormal read/write0x0reserved