Zynq UltraScale+ Devices Register Reference > Module Summary > AFIFM Module > WRCTRL (AFIFM) Register

WRCTRL (AFIFM) Register

WRCTRL (AFIFM) Register Description

Register NameWRCTRL
Relative Address0x0000000014
Absolute Address 0x00FD360014 (AFIFM0)
0x00FD370014 (AFIFM1)
0x00FD380014 (AFIFM2)
0x00FD390014 (AFIFM3)
0x00FD3A0014 (AFIFM4)
0x00FD3B0014 (AFIFM5)
0x00FF9B0014 (AFIFM6)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x000003B0
DescriptionWrite Channel Control Register

Control fields for Write Channel operation

WRCTRL (AFIFM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:13razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
WR_RELEASE_MODE12rwNormal read/write0x0Mode of Write Command Release.
1'b0: Release Wr Command on 'Wlast' enqueue into Write Data FIFO (Or, in the case of longer AXI4 style bursts, release when 16 beats are enqueued in to the Write Data FIFO)
1'b1: Release write command immediately it becomes available
Reserved11razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
Reserved10:8rwNormal read/write0x3reserved.
Reserved 7rwNormal read/write0x1reserved.
Reserved 6:4rwNormal read/write0x3reserved.
PAUSE 3rwNormal read/write0x0Pause the issuing of new write commands to the PS-side. Existing write commands will continue to be processed.
FABRIC_QOS_EN 2rwNormal read/write0x0Enable control of QoS from the fabric
0: The QoS bits are derived from APB register, AFIFM_WRQoS.staticQoS
1: The QoS bits are dynamically driven from the fabric input, axds_awQoS[3:0]
FABRIC_WIDTH 1:0rwNormal read/write0x0Configures the Write Channel Fabric interface width.
2b11: Reserved
2b10: 32-bit Fabric
2b01: 64-bit enabled
2b00: 128-bit enabled