Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_presetvalue1 (SDIO) Register
Register Name | reg_presetvalue1 |
---|---|
Relative Address | 0x0000000062 |
Absolute Address |
0x00FF160062 (SD0) 0x00FF170062 (SD1) |
Width | 16 |
Type | roRead-only |
Reset Value | 0x00000004 |
Description | Default Clock and I/O Drive Preset Values. Read clock select values and I/O drive. |
Read the SD_CLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value for Default Speed.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DriverStrengthSelectValue | 15:14 | roRead-only | 0x0 | Driver Strength is supported by 1.8V signaling bus speed modes. 00: Driver Type B is selected. (default) 01: Driver Type A is selected. 10: Driver Type C is selected. 11: Driver Type D is selected. This field is meaningless for 3.3V signaling. |
ClockGeneratorSelectValue | 10 | roRead-only | 0x0 | Select clock generator mode. 0: Host Controller Ver2.00 Clock Model. 1: Programmable Clock Generator. |
SDCLKFrequencySelectValue | 9:0 | roRead-only | 0x4 | 10-bit preset value used by programmable clock unit, loaded into the xxx Control register. |