Zynq UltraScale+ Devices Register Reference > Module Summary > GEM Module > tx_bd_control (GEM) Register

tx_bd_control (GEM) Register

tx_bd_control (GEM) Register Description

Register Nametx_bd_control
Relative Address0x00000004CC
Absolute Address 0x00FF0B04CC (GEM0)
0x00FF0C04CC (GEM1)
0x00FF0D04CC (GEM2)
0x00FF0E04CC (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionTX BD control register

tx_bd_control (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:6roRead-only0x0Reserved, read as zero, ignored on write.
tx_bd_ts_mode 5:4rwNormal read/write0x0TX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames
Reserved 3:0roRead-only0x0Reserved, read as zero, ignored on write.