Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_INIT_WAIT (DISPLAY_PORT) Register

DP_INIT_WAIT (DISPLAY_PORT) Register

DP_INIT_WAIT (DISPLAY_PORT) Register Description

Register NameDP_INIT_WAIT
Relative Address0x00000001CC
Absolute Address 0x00FD4A01CC (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000020
DescriptionThis register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO.

DP_INIT_WAIT (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:7razRead as zero0x0
INIT_WAIT 6:0rwNormal read/write0x20If (MIN_BYTES_PER_TU <= 4 )
-
[6:0] - Set INIT_WAIT to 64
Else
-
[6:0] - Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)