Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CIDR3 (SMMU500) Register

SMMU_CIDR3 (SMMU500) Register

SMMU_CIDR3 (SMMU500) Register Description

Register NameSMMU_CIDR3
Relative Address0x0000000FFC
Absolute Address 0x00FD800FFC (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x000000B1
DescriptionComponent Identification register 3

SMMU_CIDR3 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PREAMBLE 7:0roRead-only0xB1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details