Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ECCUSYN1 (DDRC) Register
Register Name | ECCUSYN1 |
---|---|
Relative Address | 0x00000000B0 |
Absolute Address | 0x00FD0700B0 (DDRC) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | ECC Uncorrected Syndrome Register 1 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ecc_uncorr_syndromes_63_32 | 31:0 | roRead-only | 0x0 | Data pattern that resulted in an uncorrected error, one for each ECC lane, all concatenated together. For 32-bit ECC, this register is not used. |