Zynq UltraScale+ Devices Register Reference > Module Summary > I2C Module > Time_Out (I2C) Register

Time_Out (I2C) Register

Time_Out (I2C) Register Description

Register NameTime_Out
Relative Address0x000000001C
Absolute Address 0x00FF02001C (I2C0)
0x00FF03001C (I2C1)
Width 8
TyperwNormal read/write
Reset Value0x0000001F
DescriptionI/O Clock Signal (SCL) Timeout Period

A timeout interrupt can be generated if the SCL I/O clock signal is held Low for more clocks periods than defined in the [TO] bit field. The sensing is active when the SCL line is held Low by the master or the slave device. This feature detects an interface stall condition.

Time_Out (I2C) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TO 7:0rwNormal read/write0x1FTimeout Period Range: 10h to 7Fh.