Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB8_PMCNTENSET (SMMU500) Register
Register Name | SMMU_CB8_PMCNTENSET |
---|---|
Relative Address | 0x0000018F48 |
Absolute Address | 0x00FD818F48 (SMMU_GPV) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
P3 | 3 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
P2 | 2 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
P1 | 1 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
P0 | 0 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |