Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > OEN_0 (GPIO) Register

OEN_0 (GPIO) Register

OEN_0 (GPIO) Register Description

Register NameOEN_0
Relative Address0x0000000208
Absolute Address 0x00FF0A0208 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionOutput enable (GPIO Bank0, MIO)

When the IO is configured as an output, this controls whether the output is enabled or not. When the output is disabled, the pin is tri-stated. NOTE: The MIO driver setting MIO_MST_TRIx (IOU_SLCR) must be disabled (i.e. set to 0) for this field to be operational. When the MIO tri-state is enabled, the driver is disabled regardless of this GPIO setting. This register controls bank0, which corresponds to MIO[25:0].

OEN_0 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26razRead as zero0x0Not used, read back as zero
OP_ENABLE_025:0rwNormal read/write0x0Output enables
0: disabled
1: enabled
Each bit configures the corresponding pin within the 26-bit bank