Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_PLL_SS_STEP_SIZE_3_MSB (SERDES) Register

L0_PLL_SS_STEP_SIZE_3_MSB (SERDES) Register

L0_PLL_SS_STEP_SIZE_3_MSB (SERDES) Register Description

Register NameL0_PLL_SS_STEP_SIZE_3_MSB
Relative Address0x000000237C
Absolute Address 0x00FD40237C (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_PLL_SS_STEP_SIZE_3_MSB (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PLL_SS_STEP_SIZE_3_MSB_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
tm_force_en_ss 7rwNormal read/write0x0Value generated by PCW.
tm_en_ss 6rwNormal read/write0x0Value generated by PCW.
force_ss_num_of_steps 5rwNormal read/write0x0Value generated by PCW.
force_ss_step_size 4rwNormal read/write0x0Value generated by PCW.
ss_spread_type 3:2rwNormal read/write0x0Value generated by PCW.
ss_step_size_3_msb 1:0rwNormal read/write0x0Value generated by PCW.