Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > PORTPMSC_30 (USB3_XHCI) Register
Register Name | PORTPMSC_30 |
---|---|
Relative Address | 0x0000000434 |
Absolute Address |
0x00FE200434 (USB3_0_XHCI) 0x00FE300434 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:17 | roRead-only | 0x0 | Reserved |
FLA | 16 | rwNormal read/write | 0 | FLA For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
U2_TIMEOUT | 15:8 | rwNormal read/write | 0 | U2_TIMEOUT For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
U1_TIMEOUT | 7:0 | rwNormal read/write | 0 | U1_TIMEOUT For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |