Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_MISC1 (SERDES) Register

L0_TM_MISC1 (SERDES) Register

L0_TM_MISC1 (SERDES) Register Description

Register NameL0_TM_MISC1
Relative Address0x0000001898
Absolute Address 0x00FD401898 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_MISC1 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0reserved.
hsrx_polarity_flip 7rwNormal read/write0x0Value generated by PCW.
Reserved 6:3rwNormal read/write0x0reserved.
Reserved 2rwNormal read/write0x0reserved.
Reserved 1rwNormal read/write0x0reserved.
Reserved 0rwNormal read/write0x0reserved.