Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DQMAP3 (DDRC) Register

DQMAP3 (DDRC) Register

DQMAP3 (DDRC) Register Description

Register NameDQMAP3
Relative Address0x000000028C
Absolute Address 0x00FD07028C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDQ Map Register 3

This register is static. Static registers can only be written when the controller is in reset.

DQMAP3 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dq_nibble_map_60_6331:24rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [60-63]
dq_nibble_map_56_5923:16rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [56-59]
dq_nibble_map_52_5515:8rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [52-55]
dq_nibble_map_48_51 7:0rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [48-51]