Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TX_ANA_TM_18 (SERDES) Register

L0_TX_ANA_TM_18 (SERDES) Register

L0_TX_ANA_TM_18 (SERDES) Register Description

Register NameL0_TX_ANA_TM_18
Relative Address0x0000000048
Absolute Address 0x00FD400048 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000002
DescriptionRegister value is generated by Vivado PCW.

L0_TX_ANA_TM_18 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TX_ANA_TM_18_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
pipe_TX_Deemph_7_0 7:0rwNormal read/write0x2Value generated by PCW.