Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_PIN_28 (IOU_SLCR) Register
Register Name | MIO_PIN_28 |
---|---|
Relative Address | 0x0000000070 |
Absolute Address | 0x00FF180070 (IOU_SLCR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | MIO Device Pin 28 Multiplexer Controls. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | rwNormal read/write | 0x0 | reserved |
L3_SEL | 7:5 | rwNormal read/write | 0x0 | Level 3 Mux Select: 0: GPIO [28] input/output bank 1. 1: CAN1 TX output. 2: I2C0 SCL input/output clock. 3: PJTAG TDO output. 4: SPI0 SS [1] output. 5: TTC1 clock input. 6: UART1 TxD output. 7: TracePort DQ[6] output. |
L2_SEL | 4:3 | rwNormal read/write | 0x0 | Level 2 Mux Select: 0: Level 3 Mux output 1: PMU GPI1 [12] input. 2: Scan Test [28] input/output. 3: DisplayPort Aux Hot Plug input. |
L1_SEL | 2 | rwNormal read/write | 0x0 | Level 1 Mux Select: 0: Level 2 Mux output. 1: NAND Ready/Busy input. |
L0_SEL | 1 | rwNormal read/write | 0x0 | Level 0 Mux Select: 0: Level 1 Mux output 1: GEM0 RGMII Tx Data [1] output. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved |