Zynq UltraScale+ Devices Register Reference > Module Summary > CSUDMA Module

CSUDMA Module

CSUDMA Module Description

Module NameCSUDMA Module
Modules of this TypeCSUDMA
Base Address0x00FFC80000 (CSUDMA)
DescriptionCSU Module DMA Controller, CSU DMA Control

CSUDMA Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
CSUDMA_SRC_ADDR0x000000000032mixedMixed types. See bit-field details.0x00000000Source mem address (lsbs) for DMA memory->stream data transfer
CSUDMA_SRC_SIZE0x000000000432mixedMixed types. See bit-field details.0x00000000DMA transfer payload for DMA memory-> stream data transfer
CSUDMA_SRC_STS0x000000000832mixedMixed types. See bit-field details.0x00000000General SRC DMA Status
CSUDMA_SRC_CTRL0x000000000C32mixedMixed types. See bit-field details.0x003FFA00General SRC DMA Control Register 1
CSUDMA_SRC_CRC0x000000001032rwNormal read/write0x00000000SRC DMA Pseudo CRC
CSUDMA_SRC_I_STS0x000000001432mixedMixed types. See bit-field details.0x00000000SRC DMA Interrupt Status Register
CSUDMA_SRC_I_EN0x000000001832mixedMixed types. See bit-field details.0x00000000SRC DMA Interrupt Enable
CSUDMA_SRC_I_DIS0x000000001C32mixedMixed types. See bit-field details.0x00000000SRC DMA Interrupt Disable
CSUDMA_SRC_I_MASK0x000000002032mixedMixed types. See bit-field details.0x0000007FSRC DMA Interrupt Mask
CSUDMA_SRC_CTRL20x000000002432mixedMixed types. See bit-field details.0x081BFFF8General SRC DMA Control Register 2
CSUDMA_SRC_ADDR_MSB0x000000002832mixedMixed types. See bit-field details.0x00000000Source mem address (msbs) for DMA memory->stream data transfer
CSUDMA_DST_ADDR0x000000080032mixedMixed types. See bit-field details.0x00000000Destination mem address (lsbs) for DMA stream->memory data transfer
CSUDMA_DST_SIZE0x000000080432mixedMixed types. See bit-field details.0x00000000DMA transfer payload for DMA stream-> memory data transfer
CSUDMA_DST_STS0x000000080832mixedMixed types. See bit-field details.0x00000000General DST DMA Status
CSUDMA_DST_CTRL0x000000080C32rwNormal read/write0x803FFA00General DST DMA Control
CSUDMA_DST_I_STS0x000000081432mixedMixed types. See bit-field details.0x00000000DST DMA Interrupt Status Register
CSUDMA_DST_I_EN0x000000081832mixedMixed types. See bit-field details.0x00000000DST DMA Interrupt Enable
CSUDMA_DST_I_DIS0x000000081C32mixedMixed types. See bit-field details.0x00000000DST DMA Interrupt Disable
CSUDMA_DST_I_MASK0x000000082032mixedMixed types. See bit-field details.0x000000FEDST DMA Interrupt Mask
CSUDMA_DST_CTRL20x000000082432mixedMixed types. See bit-field details.0x081BFFF8General DST DMA Control Register 2
CSUDMA_DST_ADDR_MSB0x000000082832mixedMixed types. See bit-field details.0x00000000Destination mem address (msbs) for DMA stream->memory data transfer
CSUDMA_SAFETY_CHK0x0000000FF832rwNormal read/write0x00000000Safety endpoint connectivity check Register