Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_EQ1 (SERDES) Register

L0_TM_EQ1 (SERDES) Register

L0_TM_EQ1 (SERDES) Register Description

Register NameL0_TM_EQ1
Relative Address0x0000001950
Absolute Address 0x00FD401950 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_EQ1 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_EQ1_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
eq_stg1_preamp_mode_val 7rwNormal read/write0x0Value generated by PCW.
eq_stg1_rl_prog 6:5rwNormal read/write0x0Value generated by PCW.
eq_stg2_cm_prog 4:3rwNormal read/write0x0Value generated by PCW.
eq_stg2_preamp_mode_val 2rwNormal read/write0x0Value generated by PCW.
eq_stg2_rl_prog 1:0rwNormal read/write0x0Value generated by PCW.