Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DRAMTMG10 (DDRC) Register

DRAMTMG10 (DDRC) Register

DRAMTMG10 (DDRC) Register Description

Register NameDRAMTMG10
Relative Address0x0000000128
Absolute Address 0x00FD070128 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x001C180A
DescriptionSDRAM Timing Register 10

This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG10 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved20:16rwNormal read/write0x1Creserved.
Reserved12:8rwNormal read/write0x18reserved.
Reserved 3:2rwNormal read/write0x2reserved.
Reserved 1:0rwNormal read/write0x2reserved.