Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AV_BUF_AUDIO_CH_CONFIG (DISPLAY_PORT) Register

AV_BUF_AUDIO_CH_CONFIG (DISPLAY_PORT) Register

AV_BUF_AUDIO_CH_CONFIG (DISPLAY_PORT) Register Description

Register NameAV_BUF_AUDIO_CH_CONFIG
Relative Address0x000000B12C
Absolute Address 0x00FD4AB12C (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAV_BUF_AUDIO_CH_CONFIG

AV_BUF_AUDIO_CH_CONFIG (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0
AUD_CH_ID 1:0rwNormal read/write0x0Bit [0] - For non live audio
- 0: Bits [31:16] are right channel and [15:0] are left channel sample
- 1: Bits [31:16] are left channel and [15:0] are right channel sample
Bit [1] - For non live graphics audio
- 0: Bits [31:16] are right channel and [15:0] are left channel sample
- 1: Bits [31:16] are left channel and [15:0] are right channel sample