Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_GPV Module
Module Name | IOU_GPV Module |
---|---|
Modules of this Type | IOU_GPV |
Base Address | 0x00FE000000 (IOU_GPV) |
Description | IOP GPV, GPV |
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
periph_id_4 | 0x0000001FD0 | 32 | roRead-only | 0x00000004 | 4KB count, JEP106 continuation code |
periph_id_5 | 0x0000001FD4 | 32 | roRead-only | 0x00000000 | Reserved |
periph_id_6 | 0x0000001FD8 | 32 | roRead-only | 0x00000000 | Reserved |
periph_id_7 | 0x0000001FDC | 32 | roRead-only | 0x00000000 | Reserved |
periph_id_0 | 0x0000001FE0 | 32 | roRead-only | 0x00000000 | Part Number [7:0] |
periph_id_1 | 0x0000001FE4 | 32 | roRead-only | 0x000000B4 | JEP106[3:0], part number [11:8] |
periph_id_2 | 0x0000001FE8 | 32 | roRead-only | 0x0000002B | Revision, JEP106 code flag, JEP106[6:4] |
periph_id_3 | 0x0000001FEC | 32 | roRead-only | 0x00000000 | You can set this using the AMBA Designer Graphical User Interface (GUI) |
comp_id_0 | 0x0000001FF0 | 32 | roRead-only | 0x0000000D | Preamble |
comp_id_1 | 0x0000001FF4 | 32 | roRead-only | 0x000000F0 | Generic IP component class, preamble |
comp_id_2 | 0x0000001FF8 | 32 | roRead-only | 0x00000005 | Preamble |
comp_id_3 | 0x0000001FFC | 32 | roRead-only | 0x000000B1 | Preamble |
intiou_intlpd_fn_mod_iss_bm | 0x0000002008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
apb_ns_0_ib_fn_mod_iss_bm | 0x0000007008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
apb_ns_1_ib_fn_mod_iss_bm | 0x0000008008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_intiou_fn_mod | 0x0000042108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
intlpd_intiou_qos_cntl | 0x000004210C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
intlpd_intiou_max_ot | 0x0000042110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
intlpd_intiou_max_comb_ot | 0x0000042114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
intlpd_intiou_aw_p | 0x0000042118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
intlpd_intiou_aw_b | 0x000004211C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
intlpd_intiou_aw_r | 0x0000042120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
intlpd_intiou_ar_p | 0x0000042124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
intlpd_intiou_ar_b | 0x0000042128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
intlpd_intiou_ar_r | 0x000004212C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
gem0M_intiou_read_qos | 0x0000043100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
gem0M_intiou_write_qos | 0x0000043104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
gem0M_intiou_fn_mod | 0x0000043108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
gem0M_intiou_qos_cntl | 0x000004310C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
gem0M_intiou_max_ot | 0x0000043110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
gem0M_intiou_max_comb_ot | 0x0000043114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
gem0M_intiou_aw_p | 0x0000043118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
gem0M_intiou_aw_b | 0x000004311C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
gem0M_intiou_aw_r | 0x0000043120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
gem0M_intiou_ar_p | 0x0000043124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
gem0M_intiou_ar_b | 0x0000043128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
gem0M_intiou_ar_r | 0x000004312C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
gem1M_intiou_read_qos | 0x0000044100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
gem1M_intiou_write_qos | 0x0000044104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
gem1M_intiou_fn_mod | 0x0000044108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
gem1M_intiou_qos_cntl | 0x000004410C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
gem1M_intiou_max_ot | 0x0000044110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
gem1M_intiou_max_comb_ot | 0x0000044114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
gem1M_intiou_aw_p | 0x0000044118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
gem1M_intiou_aw_b | 0x000004411C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
gem1M_intiou_aw_r | 0x0000044120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
gem1M_intiou_ar_p | 0x0000044124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
gem1M_intiou_ar_b | 0x0000044128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
gem1M_intiou_ar_r | 0x000004412C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
gem2M_intiou_read_qos | 0x0000045100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
gem2M_intiou_write_qos | 0x0000045104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
gem2M_intiou_fn_mod | 0x0000045108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
gem2M_intiou_qos_cntl | 0x000004510C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
gem2M_intiou_max_ot | 0x0000045110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
gem2M_intiou_max_comb_ot | 0x0000045114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
gem2M_intiou_aw_p | 0x0000045118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
gem2M_intiou_aw_b | 0x000004511C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
gem2M_intiou_aw_r | 0x0000045120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
gem2M_intiou_ar_p | 0x0000045124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
gem2M_intiou_ar_b | 0x0000045128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
gem2M_intiou_ar_r | 0x000004512C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
gem3M_intiou_read_qos | 0x0000046100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
gem3M_intiou_write_qos | 0x0000046104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
gem3M_intiou_fn_mod | 0x0000046108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
gem3M_intiou_qos_cntl | 0x000004610C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
gem3M_intiou_max_ot | 0x0000046110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
gem3M_intiou_max_comb_ot | 0x0000046114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
gem3M_intiou_aw_p | 0x0000046118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
gem3M_intiou_aw_b | 0x000004611C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
gem3M_intiou_aw_r | 0x0000046120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
gem3M_intiou_ar_p | 0x0000046124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
gem3M_intiou_ar_b | 0x0000046128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
gem3M_intiou_ar_r | 0x000004612C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
nandM_intiou_ib_fn_mod2 | 0x0000047024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
nandM_intiou_ib_read_qos | 0x0000047100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
nandM_intiou_ib_write_qos | 0x0000047104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
nandM_intiou_ib_fn_mod | 0x0000047108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
nandM_intiou_ib_qos_cntl | 0x000004710C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
nandM_intiou_ib_max_ot | 0x0000047110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
nandM_intiou_ib_max_comb_ot | 0x0000047114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
nandM_intiou_ib_aw_p | 0x0000047118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
nandM_intiou_ib_aw_b | 0x000004711C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
nandM_intiou_ib_aw_r | 0x0000047120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
nandM_intiou_ib_ar_p | 0x0000047124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
nandM_intiou_ib_ar_b | 0x0000047128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
nandM_intiou_ib_ar_r | 0x000004712C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
sd0M_intiou_ib_fn_mod2 | 0x0000048024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
sd0M_intiou_ib_read_qos | 0x0000048100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
sd0M_intiou_ib_write_qos | 0x0000048104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
sd0M_intiou_ib_fn_mod | 0x0000048108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
sd0M_intiou_ib_qos_cntl | 0x000004810C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
sd0M_intiou_ib_max_ot | 0x0000048110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
sd0M_intiou_ib_max_comb_ot | 0x0000048114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
sd0M_intiou_ib_aw_p | 0x0000048118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
sd0M_intiou_ib_aw_b | 0x000004811C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
sd0M_intiou_ib_aw_r | 0x0000048120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
sd0M_intiou_ib_ar_p | 0x0000048124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
sd0M_intiou_ib_ar_b | 0x0000048128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
sd0M_intiou_ib_ar_r | 0x000004812C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
sd1M_intiou_ib_fn_mod2 | 0x0000049024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
sd1M_intiou_ib_read_qos | 0x0000049100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
sd1M_intiou_ib_write_qos | 0x0000049104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
sd1M_intiou_ib_fn_mod | 0x0000049108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
sd1M_intiou_ib_qos_cntl | 0x000004910C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
sd1M_intiou_ib_max_ot | 0x0000049110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
sd1M_intiou_ib_max_comb_ot | 0x0000049114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
sd1M_intiou_ib_aw_p | 0x0000049118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
sd1M_intiou_ib_aw_b | 0x000004911C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
sd1M_intiou_ib_aw_r | 0x0000049120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
sd1M_intiou_ib_ar_p | 0x0000049124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
sd1M_intiou_ib_ar_b | 0x0000049128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
sd1M_intiou_ib_ar_r | 0x000004912C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
qspiM_intiou_ib_fn_mod2 | 0x000004A024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
qspiM_intiou_ib_read_qos | 0x000004A100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
qspiM_intiou_ib_write_qos | 0x000004A104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
qspiM_intiou_ib_fn_mod | 0x000004A108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
qspiM_intiou_ib_qos_cntl | 0x000004A10C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
qspiM_intiou_ib_max_ot | 0x000004A110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
qspiM_intiou_ib_max_comb_ot | 0x000004A114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
qspiM_intiou_ib_aw_p | 0x000004A118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
qspiM_intiou_ib_aw_b | 0x000004A11C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
qspiM_intiou_ib_aw_r | 0x000004A120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
qspiM_intiou_ib_ar_p | 0x000004A124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
qspiM_intiou_ib_ar_b | 0x000004A128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
qspiM_intiou_ib_ar_r | 0x000004A12C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |