Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_MST_TRI0 (IOU_SLCR) Register
Register Name | MIO_MST_TRI0 |
---|---|
Relative Address | 0x0000000204 |
Absolute Address | 0x00FF180204 (IOU_SLCR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0xFFFFFFFF |
Description | MIO pin Tri-state Enables, 31:0 |
Parallel access to the master tri-state enables for MIO pins
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PIN_31_TRI | 31 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 31, active high |
PIN_30_TRI | 30 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 30, active high |
PIN_29_TRI | 29 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 29, active high |
PIN_28_TRI | 28 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 28, active high |
PIN_27_TRI | 27 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 27, active high |
PIN_26_TRI | 26 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 26, active high |
PIN_25_TRI | 25 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 25, active high |
PIN_24_TRI | 24 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 24, active high |
PIN_23_TRI | 23 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 23, active high |
PIN_22_TRI | 22 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 22, active high |
PIN_21_TRI | 21 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 21, active high |
PIN_20_TRI | 20 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 20, active high |
PIN_19_TRI | 19 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 19, active high |
PIN_18_TRI | 18 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 18, active high |
PIN_17_TRI | 17 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 17, active high |
PIN_16_TRI | 16 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 16, active high |
PIN_15_TRI | 15 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 15, active high |
PIN_14_TRI | 14 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 14, active high |
PIN_13_TRI | 13 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 13, active high |
PIN_12_TRI | 12 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 12, active high |
PIN_11_TRI | 11 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 11, active high |
PIN_10_TRI | 10 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 10, active high |
PIN_09_TRI | 9 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 9, active high |
PIN_08_TRI | 8 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 8, active high |
PIN_07_TRI | 7 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 7, active high |
PIN_06_TRI | 6 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 6, active high |
PIN_05_TRI | 5 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 5, active high |
PIN_04_TRI | 4 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 4, active high |
PIN_03_TRI | 3 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 3, active high |
PIN_02_TRI | 2 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 2, active high |
PIN_01_TRI | 1 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 1, active high |
PIN_00_TRI | 0 | rwNormal read/write | 0x1 | Master Tri-state Enable for pin 0, active high |