Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > PMCR (SMMU500) Register

PMCR (SMMU500) Register

PMCR (SMMU500) Register Description

Register NamePMCR
Relative Address0x0000003E04
Absolute Address 0x00FD803E04 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPerformance Monitor Configuration register controls the behaviour of the event counters.

PMCR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
IMP31:24roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
X 4rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P 1roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
E 0rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details