Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_POLARITY (DISPLAY_PORT) Register

DP_MAIN_STREAM_POLARITY (DISPLAY_PORT) Register

DP_MAIN_STREAM_POLARITY (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_POLARITY
Relative Address0x0000000188
Absolute Address 0x00FD4A0188 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionProvides the polarity values for the video sync signals

DP_MAIN_STREAM_POLARITY (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0
VSYNC_POLARITY 1rwNormal read/write0x0Polarity of the vertical sync pulse
HSYNC_POLARITY 0rwNormal read/write0x0Polarity of the horizontal sync pulse.