Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB12_PMEVCNTR2 (SMMU500) Register

SMMU_CB12_PMEVCNTR2 (SMMU500) Register

SMMU_CB12_PMEVCNTR2 (SMMU500) Register Description

Register NameSMMU_CB12_PMEVCNTR2
Relative Address0x000001CE08
Absolute Address 0x00FD81CE08 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter.

SMMU_CB12_PMEVCNTR2 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details