Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_VENDOR Module > PLS1 (SATA_AHCI_VENDOR) Register
Register Name | PLS1 |
---|---|
Relative Address | 0x0000000040 |
Absolute Address | 0x00FD0C00E0 (SATA_AHCI_VENDOR) |
Width | 32 |
Type | wtcReadable, write a 1 to clear |
Reset Value | 0x00000000 |
Description | Port Link-layer Status 1. |
Indicates the status of the Link Layer for either Port 0 or Port 1. The Port monitored is controlled by the value programmed into the Port Config Register. This register acts as an accumulator for the SERDES errors. Each counter can be cleared by writing 8hFF to the individual byte. Note: All Status Registers have no predefined Reset value. The value shown in reset is a typical value that will be read after reset but will be dependent on the SERDES status, the actual value read can differ from this.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
KCEC | 31:24 | wtcReadable, write a 1 to clear | 0x0 | Kchar Error Count (KCEC): The number of DWords that have been received from the Phy, where one or more control character errors have been detected. A value of 255 indicates an error count of 255 or more as this counter does not wrap around to zero. The count value is updated with its current value each time the Status1 register is read. |
PIEC | 23:16 | wtcReadable, write a 1 to clear | 0x0 | Phy Internal Error Count (PIEC): The number of DWords that have been received from the Phy, where one or more internal errors have been detected. A value of 255 indicates an error count of 255 or more as this counter does not wrap around to zero. The count value is updated with its current value each time the Status1 register is read. |
CEC | 15:8 | wtcReadable, write a 1 to clear | 0x0 | Code Error Count (CEC): The number of DWords that have been received from the Phy, where one or more code errors have been detected. A value of 255 indicates an error count of 255 or more as this counter does not wrap around to zero. The count value is updated with its current value each time the Status1 register is read. |
DEC | 7:0 | wtcReadable, write a 1 to clear | 0x0 | Disparity Error Count (DEC): The number of DWords that have been received from the Phy, where one or more disparity errors have been detected. A value of 255 indicates an error count of 255 or more as this counter does not wrap around to zero. The count value is updated with its current value each time the Status1 register is read. |