Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ERROR_STATUS_1 (PMU_GLOBAL) Register
Register Name | ERROR_STATUS_1 |
---|---|
Relative Address | 0x0000000530 |
Absolute Address | 0x00FFD80530 (PMU_GLOBAL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | System Errors; Interrupt Clear and Status, Reg 1. |
The software can read the status and clear the errors: READ: 0: no error. 1: error detected. WRITE: 0: no effect. 1: clear bit to 0. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers. The system errors can be generated by many areas of the PS and PL. Register is reset only by the PS_POR_B reset signal pin.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31 | wtcReadable, write a 1 to clear | 0x0 | reserved. |
Reserved | 30 | wtcReadable, write a 1 to clear | 0x0 | reserved. |
Reserved | 29 | wtcReadable, write a 1 to clear | 0x0 | reserved. |
Reserved | 28 | wtcReadable, write a 1 to clear | 0x0 | reserved. |
CSU_SWDT | 27 | wtcReadable, write a 1 to clear | 0x0 | CSU_SWDT watchdog timeout error. |
CLK_MON | 26 | wtcReadable, write a 1 to clear | 0x0 | Clock Monitor (ClkMon) Error. Selected clock is not within acceptable frequency range. Refer to TRM. |
XMPU | 25:24 | wtcReadable, write a 1 to clear | 0x0 | Protect Unit errors. Bit [24] is OR of OCM_XMPU, XPPU error signals. Bit [25] is OR of FPD_XMPU, DDR_MPU error signals. |
PWR_SUPPLY | 23:16 | wtcReadable, write a 1 to clear | 0x0 | Bit [16] is for VCC_PS_LPD. Bit [17] is for VCC_PS_FPD. Bit [18] is for VCC_PS_AUX. Bit [19] is for VCCO_PS_DDR. Bit [20] is for VCCO_PS_3. Bit [21] is for VCCO_PS_0. Bit [22] is for VCCO_PS_1. Bit [23] is for VCCO_PS_2. |
Reserved | 15:14 | roRead-only | 0x0 | reserved |
FPD_SWDT | 13 | wtcReadable, write a 1 to clear | 0x0 | FPD_SWDT watchdog timeout error. |
LPD_SWDT | 12 | wtcReadable, write a 1 to clear | 0x0 | LPD_SWDT watchdog timeout error. |
Reserved | 11:10 | roRead-only | 0x0 | reserved |
RPU_CCF | 9 | wtcReadable, write a 1 to clear | 0x0 | RPU Common Cause Failure (CCF) Errors ORed together. Represents one or more errors. |
Reserved | 8 | roRead-only | 0x0 | reserved |
RPU_LS | 7:6 | wtcReadable, write a 1 to clear | 0x0 | RPU Lockstep Error detected: 00: no error. 01: lockstep error. 10: lockstep error. 11: lockstep error. |
FPD_TEMP | 5 | wtcReadable, write a 1 to clear | 0x0 | FPD Over Temperature sensor, TEMP_FPD_OT from PS SysMon unit. |
LPD_TEMP | 4 | wtcReadable, write a 1 to clear | 0x0 | LPD Over Temperature sensor, TEMP_LPD_OT from PS SysMon unit. |
RPU1 | 3 | wtcReadable, write a 1 to clear | 0x0 | RPU1 Error including both Correctable and Uncorrectable Errors |
RPU0 | 2 | wtcReadable, write a 1 to clear | 0x0 | RPU0 Error including both Correctable and Uncorrectable Errors |
OCM_ECC | 1 | wtcReadable, write a 1 to clear | 0x0 | OCM Uncorrectable ECC Error. |
DDR_ECC | 0 | wtcReadable, write a 1 to clear | 0x0 | DDR Uncorrectable ECC Error. |