Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > IOPLL_CTRL (CRL_APB) Register
Register Name | IOPLL_CTRL |
---|---|
Relative Address | 0x0000000020 |
Absolute Address | 0x00FF5E0020 (CRL_APB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00012C09 |
Description | IOPLL Clock Unit Control. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:27 | rwNormal read/write | 0x0 | reserved. |
POST_SRC | 26:24 | rwNormal read/write | 0x0 | Select the pass-thru clock source for PLL Bypass mode. 0xx: PS_REF_CLK 100: VIDEO_REF_CLK 101: ALT_REF_CLK 110: AUX_REF_CLK 111: GT_REF_CLK |
Reserved | 23 | rwNormal read/write | 0x0 | reserved. |
PRE_SRC | 22:20 | rwNormal read/write | 0x0 | Select the clock source for PLL input. 0xx: PS_REF_CLK 100: VIDEO_REF_CLK 101: ALT_REF_CLK 110: AUX_REF_CLK 111: GT_REF_CLK |
Reserved | 19:18 | rwNormal read/write | 0x0 | reserved. |
Reserved | 17 | rwNormal read/write | 0x0 | reserved. |
DIV2 | 16 | rwNormal read/write | 0x1 | Enable the divide by 2 function inside of the PLL. 0: no effect. 1: divide clock by 2. Note: this does not change the VCO frequency, just the output frequency. |
Reserved | 15 | rwNormal read/write | 0x0 | reserved. |
FBDIV | 14:8 | rwNormal read/write | 0x2C | Feedback divisor integer portion for the PLL. |
Reserved | 7:4 | rwNormal read/write | 0x0 | reserved. |
BYPASS | 3 | rwNormal read/write | 0x1 | PLL Clock Bypass Mode. 0: normal PLL mode; the source clock is selected using [PRE_SRC]. 1: bypass the PLL; the source clock is selected using [POST_SRC]. |
Reserved | 2:1 | rwNormal read/write | 0x0 | reserved. |
RESET | 0 | rwNormal read/write | 0x1 | PLL reset. 0: active. 1: held in reset. Note: Program the PLL into bypass mode before resetting the PLL. |