Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_SMR39 (SMMU500) Register
Register Name | SMMU_SMR39 |
---|---|
Relative Address | 0x000000089C |
Absolute Address | 0x00FD80089C (SMMU_GPV) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Matches a transaction with a particular Stream mapping register group. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
VALID | 31 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
MASK | 30:16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
ID | 14:0 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |