Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > V_BLEND_IN1CSC_COEFF5 (DISPLAY_PORT) Register
Register Name | V_BLEND_IN1CSC_COEFF5 |
---|---|
Relative Address | 0x000000A058 |
Absolute Address | 0x00FD4AA058 (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | V_BLEND_IN1CSC_COEFF5:Description same as V_BLEND_IN1CSC_COEFF0 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:15 | razRead as zero | 0x0 | |
Y2R_C5 | 14:0 | rwNormal read/write | 0x0 | Signed representation of value. |