Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > CRCPARSTAT (DDRC) Register
Register Name | CRCPARSTAT |
---|---|
Relative Address | 0x00000000CC |
Absolute Address | 0x00FD0700CC (DDRC) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | CRC Parity Status Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
cmd_in_err_window | 29 | roRead-only | 0x0 | Indicate if commands are in the parity/crc error window. - 0 - No command is in the parity/crc error window. - 1 - One or more commands are in the parity/crc error window or retry is in progress. This register is valid when CRCPARCTRL1.crc_parity_retry_enable=1. |
retry_operating_mode | 28 | roRead-only | 0x0 | Operating mode of retry - 0 - Normal - 1 - Retry due to CRC/Parity error is in progress |
retry_current_state | 27:24 | roRead-only | 0x0 | Indicate current retry state for debug purposes only - 0000 - IDLE:Retry is not enabled - 0001 - MON_DFI:Retry is enabled and monitoring DFI - 0010 - DETECTED ALERT:Detected dfi_alert_n - 0011 - WAKE_UP:Waking up from self-refresh state - 0100 - PRECHRGING:Pre-charging banks - 0101 - SEND_REF1:Sending extra REFs before software intervention time - 0110 - CTRLUPD:Issuing control update from retry logic - 0111 - WAIT_SW:Software intervention time - 1000 - SEND_REF2:Sending extra REFs before retrying commands - 1001 - RETRY_COMMANDS:Retrying commands - 1010 - RESTART_RETRY:Restarting retry due to alert_n detection during retry - 1111 - FATL_ERR:Fatal error detected FOR DEBUG PURPOSE ONLY |
dfi_alert_err_fatl_code | 22:20 | roRead-only | 0x0 | Indicate reason of dfi_alert_err_fatl_int assertion - [22] MPSMX caused parity error. (RCDs parity error detection only) - [21] Parity error happens again during software intervention time - [20] MRS was in retry_fifo_max_hold_timer_x4 window from alert_n=0 or STAT.operating_mode is Init. Two or more reason can be available at the same time It remains set until cleared by CRCPARCTL0.dfi_alert_err_fatl_clr. |
dfi_alert_err_no_sw | 19 | roRead-only | 0x0 | Indicate whether software can perform MRS/MPR/PDA during software intervention time. - 0 - MRS/MPR/PDA can be performed during software intervention time - 1 - MRS/MPR/PDA can NOT be performed during software intervention time If CRCPARCTL1.alert_wait_for_sw=1 and dfi_alert_err_no_sw=1, software can not perform MRS/MPR/PDA until dfi_alert_err_int is cleared by dfi_alert_err_int_clr. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr. |
dfi_alert_err_max_reached_int | 18 | roRead-only | 0x0 | DFI alert error counter max reached interrupt. If the CRCPARSTAT.dfi_alert_err_cnt reaches it maximum value, this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr |
dfi_alert_err_fatl_int | 17 | roRead-only | 0x0 | Fatal parity error interrupt. One or more these situation below happens, this interrupt bit is set. - PDA operation is in progress/started during retry is in control - Parity error happens again during dfi_alert_err_inrt=1 - MRS was in retry_fifo_max_hold_timer_x4 window from alert_n=0. It remains set until cleared by CRCPARCTL0.dfi_alert_err_fatl_clr. If this interrupt is asserted, system reset is strongly recommended. |
dfi_alert_err_int | 16 | roRead-only | 0x0 | DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr |
dfi_alert_err_cnt | 15:0 | roRead-only | 0x0 | DFI alert error count. If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. |