Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ADDR_ERROR_STATUS (PMU_GLOBAL) Register
Register Name | ADDR_ERROR_STATUS |
---|---|
Relative Address | 0x0000000010 |
Absolute Address | 0x00FFD80010 (PMU_GLOBAL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Register Address Error; Interrupt Status and Clear. |
Register access requests are handled by the APB interface. When the address does not match an implemented register, the interface optionally asserts the SLVERR signal back on APB and sets an interrupt . The SLVERR error signal is enabled using the Global_Cntrl [SLVERR_Enable] bit. The IRQ signal to the interrupt controller is raised when a Status bit reads 1 and its Mask reads 0. The Mask is controlled by the enable and disable registers.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | roRead-only | 0x0 | reserved |
Status | 0 | wtcReadable, write a 1 to clear | 0x0 | Read. 0: no interrupt. 1: interrupt asserted. Write. 0: no effect. 1: clear bit to 0. |