Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > TX_thres (QSPI) Register

TX_thres (QSPI) Register

TX_thres (QSPI) Register Description

Register NameTX_thres
Relative Address0x0000000028
Absolute Address 0x00FF0F0028 (QSPI)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionTX FIFO Threshold

TX_thres (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Threshold_of_TX_FIFO31:0rwNormal read/write0x1Defines the level at which the TX FIFO not full interrupt is generated
Note: Change this value only when controller is not communicating with the memory device.