Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > RESET_CTRL (CRL_APB) Register
Register Name | RESET_CTRL |
---|---|
Relative Address | 0x0000000218 |
Absolute Address | 0x00FF5E0218 (CRL_APB) |
Width | 8 |
Type | rwNormal read/write |
Reset Value | 0x00000001 |
Description | PS_SRST_B Pin Control and Trigger. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 7:5 | rwNormal read/write | 0x0 | reserved. |
soft_reset | 4 | rwNormal read/write | 0x0 | Software reset. Cause a system reset to occur. This is the equivalent to asserting the external PS_SRST_B reset signal pin. |
Reserved | 3:2 | rwNormal read/write | 0x0 | reserved. |
Reserved | 1 | rwNormal read/write | 0x0 | reserved. |
srst_dis | 0 | rwNormal read/write | 0x1 | 0: PS_SRST_B reset pin will functional properly. 1: PS_SRST_B reset pin will be disabled. System reset will disable. BootROM will enable. |