Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > isr (IOU_SLCR) Register

isr (IOU_SLCR) Register

isr (IOU_SLCR) Register Description

Register Nameisr
Relative Address0x0000000700
Absolute Address 0x00FF180700 (IOU_SLCR)
Width 1
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionAddress Decode Error Interrupt Status

This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

isr (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0wtcReadable, write a 1 to clear0x0Status for an address decode error interrupt.
0: No Event
1: Event Occurred