Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_VENDOR Module > PLC2 (SATA_AHCI_VENDOR) Register

PLC2 (SATA_AHCI_VENDOR) Register

PLC2 (SATA_AHCI_VENDOR) Register Description

Register NamePLC2
Relative Address0x0000000038
Absolute Address 0x00FD0C00D8 (SATA_AHCI_VENDOR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort LinkCfg2

Controls the configuration of the Link Layer for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.

PLC2 (SATA_AHCI_VENDOR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
OP31:0rwNormal read/write0x0Override Primitive (OP): This 32-bit bus specifies the data to be used in the overriding primitive debug logic, described in the definition of LinkCfg1 above.