Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB12_PMINTENCLR (SMMU500) Register

SMMU_CB12_PMINTENCLR (SMMU500) Register

SMMU_CB12_PMINTENCLR (SMMU500) Register Description

Register NameSMMU_CB12_PMINTENCLR
Relative Address0x000001CF4C
Absolute Address 0x00FD81CF4C (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionProvides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter.

SMMU_CB12_PMINTENCLR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P3 3woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2 2woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1 1woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P0 0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details