Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > ISR (SPI) Register

ISR (SPI) Register

ISR (SPI) Register Description

Register NameISR
Relative Address0x0000000004
Absolute Address 0x00FF040004 (SPI0)
0x00FF050004 (SPI1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000004
DescriptionSPI interrupt status

This register is set when the described event occurs and the interrupt is enabled in the mask register. When any of these bits are set the interrupt output is asserted high. In the default configuration, these bits are all cleared simultaneously by reading this register, though this may be configured for an individual write-one-to-clear scheme.

ISR (SPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:7roRead-only0x0Reserved, read as zero, ignored on write.
TX_FIFO_underflow 6wtcReadable, write a 1 to clear0x0TX FIFO underflow, write one to this bit location to clear.
1: underflow is detected
0: no underflow has been detected
RX_FIFO_full 5wtcReadable, write a 1 to clear0x0RX FIFO full
1: FIFO is full
0: FIFO is not full
RX_FIFO_not_empty 4wtcReadable, write a 1 to clear0x0RX FIFO not empty
1: FIFO has more than or equal to THRESHOLD entries
0: FIFO has less than RX THRESHOLD entries
TX_FIFO_full 3wtcReadable, write a 1 to clear0x0TX FIFO full
1: FIFO is full
0: FIFO is not full
TX_FIFO_not_full 2wtcReadable, write a 1 to clear0x1TX FIFO not full
1: FIFO has less than THRESHOLD entries
0: FIFO has more than or equal toTHRESHOLD entries
MODE_FAIL 1wtcReadable, write a 1 to clear0x0Logic level on n_ss_in pin is inconsistent with the SPI mode.
1: Use if n_ss_in is low in master mode (multi-master contention) or n_ss_in goes high during a transmission in slave mode. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is read.
ModeFail interrupt, write one to this bit location to clear.
1: a mode fault has occurred
0: no mode fault has been detected
RX_OVERFLOW 0wtcReadable, write a 1 to clear0x0Receive Overflow interrupt, write one to this bit location to clear.
1: overflow occured
0: no overflow occurred