Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ADDR_ERROR_STATUS (PMU_GLOBAL) Register

ADDR_ERROR_STATUS (PMU_GLOBAL) Register

ADDR_ERROR_STATUS (PMU_GLOBAL) Register Description

Register NameADDR_ERROR_STATUS
Relative Address0x0000000010
Absolute Address 0x00FFD80010 (PMU_GLOBAL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister Address Error; Interrupt Status and Clear.

Register access requests are handled by the APB interface. When the address does not match an implemented register, the interface optionally asserts the SLVERR signal back on APB and sets an interrupt . The SLVERR error signal is enabled using the Global_Cntrl [SLVERR_Enable] bit. The IRQ signal to the interrupt controller is raised when a Status bit reads 1 and its Mask reads 0. The Mask is controlled by the enable and disable registers.

ADDR_ERROR_STATUS (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0reserved
Status 0wtcReadable, write a 1 to clear0x0Read.
0: no interrupt.
1: interrupt asserted.
Write.
0: no effect.
1: clear bit to 0.