Zynq UltraScale+ Devices Register Reference > Module Summary > DPDMA Module > DPDMA_CH0_DSCR_STRT_ADDR (DPDMA) Register

DPDMA_CH0_DSCR_STRT_ADDR (DPDMA) Register

DPDMA_CH0_DSCR_STRT_ADDR (DPDMA) Register Description

Register NameDPDMA_CH0_DSCR_STRT_ADDR
Relative Address0x0000000204
Absolute Address 0x00FD4C0204 (DPDMA)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDescriptor Start Address Register

DPDMA_CH0_DSCR_STRT_ADDR (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LSB31:0rwNormal read/write0x032 bit start address for first descriptor fetch