Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM0_RESULT1 (VCU_SLCR) Register

APM0_RESULT1 (VCU_SLCR) Register

APM0_RESULT1 (VCU_SLCR) Register Description

Register NameAPM0_RESULT1
Relative Address0x0000000110
Absolute Address 0x00A0040110 (VCU_SLCR)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAPM0_RESULT1

APM0_RESULT1 (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
rd_transac_count31:0roRead-only0x0Number of read transactions happened in configured timing window.