Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DPLL_TO_LPD_CTRL (CRF_APB) Register
Register Name | DPLL_TO_LPD_CTRL |
---|---|
Relative Address | 0x000000004C |
Absolute Address | 0x00FD1A004C (CRF_APB) |
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000400 |
Description | DPLL to LPD Clock Divisor. |
Program divisor for DPLL clock source (in FPD) driven to LPD clock generators. Refer to data sheet for frequency limits.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 15:14 | rwNormal read/write | 0x0 | reserved. |
DIVISOR0 | 13:8 | rwNormal read/write | 0x4 | 6-bit divider. |
Reserved | 7:0 | rwNormal read/write | 0x0 | reserved. |