Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_51 (PCIE_ATTRIB) Register
Register Name | ATTR_51 |
---|---|
Relative Address | 0x00000000CC |
Absolute Address | 0x00FD4800CC (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00004021 |
Description | ATTR_51 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_pm_base_ptr | 15:8 | rwNormal read/write | 0x40 | Byte address of the base of the Power Management (PM) Capability Structure. Any access to this structure (via either the link or the management port) is relative to this address. |
attr_pcie_revision | 7:4 | rwNormal read/write | 0x2 | Not currently in use. Need to correct this definition: 2 specifies PCI Express v2.0 compliance. 1 specifies PCI Express v1.1 compliance. 0 specifies PCI Express v1.0a compliance. 1 should be used. Not acted upon. |
attr_pcie_cap_slot_implemented | 3 | rwNormal read/write | 0x0 | Slot Implemented. When TRUE, indicates that the PCI Express Link associated with this Port is connected to a slot (rather than to an integrated component). Valid only for Root Port of Root Complex and Downstream Port of Switch. Transferred to the PCI Express Capabilities register. |
attr_pcie_cap_rsvd_15_14 | 2:1 | rwNormal read/write | 0x0 | This sets the Reserved bits [15:14] of the PCIE Capability register. These should only be set to 0. |
attr_pcie_cap_on | 0 | rwNormal read/write | 0x1 | Indicates that the PCIE structures exists. If this is FALSE, then the PCIE structure cannot be accessed via either the link or the management port. |