Zynq UltraScale+ Devices Register Reference > Module Summary > IPI Module > PL_1_ISR (IPI) Register

PL_1_ISR (IPI) Register

PL_1_ISR (IPI) Register Description

Register NamePL_1_ISR
Relative Address0x0000050010
Absolute Address 0x00FF350010 (IPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionCh 8 Interrupt Status and Clear (receiver). Default PL 1.

Read this register along with the mask register to determine which interrupt sender(s) caused the IPI interrupt. READ: 0: inactive. 1: active. WRITE: 0: no effect. 1: clears this bit. Note: If a Status bit is 1 and its mask is 0, then the IRQ signal is asserted to the interrupt controllers. Note: These bit values can be read by the sender using the senders observation register. Beware that this does not provide the sender with the state of the receivers mask register.

PL_1_ISR (IPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28roRead-only0x0reserved
PL_327wtcReadable, write a 1 to clear0x0Ch 10. Default to PL IPI3.
PL_226wtcReadable, write a 1 to clear0x0Ch 9. Default to PL IPI2.
PL_125wtcReadable, write a 1 to clear0x0Ch 8. Default to PL IPI1.
PL_024wtcReadable, write a 1 to clear0x0Ch 7. Default to PL IPI0.
Reserved23:20roRead-only0x0reserved
PMU_319wtcReadable, write a 1 to clear0x0Ch 6: PMU IPI3.
PMU_218wtcReadable, write a 1 to clear0x0Ch 5: PMU IPI2.
PMU_117wtcReadable, write a 1 to clear0x0Ch 4: PMU IPI1.
PMU_016wtcReadable, write a 1 to clear0x0Ch 3: PMU IPI0.
Reserved15:10roRead-only0x0reserved
RPU_1 9wtcReadable, write a 1 to clear0x0Ch 2. Default to RPU1.
RPU_0 8wtcReadable, write a 1 to clear0x0Ch 1. Default to RPU0.
Reserved 7:1roRead-only0x0reserved
APU 0wtcReadable, write a 1 to clear0x0Ch 0. Default to APU MPCore.