Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CIDR1 (SMMU500) Register

SMMU_CIDR1 (SMMU500) Register

SMMU_CIDR1 (SMMU500) Register Description

Register NameSMMU_CIDR1
Relative Address0x0000000FF4
Absolute Address 0x00FD800FF4 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x000000F0
DescriptionComponent Identification register 1

SMMU_CIDR1 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PREAMBLE 7:0roRead-only0xF0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details