Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_PLIST_CONFIG (GPU) Register
Register Name | PP0_PLIST_CONFIG |
---|---|
Relative Address | 0x0000008050 |
Absolute Address | 0x00FD4B8050 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Polygon List Format Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:30 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
LIST_FORMAT | 29:28 | rwNormal read/write | 0x0 | The polygon list format is as follows: 0: Legacy format, 1x1 tile coverage = default 1: 2x2 supertiling 2: 4x4 supertiling 3: undefined |
_ | 27:22 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
SCALE_Y | 21:16 | rwNormal read/write | 0x0 | Log2 of the number of tiles in the y direction for a supertile. |
Reserved | 15:6 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
SCALE_X | 5:0 | rwNormal read/write | 0x0 | Log2 of the number of tiles in the x direction for a supertile. |