Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ERROR_SIG_MASK_1 (PMU_GLOBAL) Register

ERROR_SIG_MASK_1 (PMU_GLOBAL) Register

ERROR_SIG_MASK_1 (PMU_GLOBAL) Register Description

Register NameERROR_SIG_MASK_1
Relative Address0x0000000580
Absolute Address 0x00FFD80580 (PMU_GLOBAL)
Width32
TyperoRead-only
Reset Value0x000000C3
DescriptionSystem Errors to PL; Interrupt Mask, Reg 1.

0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only. For details on the bit fields, refer to the ERROR_STATUS_1 register description. Register is reset only by the PS_POR_B reset signal pin.

ERROR_SIG_MASK_1 (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31roRead-only0x0reserved.
Reserved30roRead-only0x0reserved.
Reserved29roRead-only0x0reserved.
Reserved28roRead-only0x0reserved.
CSU_SWDT27roRead-only0x0CSU_SWDT timeout.
CLK_MON26roRead-only0x0Clock Monitor (ClkMon).
XMPU25:24roRead-only0x0XMPU and XPPU error signals.
PWR_SUPPLY23:16roRead-only0x0Eight (8) PS VCC and VCCO power supplies.
Reserved15:14roRead-only0x0reserved
FPD_SWDT13roRead-only0x0FPD_SWDT timeout.
LPD_SWDT12roRead-only0x0LPD_SWDT timeout.
Reserved11:10roRead-only0x0reserved
RPU_CCF 9roRead-only0x0RPU common cause failures.
Reserved 8roRead-only0x0reserved
RPU_LS 7:6roRead-only0x3RPU lockstep error.
FPD_TEMP 5roRead-only0x0FPD over tempurature alarm.
LPD_TEMP 4roRead-only0x0LPD over tempurature alarm.
RPU1 3roRead-only0x0RPU1 RAM (all ECC errors).
RPU0 2roRead-only0x0RPU0 RAM (all ECC errors).
OCM_ECC 1roRead-only0x1OCM (uncorrectable only).
DDR_ECC 0roRead-only0x1DDR (uncorrectable only).