Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > QSPI_DATA_DLY_ADJ (QSPI) Register

QSPI_DATA_DLY_ADJ (QSPI) Register

QSPI_DATA_DLY_ADJ (QSPI) Register Description

Register NameQSPI_DATA_DLY_ADJ
Relative Address0x00000001F8
Absolute Address 0x00FF0F01F8 (QSPI)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionQSPI RX Data Delay

QSPI RX Data Delay Register Register for adjusting the internal receive data delay for read data capturing. This feature is only active when [USE_LPBK] is active and Flash clock is around 100MHz

QSPI_DATA_DLY_ADJ (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
USE_DATA_DLY31rwNormal read/write0x0Enable using delay elements in receive data path
0: Disable data delay
1: Enable
data delay
Note: Change this value only when controller is not communicating with the memory device.
DATA_DLY_ADJ30:28rwNormal read/write0x0Delay adjustment value
Note: Change this value only when controller is not communicating with the memory device.
Reserved27:0rwNormal read/write0x0reserved