Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > MR7 (DDR_PHY) Register
Register Name | MR7 |
---|---|
Relative Address | 0x000000019C |
Absolute Address | 0x00FD08019C (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | LPDDR4 Mode Register 7 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
RSVD | 7:0 | rwNormal read/write | 0x0 | These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. |
Alternate Register MR7_DDR3, reset=0x0
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD_15_0 Offset=0 Width=16 read-write
[[*]] Description: Reserve for future use.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.