Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > HETER (STM) Register
Register Name | HETER |
---|---|
Relative Address | 0x0000000D20 |
Absolute Address | 0x00FE9C0D20 (CORESIGHT_SOC_STM) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Enable Trigger Generation on Hardware Events. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
HETE | 31:0 | rwNormal read/write | 0 | Bit mask to enable trigger generation from the hardware events, with one bit per hardware event.0 = disabled1 = enabled |