Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > ACPU_CTRL (CRF_APB) Register

ACPU_CTRL (CRF_APB) Register

ACPU_CTRL (CRF_APB) Register Description

Register NameACPU_CTRL
Relative Address0x0000000060
Absolute Address 0x00FD1A0060 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x03000400
DescriptionAPU MPCore Clock Generator Control.

Register is write protected by crf_apb.crf_wprot [active].

ACPU_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28rwNormal read/write0x0reserved.
Reserved27rwNormal read/write0x0reserved.
Reserved26rwNormal read/write0x0reserved.
CLKACT_HALF25rwNormal read/write0x1Clock active control for half-speed APU Clock.
0: disable. Clock stop.
1: enable.
CLKACT_FULL24rwNormal read/write0x1Clock active control for full-speed APU Clock.
0: disable. Clock stop.
1: enable.
Reserved23:14rwNormal read/write0x0reserved.
DIVISOR013:8rwNormal read/write0x46-bit divider.
Reserved 7:3rwNormal read/write0x0reserved.
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: APLL
010: DPLL
011: VPLL