Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PIDR7 (SMMU500) Register
Register Name | SMMU_PIDR7 |
---|---|
Relative Address | 0x0000000FDC |
Absolute Address | 0x00FD800FDC (SMMU_GPV) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Peripheral Identificaation register 7 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
_ | 31:0 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |