Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > Config (SPI) Register
Register Name | Config |
---|---|
Relative Address | 0x0000000000 |
Absolute Address |
0x00FF040000 (SPI0) 0x00FF050000 (SPI1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00020000 |
Description | SPI configuration |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:18 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
Modefail_gen_en | 17 | rwNormal read/write | 0x1 | ModeFail Generation Enable 1: enable 0: disable Change only when controller is not actively transmitting or receiving data. |
Man_start_com | 16 | woWrite-only | 0x0 | Manual Start Command 1: start transmission of data 0: don't care Change only when controller is not actively transmitting or receiving data. |
Man_start_en | 15 | rwNormal read/write | 0x0 | Manual Start Enable 1: enables manual start 0: auto mode Change only when controller is not actively transmitting or receiving data. |
Manual_CS | 14 | rwNormal read/write | 0x0 | Manual CS 1: manual CS mode 0: auto mode Change only when controller is not actively transmitting or receiving data. |
CS | 13:10 | rwNormal read/write | 0x0 | Peripheral chip select lines. xxx0: slave 0 selected xx01: slave 1 selected x011: slave 2 selected 0111: reserved 1111: No slave selected Change only when controller is not actively transmitting or receiving data. |
PERI_SEL | 9 | rwNormal read/write | 0x0 | Peripheral select decode 1: allow external 3-to-8 decode 0: only 1 of 3 selects Change only when controller is not actively transmitting or receiving data. |
REF_CLK | 8 | rwNormal read/write | 0x0 | Master reference clock select 1: not supported 0: use SPI REFERENCE CLOCK |
Reserved | 7:6 | rwNormal read/write | 0x0 | Reserved, read as zero, write with 00 |
BAUD_RATE_DIV | 5:3 | rwNormal read/write | 0x0 | Master mode baud rate divisor controls the amount the SPI_REF_CLK is divided for the controller. 000: reserved 001: divide by 4 010: divide by 8 011: divide by 16 100: divide by 32 101: divide by 64 110: divide by 128 111: divide by 256 Change only when controller is not actively transmitting or receiving data. |
CLK_PH | 2 | rwNormal read/write | 0x0 | Clock phase 1: the SPI clock is inactive outside the word 0: the SPI clock is active outside the word Change only when controller is not actively transmitting or receiving data. |
CLK_POL | 1 | rwNormal read/write | 0x0 | Clock polarity outside SPI word 1: the SPI clock is quiescent high 0: the SPI clock is quiescent low Change only when controller is not actively transmitting or receiving data. |
MODE_SEL | 0 | rwNormal read/write | 0x0 | Mode select 1: the SPI is in master mode 0: the SPI is in slave mode Change only when controller is not actively transmitting or receiving data. |