Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_77 (PCIE_ATTRIB) Register

ATTR_77 (PCIE_ATTRIB) Register

ATTR_77 (PCIE_ATTRIB) Register Description

Register NameATTR_77
Relative Address0x0000000134
Absolute Address 0x00FD480134 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionATTR_77

This register should only be written to during reset of the PCIe block

ATTR_77 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_rbar_cap_control_encodedbar112:8rwNormal read/write0x0Initial value for the 2nd RBAR Control "BAR Size" field (if any). Encoding is 0=1MB, 1=2MB,2=4MB,etc. This value must correspond to the size requested in the attribute BARx (where x is the value of RBAR_CAP_INDEX1). For instance, if RBAR_CAP_INDEX1=3, and BAR3 requests a 16MB aperture, then this attribute must be set to 4 (meaning 16MB).
attr_rbar_cap_control_encodedbar0 7:3rwNormal read/write0x0Initial value for the 1st RBAR Control "BAR Size" field (if any). Encoding is 0=1MB, 1=2MB,2=4MB,etc. This value must correspond to the size requested in the attribute BARx (where x is the value of RBAR_CAP_INDEX0). For instance, if RBAR_CAP_INDEX0=3, and BAR3 requests a 16MB aperture, then this attribute must be set to 4 (meaning 16MB).
attr_rbar_cap_index5 2:0rwNormal read/write0x0BAR Index value for Resizable BAR Control Register(5). Set to 0 if 5 or fewer BARs can be resized. This value should not be lower than the value on RBAR_CAP_INDEX0,1,2,3,4.