Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > csu_dma_reset (CSU) Register

csu_dma_reset (CSU) Register

csu_dma_reset (CSU) Register Description

Register Namecsu_dma_reset
Relative Address0x000000000C
Absolute Address 0x00FFCA000C (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCSU DMA Reset

csu_dma_reset (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
reset 0rwNormal read/write0x0Asserts reset to the CSU DMA when set. The DMA will remain in reset until this bit is unset.