Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_IOMODULE Module > PIT1_CONTROL (PMU_IOMODULE) Register

PIT1_CONTROL (PMU_IOMODULE) Register

PIT1_CONTROL (PMU_IOMODULE) Register Description

Register NamePIT1_CONTROL
Relative Address0x0000000058
Absolute Address 0x00FFD40058 (PMU_IOMODULE)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPIT1 Control Register

The EN bit in this register enables/disables counting. The PRELOAD bit determines if the counting is continuous with automatic reload of the PIT1_PRELOAD value when lapsing (PIT1_COUNTER = 0) or if the counting is stopped after counting the number of cycles defined in PIT1_PRELOAD.

PIT1_CONTROL (PMU_IOMODULE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0reserved
PRELOAD 1woWrite-only0x00 = Counter counts PIT1_PRELOAD value cycles and then stops
1 = Counter value is automatically reloaded with the PIT1_PRELOAD value when counter lapses
EN 0woWrite-only0x00 = Counter Disabled
1 = Counter Enabled