Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > PORTLI_20 (USB3_XHCI) Register

PORTLI_20 (USB3_XHCI) Register

PORTLI_20 (USB3_XHCI) Register Description

Register NamePORTLI_20
Relative Address0x0000000428
Absolute Address 0x00FE200428 (USB3_0_XHCI)
0x00FE300428 (USB3_1_XHCI)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPort Link Info Register
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.

PORTLI_20 (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved
Reserved15:0roRead-only0x0Reserved
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.