Zynq UltraScale+ Devices Register Reference > Module Summary > AFIFM Module > I_STS (AFIFM) Register

I_STS (AFIFM) Register

I_STS (AFIFM) Register Description

Register NameI_STS
Relative Address0x0000000E00
Absolute Address 0x00FD360E00 (AFIFM0)
0x00FD370E00 (AFIFM1)
0x00FD380E00 (AFIFM2)
0x00FD390E00 (AFIFM3)
0x00FD3A0E00 (AFIFM4)
0x00FD3B0E00 (AFIFM5)
0x00FF9B0E00 (AFIFM6)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Status Register

This register holds the contents of the raw, pre-masked interrupt status bit. Even if a mask bit is set, S/W could still read this sticky bit to see if any event actually occurred. This register requires a specific write=1 to clear its contents. Writes=0 are ignored.

I_STS (AFIFM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
INVALID_APB 0wtcReadable, write a 1 to clear0x0Indicates that an APB (register) access has occured to an unimplemented space (there is no register at that location).