Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > GP_CONTR_REG_CMD (GPU) Register

GP_CONTR_REG_CMD (GPU) Register

GP_CONTR_REG_CMD (GPU) Register Description

Register NameGP_CONTR_REG_CMD
Relative Address0x0000000020
Absolute Address 0x00FD4B0020 (GPU)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionGP Control Register Command

GP_CONTR_REG_CMD (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:12woWrite-only0x0Reserved, write as zero, read undefined
GP_CMD_CLK_OVERRIDE11woWrite-only0x0Disable block level clock gates. Writing a 1 to this bit overrides all the
architectural clock gates in the design so all clocks are always active
GP_CMD_SOFT_RESET10woWrite-only0x0Waits until all outstanding bus-transfers are completed, then resets the
internal state of GP. Use the GP_IRQ_RESET_COMPLETED
interrupt bit to discover when the reset has actually completed
GP_CMD_STOP_BUS 9woWrite-only0x0Stop data bus.
GP_CMD_START_BUS 8woWrite-only0x0Start data bus.
Reserved 7woWrite-only0x0Reserved, write as zero, read undefined.
GP_CMD_FORCE_HANG 6woWrite-only0x0Force hang. This functionality depends on the watchdog timer
GP_CMD_FORCE_RESET 5woWrite-only0x0Resets the internal state of GP immediately.
If GP_CMD_FORCE_RESET is asserted while there is a bus
transaction in progress the AXI interconnect might operate at reduced
efficiency or lockup.
To ensure a safe reset:
1. Write 1 to GP_CMD_STOP_BUS.
2. Wait until all transactions have completed. The
GP_IRQ_AXI_BUS_STOPPED interrupt is asserted when the
bus is idle.
3. Write 1 to GP_CMD_FORCE_RESET.
The use of GP_CMD_FORCE_RESET must be deprecated, unless
you require backwards compatibility with Mali-200.
GP_CMD_UPDATE_PLB_ALLOC 4woWrite-only0x0Update polygon list allocation addresses.
Reserved 3:2woWrite-only0x0Reserved, write as zero, read undefined.
GP_CMD_START_PLB 1woWrite-only0x0Start PLB.
GP_CMD_START_VS 0woWrite-only0x0Start vertex shader.