Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > RP_CTRL (PCIE_ATTRIB) Register
Register Name | RP_CTRL |
---|---|
Relative Address | 0x0000000234 |
Absolute Address | 0x00FD480234 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | PL Root Port Mode Control Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
pl_downstream_deemph_source | 1 | rwNormal read/write | 0x0 | Enables the Root Port to control de-emphasis used on the link at 5.0 Gb/s speeds. 0b - Use Upstream link partner preferred de-emphasis. 1b - Use Selectable de-emphasis value from Link Control 2 register. |
pl_transmit_hot_rst | 0 | rwNormal read/write | 0x0 | Active-High signal to direct the PCI ExpressRoot Port to transmit an In-Band Hot Reset |