Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_MST_TRI1 (IOU_SLCR) Register

MIO_MST_TRI1 (IOU_SLCR) Register

MIO_MST_TRI1 (IOU_SLCR) Register Description

Register NameMIO_MST_TRI1
Relative Address0x0000000208
Absolute Address 0x00FF180208 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0xFFFFFFFF
DescriptionMIO pin Tri-state Enables, 63:32

Parallel access to the master tri-state enables for MIO pins

MIO_MST_TRI1 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PIN_63_TRI31rwNormal read/write0x1Master Tri-state Enable for pin 63, active high
PIN_62_TRI30rwNormal read/write0x1Master Tri-state Enable for pin 62, active high
PIN_61_TRI29rwNormal read/write0x1Master Tri-state Enable for pin 61, active high
PIN_60_TRI28rwNormal read/write0x1Master Tri-state Enable for pin 60, active high
PIN_59_TRI27rwNormal read/write0x1Master Tri-state Enable for pin 59, active high
PIN_58_TRI26rwNormal read/write0x1Master Tri-state Enable for pin 58, active high
PIN_57_TRI25rwNormal read/write0x1Master Tri-state Enable for pin 57, active high
PIN_56_TRI24rwNormal read/write0x1Master Tri-state Enable for pin 56, active high
PIN_55_TRI23rwNormal read/write0x1Master Tri-state Enable for pin 55, active high
PIN_54_TRI22rwNormal read/write0x1Master Tri-state Enable for pin 54, active high
PIN_53_TRI21rwNormal read/write0x1Master Tri-state Enable for pin 53, active high
PIN_52_TRI20rwNormal read/write0x1Master Tri-state Enable for pin 52, active high
PIN_51_TRI19rwNormal read/write0x1Master Tri-state Enable for pin 51, active high
PIN_50_TRI18rwNormal read/write0x1Master Tri-state Enable for pin 50, active high
PIN_49_TRI17rwNormal read/write0x1Master Tri-state Enable for pin 49, active high
PIN_48_TRI16rwNormal read/write0x1Master Tri-state Enable for pin 48, active high
PIN_47_TRI15rwNormal read/write0x1Master Tri-state Enable for pin 47, active high
PIN_46_TRI14rwNormal read/write0x1Master Tri-state Enable for pin 46, active high
PIN_45_TRI13rwNormal read/write0x1Master Tri-state Enable for pin 45, active high
PIN_44_TRI12rwNormal read/write0x1Master Tri-state Enable for pin 44, active high
PIN_43_TRI11rwNormal read/write0x1Master Tri-state Enable for pin 43, active high
PIN_42_TRI10rwNormal read/write0x1Master Tri-state Enable for pin 42, active high
PIN_41_TRI 9rwNormal read/write0x1Master Tri-state Enable for pin 41, active high
PIN_40_TRI 8rwNormal read/write0x1Master Tri-state Enable for pin 40, active high
PIN_39_TRI 7rwNormal read/write0x1Master Tri-state Enable for pin 39, active high
PIN_38_TRI 6rwNormal read/write0x1Master Tri-state Enable for pin 38, active high
PIN_37_TRI 5rwNormal read/write0x1Master Tri-state Enable for pin 37, active high
PIN_36_TRI 4rwNormal read/write0x1Master Tri-state Enable for pin 36, active high
PIN_35_TRI 3rwNormal read/write0x1Master Tri-state Enable for pin 35, active high
PIN_34_TRI 2rwNormal read/write0x1Master Tri-state Enable for pin 34, active high
PIN_33_TRI 1rwNormal read/write0x1Master Tri-state Enable for pin 33, active high
PIN_32_TRI 0rwNormal read/write0x1Master Tri-state Enable for pin 32, active high