Zynq UltraScale+ Devices Register Reference > Module Summary > XMPU_OCM Module > LOCK (XMPU_OCM) Register

LOCK (XMPU_OCM) Register

LOCK (XMPU_OCM) Register Description

Register NameLOCK
Relative Address0x0000000020
Absolute Address 0x00FFA70020 (OCM_XMPU_CFG)
Width 1
TyperwNormal read/write
Reset Value0x00000000
DescriptionRegister Write Lock.

All register writes must be done by a secure bus master as defined by TrustZone. The write lock prevents the secure master from writing to all registers except the status registers: ISR, IMR, IEN and IDS. Note: all XMPU registers are readable by secure bus masters. Note: regardless of the LOCK [RegWrDis] setting, the status registers are always writeable by secure and non-secure bus masters.

LOCK (XMPU_OCM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RegWrDis 0rwNormal read/write0x0Register Write Disable. Applies to all registers except ISR, IMR, IEN and IDS.
0: read/write allowed.
1: read-only.
Once this bit is set, it can only be cleared by an OCM_XMPU reset.