Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM0_TIMER (VCU_SLCR) Register

APM0_TIMER (VCU_SLCR) Register

APM0_TIMER (VCU_SLCR) Register Description

Register NameAPM0_TIMER
Relative Address0x0000000104
Absolute Address 0x00A0040104 (VCU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAPM0_TIMER

APM0_TIMER (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
burst_max_val31:0rwNormal read/write0x0Maximum value of clock ticks in timing mode window in case of Mode 2. This is number of
AXI clock cycles. Timing window counter will restart once it attains the maximum value. A new timing window start after that.