Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > PGCR2 (DDR_PHY) Register
Register Name | PGCR2 |
---|---|
Relative Address | 0x0000000018 |
Absolute Address | 0x00FD080018 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00F12480 |
Description | PHY General Configuration Register 2 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CLRTSTAT | 31 | wtcReadable, write a 1 to clear | 0x0 | Clear Training Status Registers: A write of 1b1 to this bit will reset the error and done status bits for all training blocks (CA training, QS gate training, WL training, WLA training, read bit deskew, read eye centering, write bit deskew, write eye centering). This bit is self clearing. |
CLRZCAL | 30 | wtcReadable, write a 1 to clear | 0x0 | Clear Impedance Calibration: A write of 1b1 to this bit will reset the impedance calibration FSM and clear the ZQnSR error/done status bits ZQnSR[9:0]. Also, it will clear ZQnSR.ZERR and PGSR0.ZCERR. This bit is self clearing. |
CLRPERR | 29 | wtcReadable, write a 1 to clear | 0x0 | Clear Parity Error: A write of 1b1 to this bit will clear the PGSR1[31] PARERR. This bit is self clearing. |
ICPC | 28 | rwNormal read/write | 0x0 | Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are: 1b0 = Asserted after PHY initialization (PLL locking and impedance calibration) if enabled is complete. 1b1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization and data training) if enabled is complete. |
DTPMXTMR | 27:20 | rwNormal read/write | 0xF | Data Training PUB Mode Exit Timer: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. |
INITFSMBYP | 19 | rwNormal read/write | 0x0 | Initialization Bypass: Forces, if set, the Initialization FSMs to the DONE state. To be used for debug purposes only. This bit is not self- clearing so it must be cleared before triggering any operation in the PIR. |
PLLFSMBYP | 18 | rwNormal read/write | 0x0 | PLL FSM Bypass: Forces, if set, the PLL FSM to the DONE state. To be used for debug purposes only. This bit is not self-clearing so it must be cleared before triggering any operation in the PIR. Set this bit to 1'b1 when PLL is in bypass mode. |
tREFPRD | 17:0 | rwNormal read/write | 0x12480 | Refresh Period: Indicates the period in clock cycles after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further number of clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. In DDR3 and LPDDR3 mode, 400 clocks needs to subtracted In DDR4 and LPDDR4 mode, 800 clocks needs to subtracted In DDR3 and LPDDR3 mode, (DTCR.RFSHDT * tREFI)/tCK - 400 In DDR4 and LPDDR4 mode, (DTCR.RFSHDT * tREFI)/tCK - 800 |