Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > PIDR1 (TSGEN) Register
Register Name | PIDR1 |
---|---|
Relative Address | 0x0000000FE4 |
Absolute Address | 0x00FE900FE4 (CORESIGHT_SOC_TSGEN) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x000000B1 |
Description | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DES_0 | 7:4 | roRead-only | 0xB | Bits [3:0] of the JEDEC identity code indicating the designer of the component, together with the continuation code. |
PART_1 | 3:0 | roRead-only | 0x1 | Bits [11:8] of the component part number. This is selected by the designer of the component. |