Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > CIDR2 (TSGEN) Register

CIDR2 (TSGEN) Register

CIDR2 (TSGEN) Register Description

Register NameCIDR2
Relative Address0x0000000FF8
Absolute Address 0x00FE900FF8 (CORESIGHT_SOC_TSGEN)
Width32
TyperoRead-only
Reset Value0x00000005
DescriptionA component identification register, that indicates that the identification registers are present.

CIDR2 (TSGEN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PRMBL_2 7:0roRead-only0x5Contains bits[23:16] of the component identification code.