Zynq UltraScale+ Devices Register Reference > Module Summary > GEM Module > tsu_timer_nsec (GEM) Register

tsu_timer_nsec (GEM) Register

tsu_timer_nsec (GEM) Register Description

Register Nametsu_timer_nsec
Relative Address0x00000001D4
Absolute Address 0x00FF0B01D4 (GEM0)
0x00FF0C01D4 (GEM1)
0x00FF0D01D4 (GEM2)
0x00FF0E01D4 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
Description1588 Timer Nanoseconds Register

tsu_timer_nsec (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Reserved, read as 0, ignored on write.
timer29:0rwNormal read/write0x0Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero and a write to the timer adjust register causes a decrement the seconds register will be decremented if necessary and the nanoseconds register will roll back to 9999999xx(dec)).