Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB12_PMEVTYPER0 (SMMU500) Register

SMMU_CB12_PMEVTYPER0 (SMMU500) Register

SMMU_CB12_PMEVTYPER0 (SMMU500) Register Description

Register NameSMMU_CB12_PMEVTYPER0
Relative Address0x000001CE80
Absolute Address 0x00FD81CE80 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter

SMMU_CB12_PMEVTYPER0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P31rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
U30rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSP29rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSU28rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EVENT 4:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details