Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > PIDR1 (TSGEN) Register

PIDR1 (TSGEN) Register

PIDR1 (TSGEN) Register Description

Register NamePIDR1
Relative Address0x0000000FE4
Absolute Address 0x00FE900FE4 (CORESIGHT_SOC_TSGEN)
Width32
TyperoRead-only
Reset Value0x000000B1
DescriptionPart of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity.

PIDR1 (TSGEN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DES_0 7:4roRead-only0xBBits [3:0] of the JEDEC identity code indicating the designer of the component, together with the continuation code.
PART_1 3:0roRead-only0x1Bits [11:8] of the component part number. This is selected by the designer of the component.