Zynq UltraScale+ Devices Register Reference > Module Summary > RPU Module > RPU_GLBL_CNTL (RPU) Register

RPU_GLBL_CNTL (RPU) Register

RPU_GLBL_CNTL (RPU) Register Description

Register NameRPU_GLBL_CNTL
Relative Address0x0000000000
Absolute Address 0x00FF9A0000 (RPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000050
DescriptionGlobal Control Regiter for RPU

RPU_GLBL_CNTL (RPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11razRead as zero0x0Reserved for future use
GIC_AXPROT10rwNormal read/write0x0GIC access security setting. This bit is equivalent to AxPROT[1] on AXI bus.
0: All RPU transactions to GIC are secure (reset default).
1: All RPU transactions to GIC are non-secure.
Note: The RPU does not toggle the TZ bit.
Reserved 9razRead as zero0x0Reserved for future use
TCM_CLK_CNTL 8rwNormal read/write0x0TCM clock disable (all TCMs, both RPU processors):
0: TCMs are clocked (reset default).
1: TCM clocks are stopped (gated off)
TCM_WAIT 7rwNormal read/write0x0Insert Wait states in TCM access:
0: Disable (no wait state inserted, reset default)
1: Enable (insert single cycle wait on every TCM access: ATCM , B0TCM, and B1TCM)
TCM_COMB 6rwNormal read/write0x1Combine TCMs of RPU0 and RPU1:
0: Disable (128KB TCMs are visible to each RPU)
1: Enable (256KB TCM is visible to RPU0, reset default)
TEINIT 5rwNormal read/write0x0Select exception handling state:
0: Arm (reset default)
1: Thumb
SLCLAMP 4rwNormal read/write0x1Output clamps for redundant processor:
0: Disable
1: Enable (required for lock-step mode, reset default)
SLSPLIT 3rwNormal read/write0x0Processor Mode:
0: Lock-step mode (Safety mode, reset default).
1: Dual, split mode (Performance Mode).
DBGNOCLKSTOP 2rwNormal read/write0x0Clock control when entering standby:
0: clocks are stopped in standby mode (reset default).
1: clocks continue in standby mode (does not assert nCLKSTOPPEDm).
CFGIE 1rwNormal read/write0x0Instruction fetch endianess:
0: Little-endian (reset default)
1: Big-endian
CFGEE 0rwNormal read/write0x0Data endianness during exception handling:
0: Little-endian (reset default).
1: Big-endian.