Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > IR_MASK (CRL_APB) Register

IR_MASK (CRL_APB) Register

IR_MASK (CRL_APB) Register Description

Register NameIR_MASK
Relative Address0x0000000008
Absolute Address 0x00FF5E0008 (CRL_APB)
Width 1
TyperoRead-only
Reset Value0x00000001
DescriptionInterrupt Mask.

Read-only. 0: enabled. 1: masked (disabled IRQ). If an IR_STATUS bit = 1 (asserted interrupt) and the IR_MASK bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Modify the mask bits using the enable and disable registers.

IR_MASK (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0roRead-only0x1Register Access Error on APB.