Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > GDBGEPINFO1 (USB3_XHCI) Register

GDBGEPINFO1 (USB3_XHCI) Register

GDBGEPINFO1 (USB3_XHCI) Register Description

Register NameGDBGEPINFO1
Relative Address0x000000C17C
Absolute Address 0x00FE20C17C (USB3_0_XHCI)
0x00FE30C17C (USB3_1_XHCI)
Width32
TyperoRead-only
Reset Value0x00800000
DescriptionGlobal Debug Endpoint Information Register 1
This register is for internal use only.
If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined).
Bit Bash test should not be done on this debug register.

GDBGEPINFO1 (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EPDEBUG31:0roRead-only0x800000Endpoint Debug Information, bits[63:32]