Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_transfermode (SDIO) Register
Register Name | reg_transfermode |
---|---|
Relative Address | 0x000000000C |
Absolute Address |
0x00FF16000C (SD0) 0x00FF17000C (SD1) |
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Control the Data Transfer Operations. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
xfermode_multiblksel | 5 | rwNormal read/write | 0x0 | This bit enables multiple block data transfers. 0 Single Block. 1 Multiple Block. |
xfermode_dataxferdir | 4 | rwNormal read/write | 0x0 | This bit defines the direction of data transfers. 0: Write from Host to Card. 1: Read from Card to Host. |
xfermode_autocmdena | 3:2 | rwNormal read/write | 0x0 | Auto command function enables. 00: Auto Command Disabled. 01: Auto CMD12 Enabled. 10: Auto CMD23 Enabled. 11: reserved. There are two methods to stop multiple-block read and write operation. (1) Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. The controller issues CMD12 automatically when the last block transfer is completed. Auto CMD12 error is indicated in the Auto CMD Error Status register. The driver shall not set this bit if the command does not require Auto CMD12. (2) Auto CMD23 Enable: The controller issues an Auto CMD23 before issuing a command specified in the Command Register. The following conditions are required to use the Auto CMD23. * Auto CMD23 Supported (Host Controller Version is 3.00 or later). * A memory card that supports CMD23 (SCR[33]=1). * If DMA is used, it shall be ADMA. * Only when CMD18 or CMD25 is issued. By writing the Command register, the controller issues a CMD23 first and then issues a command specified by the Command Index in Command register 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register. |
xfermode_blkcntena | 1 | rwNormal read/write | 0x0 | Block Count Register Enable. 0: disable (setting is also useful for executing an infinite transfer). 1: enable. Applicable to multiple block transfers. |
xfermode_dmaenable | 0 | rwNormal read/write | 0x0 | DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin when the Host Driver writes to the upper byte of Command register (00Fh). 0: disable DMA. 1: enable DMA. |