Zynq UltraScale+ Devices Register Reference > Module Summary > A53_CTI_3 Module > ASICCTL (A53_CTI_3) Register

ASICCTL (A53_CTI_3) Register

ASICCTL (A53_CTI_3) Register Description

Register NameASICCTL
Relative Address0x0000000144
Absolute Address 0x00FEF20144 (CORESIGHT_A53_CTI_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionImplementation-defined ASIC control, value written to the register is output on asicctl[7:0].

ASICCTL (A53_CTI_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ASICCTL 7:0rwNormal read/write0x0Implementation-defined ASIC control, value written to the register is output on asicctl[7:0].If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the Device ID Register. This is done within a Verilog define EXTMUXNUM.