Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > jtag_sec (CSU) Register

jtag_sec (CSU) Register

jtag_sec (CSU) Register Description

Register Namejtag_sec
Relative Address0x0000000038
Absolute Address 0x00FFCA0038 (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionJTAG Security Gates

jtag_sec (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved14:12rwNormal read/write0x0reserved.
Reserved11:9rwNormal read/write0x0reserved.
ssss_pmu_sec 8:6rwNormal read/write0x0Setting these bits disables the security gate for the PMU MDM and allows the PS TAP to connect to the PMU. All bits must be set to 1 for the security gate to be released. (POR reset only)
ssss_pltap_sec 5:3rwNormal read/write0x0Setting these bits disables the security gate for the PLTAP and allows the PSTAP to connect to the PL for bitstream loading and boundary scan operations. All bits must be set to 1 to release the security gate. (POR reset only)
ssss_dap_sec 2:0rwNormal read/write0x0Setting these bits disables the security gate for the Arm DAP and allows the PS TAP or PJTAG to connect to the DAP. All bits must be set to 1 for the security gate to be released. (POR reset only)