Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > CHKR2_CLKA_UPPER (CRL_APB) Register

CHKR2_CLKA_UPPER (CRL_APB) Register

CHKR2_CLKA_UPPER (CRL_APB) Register Description

Register NameCHKR2_CLKA_UPPER
Relative Address0x0000000180
Absolute Address 0x00FF5E0180 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionUpper Clock Comparison Threshold.

CHKR2_CLKA_UPPER (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
thrshld31:0rwNormal read/write0x0Upper Threshold. This must be set up before a start bit is set (there is no clock crossing from this bus to the comparison logic.)