Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > enable_component_id_0 (PL390) Register

enable_component_id_0 (PL390) Register

enable_component_id_0 (PL390) Register Description

Register Nameenable_component_id_0
Relative Address0x0000000FF0
Absolute Address 0x00F9000FF0 (RCPU_GIC)
Width 8
TyperoRead-only
Reset Value0x0000000D
DescriptionThe component_id_[3:0] Registers are four eight-bit wide registers,
that can conceptually be treated as a single register that holds a
32-bit PrimeCell ID value.

enable_component_id_0 (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
component_id_0 7:0roRead-only0xDThese bits read back as 0x0D.