Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_DMA Module > DMA_CHANNEL_SCRATCH2 (AXIPCIE_DMA) Register
Register Name | DMA_CHANNEL_SCRATCH2 |
---|---|
Relative Address | 0x0000000058 |
Absolute Address |
0x00FD0F0058 (AXIPCIE_DMA0) 0x00FD0F00D8 (AXIPCIE_DMA1) 0x00FD0F0158 (AXIPCIE_DMA2) 0x00FD0F01D8 (AXIPCIE_DMA3) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Scratchpad Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
scratch2 | 31:0 | rwNormal read/write | 0x0 | Scratchpad Register. Intended to enable information to be passed between sofwtare. For example, applications with both an AXI CPU and an PCIe CPU may use this register to pass information between CPUs. The DMA Channel implementation does not use or alter this information. |