Zynq UltraScale+ Devices Register Reference > Module Summary > SIOU Module > IR_DISABLE (SIOU) Register

IR_DISABLE (SIOU) Register

IR_DISABLE (SIOU) Register Description

Register NameIR_DISABLE
Relative Address0x0000000010
Absolute Address 0x00FD3D0010 (SIOU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)

IR_DISABLE (SIOU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0Reserved
addr_decode_err 0woWrite-only0x0Mask for an address decode error interrupt.