Zynq UltraScale+ Devices Register Reference > Module Summary > I2C Module > Control_Reg (I2C) Register
Register Name | Control_Reg |
---|---|
Relative Address | 0x0000000000 |
Absolute Address |
0x00FF020000 (I2C0) 0x00FF030000 (I2C1) |
Width | 16 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Control Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
divisor_a | 15:14 | rwNormal read/write | 0x0 | Divisor for stage A clock divider. 0 - 3: Divides the input APB bus clock frequency by divisor_a + 1. |
divisor_b | 13:8 | rwNormal read/write | 0x0 | Divisor for stage B clock divider. 0 - 63: Divides the output frequency from divisor_a by divisor_b + 1. |
Reserved | 7 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
CLR_FIFO | 6 | rwNormal read/write | 0x0 | 0: no effect. 1: initialize the FIFO to all zeros and clears the transfer size register; self-clearing bit. |
SLVMON | 5 | rwNormal read/write | 0x0 | Slave monitor mode 1 - monitor mode. 0 - normal operation. |
HOLD | 4 | rwNormal read/write | 0x0 | hold_bus 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. |
ACK_EN | 3 | rwNormal read/write | 0x0 | This bit needs to be set to 1 1 - acknowledge enabled, ACK transmitted 0 - acknowledge disabled, NACK transmitted. |
NEA | 2 | rwNormal read/write | 0x0 | Addressing mode: This bit is used in master mode only. 1 - normal (7-bit) address 0 - extended (10-bit) address |
MS | 1 | rwNormal read/write | 0x0 | Overall interface mode: 1 - master 0 - slave |
RW | 0 | rwNormal read/write | 0x0 | Direction of transfer: This bit is used in master mode only. 1 - master receiver 0 - master transmitter. |