Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU Module > MASTER_ID00 (XPPU) Register

MASTER_ID00 (XPPU) Register

MASTER_ID00 (XPPU) Register Description

Register NameMASTER_ID00
Relative Address0x0000000100
Absolute Address 0x00FF980100 (LPD_XPPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x83FF0040
DescriptionMaster Profile 0. Predefined for PMU.

Each Master profile includes a read/write attribute, a Master ID mask, a Master ID matching value, and parity bits for the profile.

MASTER_ID00 (XPPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MIDP31rwNormal read/write0x1Parity protection for [MIDR], [MIDM] and [MID].
MIDR30rwNormal read/write0x0Allow only read transactions.
0: read or write okay.
1: read transactions only.
Reserved29:26roRead-only0x0reserved
MIDM25:16rwNormal read/write0x3FFMaster ID mask. Applied to transaction Master ID and [MID] bit field.
Reserved15:10roRead-only0x0reserved
MID 9:0rwNormal read/write0x40Master ID; subject to [MIDM] mask. Predefined value may be changed to profile another master or set of masters.