Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_COMP_PATTERN_80BIT_1 (DISPLAY_PORT) Register

DP_COMP_PATTERN_80BIT_1 (DISPLAY_PORT) Register

DP_COMP_PATTERN_80BIT_1 (DISPLAY_PORT) Register Description

Register NameDP_COMP_PATTERN_80BIT_1
Relative Address0x0000000020
Absolute Address 0x00FD4A0020 (DISPLAY_PORT)
Width32
TyperwNormal read/write
Reset Value0x00000000
Description32 bits of 80-bit custom pattern that is used for LINK quality test. These bits are valid when Bit 2 of DP_LINK_QUAL_PATTERN_SET 0x10 register is set to 1

DP_COMP_PATTERN_80BIT_1 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BITS_31_031:0rwNormal read/write0x0LSB 32bits