Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > GEM_CLK_CTRL (IOU_SLCR) Register

GEM_CLK_CTRL (IOU_SLCR) Register

GEM_CLK_CTRL (IOU_SLCR) Register Description

Register NameGEM_CLK_CTRL
Relative Address0x0000000308
Absolute Address 0x00FF180308 (IOU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGEM I/O Clock Control

GEM_CLK_CTRL (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:23razRead as zero0x0Reserved. Writes are ignored, read data is zero.
TSU_CLK_LB_SEL22rwNormal read/write0x0Selection of TSU Interface clock
0: TSU clock from the PS
1: TSU clock loop backed from the PL
TSU_CLK_SEL21:20rwNormal read/write0x0Selection of TSU clock source. TSU clock is common for all the GEMs
00: TSU clock from PLL
10: TSU clock from PLL
01: reserved
11: TSU clock from MIO[50] or MIO[51]
Reserved19razRead as zero0x0Reserved. Writes are ignored, read data is zero.
GEM3_FIFO_CLK_SEL18rwNormal read/write0x0Selection of FIFO Interface clock
0: Tx clock from the PS
1: Tx clock loop backed from the PL
GEM3_SGMII_MODE17rwNormal read/write0x0Selection of SGMII or Non SGMII mode
0: Non-SGMII mode.
1: SGMII (clock is from GTR SerDes)
Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock.
GEM3_REF_SRC_SEL16rwNormal read/write0x0PLL or PHY source selection for gem3_ref_clk generation
0: PLL Reference clock
1: EMIO PLL clock or GTX Clock
GEM3_RX_SRC_SEL15rwNormal read/write0x0Select source for GEM3_RX_CLK:
0: MIO clock
1: EMIO clock
Reserved14razRead as zero0x0Reserved. Writes are ignored, read data is zero.
GEM2_FIFO_CLK_SEL13rwNormal read/write0x0Selection of FIFO Interface clock
0: Tx clock from the PS
1: Tx clock loop backed from the PL
GEM2_SGMII_MODE12rwNormal read/write0x0Selection of SGMII or Non SGMII mode
0: Non-SGMII mode.
1: SGMII (clock is from GTR SerDes)
Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock.
GEM2_REF_SRC_SEL11rwNormal read/write0x0PLL or PHY source selection for GEMn_REF_CLK generation
0: PLL Reference clock
1: EMIO PLL clock or GTX Clock
GEM2_RX_SRC_SEL10rwNormal read/write0x0Select source for GEMn_RX_CLK:
0: MIO clock
1: EMIO clock
Reserved 9razRead as zero0x0Reserved. Writes are ignored, read data is zero.
GEM1_FIFO_CLK_SEL 8rwNormal read/write0x0Selection of FIFO Interface clock
0: Tx clock from the PS
1: Tx clock loop backed from the PL
GEM1_SGMII_MODE 7rwNormal read/write0x0Selection of SGMII or Non SGMII mode
0: Non-SGMII mode.
1: SGMII (clock is from GTR SerDes)
Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock.
GEM1_REF_SRC_SEL 6rwNormal read/write0x0Select source for GEMn_RX_CLK:
0:
PLL Reference clock from Internal(PS) PLL
1: Reference/TX clock from EMIO or GTR Clock (route using [GEM0_RX_SRC_SEL]).
Valid when:
* [GEM0_SGMII_MODE] = 0 (non-SGMII).
GEM1_RX_SRC_SEL 5rwNormal read/write0x0Select external source for GEMn_RX_CLK:
0: MIO clock (route using MIO_PIN_xx registers).
1: EMIO clock.
Valid when:
* [GEM0_SGMII_MODE] = 0 (non-SGMII).
* [GEM0_REF_SRC_SEL] = 1.
Reserved 4razRead as zero0x0Reserved. Writes are ignored, read data is zero.
GEM0_FIFO_CLK_SEL 3rwNormal read/write0x0Selection of FIFO Interface clock
0: Tx clock from the PS
1: Tx clock loop backed from the PL
GEM0_SGMII_MODE 2rwNormal read/write0x0Selection of SGMII or Non SGMII mode
0: Non-SGMII mode.
1: SGMII (clock is from GTR SerDes)
Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock.
GEM0_REF_SRC_SEL 1rwNormal read/write0x0Select source for GEMn_RX_CLK:
0:
PLL Reference clock from Internal(PS) PLL
1: Reference/TX clock from EMIO or GTR Clock (route using [GEM0_RX_SRC_SEL]).
Valid when:
* [GEM0_SGMII_MODE] = 0 (non-SGMII).
GEM0_RX_SRC_SEL 0rwNormal read/write0x0Select external source for GEMn_RX_CLK:
0: MIO clock (route using MIO_PIN_xx registers).
1: EMIO clock.
Valid when:
* [GEM0_SGMII_MODE] = 0 (non-SGMII).
* [GEM0_REF_SRC_SEL] = 1.