Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB5_FSYNR0 (SMMU500) Register

SMMU_CB5_FSYNR0 (SMMU500) Register

SMMU_CB5_FSYNR0 (SMMU500) Register Description

Register NameSMMU_CB5_FSYNR0
Relative Address0x0000015068
Absolute Address 0x00FD815068 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionHolds fault syndrome information about the memory access that caused a synchronous abort exception

SMMU_CB5_FSYNR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
S1CBNDX19:16rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
AFR11rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PTWF10rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ATOF 9roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSATTR 8rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IND 6rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PNU 5rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
WNR 4rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PLVL 1:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details