Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU Module > ISR (XPPU) Register
Register Name | ISR |
---|---|
Relative Address | 0x0000000010 |
Absolute Address | 0x00FF980010 (LPD_XPPU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Status and Clear. |
AXI and APB Access Violations. If a Status bit is 1 and its Mask is 0, then the IRQ interrupt signal is activated to the interrupt controller. The first AXI violation is recorded. Once an ISR[7:1] status bit is set, subsequent AXI violations are not recorded, but their transactions are poisoned. The status bits are cleared by a system reset and can be cleared by software.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | roRead-only | 0x0 | reserved |
APER_PARITY | 7 | wtcReadable, write a 1 to clear | 0x0 | Aperture Parity Error detected for an aperture entry fetched from local RAM. 0: no error. 1: error detected. This parity checking is enable by setting CTRL [APER_PARITY_EN] = 1. |
APER_TZ | 6 | wtcReadable, write a 1 to clear | 0x0 | TrustZone Violation; a non-secure master attempted to access an aperture to a secure memory location. 0: no violation. 1: violation detected. |
APER_PERM | 5 | wtcReadable, write a 1 to clear | 0x0 | Master ID Access Violation. The transaction does not match any of the 20 Master ID aperture profile configurations. 0: no violation. 1: violation detected. |
Reserved | 4 | roRead-only | 0x0 | reserved |
MID_PARITY | 3 | wtcReadable, write a 1 to clear | 0x0 | Master ID Parity Error. One of the 20 Master ID entries fetched from the local registers contained a parity error. 0: no error. 1: error detected. This parity checking is enable by setting CTRL [MID_PARITY_EN] = 1. |
MID_RO | 2 | wtcReadable, write a 1 to clear | 0x0 | Read permission Violation. The master attempted a write, but Master ID entry matching the request specifies read-only permission; MASTER_IDxx [MIDR] =1. 0: no violation. 1: violation detected. This violation checking is enable by setting CTRL [ENABLE] = 1. |
MID_MISS | 1 | wtcReadable, write a 1 to clear | 0x0 | Master ID Not Found. The transaction's Master ID, after masking is applied, doesn't match a Master ID in the entry list. 0: no miss. 1: miss detected. |
INV_APB | 0 | wtcReadable, write a 1 to clear | 0x0 | Register Access Error on APB. A register access was requested to an unimplemented register location. The PSLVERR error signal is also asserted back to the APB interconnect. |