Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DPLL_CFG (CRF_APB) Register

DPLL_CFG (CRF_APB) Register

DPLL_CFG (CRF_APB) Register Description

Register NameDPLL_CFG
Relative Address0x0000000030
Absolute Address 0x00FD1A0030 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDPLL Integer Helper Data Configuration.

DPLL_CFG (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LOCK_DLY31:25rwNormal read/write0x0Lock circuit configuration settings for lock windowsize
Reserved24:23rwNormal read/write0x0reserved.
LOCK_CNT22:13rwNormal read/write0x0Lock circuit counter setting
Reserved12rwNormal read/write0x0reserved.
LFHF11:10rwNormal read/write0x0PLL loop filter high frequency capacitor control
Reserved 9rwNormal read/write0x0reserved.
CP 8:5rwNormal read/write0x0PLL charge pump control
Reserved 4rwNormal read/write0x0reserved.
RES 3:0rwNormal read/write0x0PLL loop filter resistor control