Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > GQSPI_LPBK_DLY_ADJ (QSPI) Register
Register Name | GQSPI_LPBK_DLY_ADJ |
---|---|
Relative Address | 0x0000000138 |
Absolute Address | 0x00FF0F0138 (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000033 |
Description | GQSPI Loopback clock delay adjustment Register |
Register for adjusting the internal loopback clock delay for read data capturing. This feature is only active if bit 5 is set AND if the baud rate divisor is programmed to 2 (i.e., 000).
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:6 | razRead as zero | 0x0 | reserved |
USE_LPBK | 5 | rwNormal read/write | 0x1 | Use internal loopback master clock for read data capturing when baud rate divisor is 2. Note: Change this value only when controller is not communicating with the memory device. |
DLY1 | 4:3 | rwNormal read/write | 0x2 | Must be set to 00 if Loopback clk used. Note: Change this value only when controller is not communicating with the memory device. |
DLY0 | 2:0 | rwNormal read/write | 0x3 | Must be set to 00 if Loopback clk used. Note: Change this value only when controller is not communicating with the memory device. |