Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > control_n_periph_id_3 (PL390) Register

control_n_periph_id_3 (PL390) Register

control_n_periph_id_3 (PL390) Register Description

Register Namecontrol_n_periph_id_3
Relative Address0x0000001FDC
Absolute Address 0x00F9001FDC (RCPU_GIC)
Width 8
TyperoRead-only
Reset Value0x00000000
DescriptionThe periph_id_[8:0] Registers provide information about the
configuration of the peripheral. Note some fields span across
adjacent registers.

control_n_periph_id_3 (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RevAnd 7:4roRead-only0x0The top-level RTL provides four AND gates that are tied-off to
provide an output value of 0x0. Once silicon is available, if
metal fixes are necessary then the manufacturer can modify the
tie-offs to indicate that a revision of the silicon has occurred.
mod_number 3:0roRead-only0x0The customer can update this field if they modify the RTL of the
GIC. Arm set this to 0x0.