Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_SMR3 (SMMU500) Register

SMMU_SMR3 (SMMU500) Register

SMMU_SMR3 (SMMU500) Register Description

Register NameSMMU_SMR3
Relative Address0x000000080C
Absolute Address 0x00FD80080C (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMatches a transaction with a particular Stream mapping register group.

SMMU_SMR3 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VALID31rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MASK30:16rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ID14:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details