Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > VCU_IEN (VCU_SLCR) Register
Register Name | VCU_IEN |
---|---|
Relative Address | 0x0000000078 |
Absolute Address | 0x00A0040078 (VCU_SLCR) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | Interrupt Enable Register. A write of 1 to this location will unmask the interrupt. (IMR: 0) |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
apm3_fifo3_ovfl | 19 | woWrite-only | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
apm3_fifo2_ovfl | 18 | woWrite-only | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
apm3_fifo1_ovfl | 17 | woWrite-only | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
apm3_fifo0_ovfl | 16 | woWrite-only | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for 2nd Decoder AXI4 Bus. |
apm3_result_valid | 15 | woWrite-only | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for 2nd Decoder AXI4 Bus. |
apm2_fifo3_ovfl | 14 | woWrite-only | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
apm2_fifo2_ovfl | 13 | woWrite-only | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
apm2_fifo1_ovfl | 12 | woWrite-only | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
apm2_fifo0_ovfl | 11 | woWrite-only | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for 1st Decoder AXI4 Bus. |
apm2_result_valid | 10 | woWrite-only | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for 1st Decoder AXI4 Bus. |
apm1_fifo3_ovfl | 9 | woWrite-only | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This for is 2nd Encoder AXI4 Bus. |
apm1_fifo2_ovfl | 8 | woWrite-only | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for 2nd Encoder AXI4 Bus. |
apm1_fifo1_ovfl | 7 | woWrite-only | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for 2nd Encoder AXI4 Bus. |
apm1_fifo0_ovfl | 6 | woWrite-only | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for 2nd Encoder AXI4 Bus. |
apm1_result_valid | 5 | woWrite-only | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is for 2nd Encoder AXI4 Bus. |
apm0_fifo3_ovfl | 4 | woWrite-only | 0x0 | Overflow occured on 2nd read latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
apm0_fifo2_ovfl | 3 | woWrite-only | 0x0 | Overflow occured on 1st read latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
apm0_fifo1_ovfl | 2 | woWrite-only | 0x0 | Overflow occured on 2nd write latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
apm0_fifo0_ovfl | 1 | woWrite-only | 0x0 | Overflow occured on 1st write latency measurement FIFO. This is for 1st Encoder AXI4 Bus. |
apm0_result_valid | 0 | woWrite-only | 0x0 | Timing window completion interrupt. This indicates that performance measurement results are available for read. This is 1st Encoder AXI4 Bus. |