Zynq UltraScale+ Devices Register Reference > Module Summary > A53_CTI_2 Module > ASICCTL (A53_CTI_2) Register
Register Name | ASICCTL |
---|---|
Relative Address | 0x0000000144 |
Absolute Address | 0x00FEE20144 (CORESIGHT_A53_CTI_2) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Implementation-defined ASIC control, value written to the register is output on asicctl[7:0]. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ASICCTL | 7:0 | rwNormal read/write | 0x0 | Implementation-defined ASIC control, value written to the register is output on asicctl[7:0].If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the Device ID Register. This is done within a Verilog define EXTMUXNUM. |