Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PERFWR1 (DDRC) Register
Register Name | PERFWR1 |
---|---|
Relative Address | 0x000000026C |
Absolute Address | 0x00FD07026C (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x0F00007F |
Description | Write CAM Register 1 |
This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
w_xact_run_length | 31:24 | rwNormal read/write | 0xF | Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. |
w_max_starve | 15:0 | rwNormal read/write | 0x7F | Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. |