Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PIDR2 (SMMU500) Register
Register Name | SMMU_PIDR2 |
---|---|
Relative Address | 0x0000000FE8 |
Absolute Address | 0x00FD800FE8 (SMMU_GPV) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x0000001B |
Description | Peripheral Identificaation register 2 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Architecture_Revision | 7:4 | roRead-only | 0x1 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
JEDEC | 3 | roRead-only | 0x1 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
JEP106_identity_code | 2:0 | roRead-only | 0x3 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |