Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM2_RESULT20 (VCU_SLCR) Register

APM2_RESULT20 (VCU_SLCR) Register

APM2_RESULT20 (VCU_SLCR) Register Description

Register NameAPM2_RESULT20
Relative Address0x000000035C
Absolute Address 0x00A004035C (VCU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x1FFF0000
DescriptionAPM2_RESULT20

APM2_RESULT20 (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
validity_check31roRead-only0x0This signal will toggle in alternate timing window. This is required for safe reading of accumulated read and write latencies parameters which requires more then one APM access. This bit field is read with all the latency related APB registers and this is expected to be same for all those registers.
Reserved30:29razRead as zero0x0reserved
min_wr_lat028:16roRead-only0x1FFF-
Reserved15:13razRead as zero0x0reserved
max_wr_lat012:0roRead-only0x0-