Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > enable_match_d_n (PL390) Register
Register Name | enable_match_d_n |
---|---|
Relative Address | 0x0000000DE0 |
Absolute Address | 0x00F9000DE0 (RCPU_GIC) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Returns the status of the match_d<n> tie-off signals for CPU Interface <n>. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
match_d | 31:0 | roRead-only | 0x0 | Returns the status of the match_d<n>[31:0] inputs on the Distributor: Bit [X] = 0 match_d<n>[X] is LOW, Bit [X] = 1 match_d<n>[X] is HIGH. Where <n> is a number, from 0 to 7, that identifies one of the CPU Interfaces. |