Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_DEC_TOP Module > AXI_BW (VCU_DEC_TOP) Register

AXI_BW (VCU_DEC_TOP) Register

AXI_BW (VCU_DEC_TOP) Register Description

Register NameAXI_BW
Relative Address0x0000009204
Absolute Address 0x00A0029204 (VCU_DECODE)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAXI Bandwidth Measurement Window

AXI_BW (VCU_DEC_TOP) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
AxiBandwidthWindow31:0rwNormal read/write0x0Time window of the bandwidth counters for the 128-bit AXI master ports. It sets the number of aclk clock cycles during which average bandwidth figures are measured. A zero value disables the counters.