Zynq UltraScale+ Devices Register Reference > Module Summary > TTC Module > Event_Control_Timer_3 (TTC) Register

Event_Control_Timer_3 (TTC) Register

Event_Control_Timer_3 (TTC) Register Description

Register NameEvent_Control_Timer_3
Relative Address0x0000000074
Absolute Address 0x00FF110074 (TTC0)
0x00FF120074 (TTC1)
0x00FF130074 (TTC2)
0x00FF140074 (TTC3)
Width 4
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnable, pulse and overflow

Event_Control_Timer_3 (TTC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
E_TM 3rwNormal read/write0x0Test Mode: when this bit is high, the event timer is pre-loaded with 0xFFFF0000 and will overflow to this value if set to do so.
E_Ov 2rwNormal read/write0x0When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow.
E_Lo 1rwNormal read/write0x0When this bit is high, the timer counts LPD_LSBUS_CLK clock cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk.
E_En 0rwNormal read/write0x0Enable timer: when this bit is high, the event timer is enabled.