Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > smmu_cb10_pmauthstatus (SMMU500) Register

smmu_cb10_pmauthstatus (SMMU500) Register

smmu_cb10_pmauthstatus (SMMU500) Register Description

Register Namesmmu_cb10_pmauthstatus
Relative Address0x000001AFB8
Absolute Address 0x00FD81AFB8 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00000080
DescriptionProvides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions

smmu_cb10_pmauthstatus (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SNI 7roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SNE 6roRead-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SI 5roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SE 4roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNI 3roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSNE 2roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSI 1roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSE 0roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details