Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_VSWIDTH (DISPLAY_PORT) Register

DP_MAIN_STREAM_VSWIDTH (DISPLAY_PORT) Register

DP_MAIN_STREAM_VSWIDTH (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_VSWIDTH
Relative Address0x0000000190
Absolute Address 0x00FD4A0190 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSets the width of the vertical sync pulse.

DP_MAIN_STREAM_VSWIDTH (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:15razRead as zero0x0
VSWIDTH14:0rwNormal read/write0x0Width of the vertical sync in lines.