Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DITHER_CONFIG_SEED0 (DISPLAY_PORT) Register

DITHER_CONFIG_SEED0 (DISPLAY_PORT) Register

DITHER_CONFIG_SEED0 (DISPLAY_PORT) Register Description

Register NameDITHER_CONFIG_SEED0
Relative Address0x000000B080
Absolute Address 0x00FD4AB080 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00008000
DescriptionTo set seed for LFSR0

DITHER_CONFIG_SEED0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0
COLR015:0rwNormal read/write0x8000Seed for random value generation for color component 0