Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > DEVTEN (USB3_XHCI) Register

DEVTEN (USB3_XHCI) Register

DEVTEN (USB3_XHCI) Register Description

Register NameDEVTEN
Relative Address0x000000C708
Absolute Address 0x00FE20C708 (USB3_0_XHCI)
0x00FE30C708 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDevice Event Enable Register
This register controls the generation of device-specific events. If an enable bit is set to 0, the event will not be generated.

DEVTEN (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:14roRead-only0x0Reserved
VENDEVTSTRCVDEN12rwNormal read/write0Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)
Reserved11roRead-only0x0Reserved
Reserved10roRead-only0x0Reserved
ERRTICERREVTEN 9rwNormal read/write0Erratic Error Event Enable
Reserved 8roRead-only0x0Reserved
SOFTEVTEN 7rwNormal read/write0Start of (u)frame
U3L2L1SuspEn 6rwNormal read/write0U3/L2-L1 Suspend Event Enable.
HibernationReqEvtEn 5rwNormal read/write0This bit enables/disables the generation of the Hibernation Request Event.
WKUPEVTEN 4rwNormal read/write0Resume/Remote Wakeup Detected Event Enable.
ULSTCNGEN 3rwNormal read/write0USB/Link State Change Event Enable
CONNECTDONEEVTEN 2rwNormal read/write0Connection Done Enable
USBRSTEVTEN 1rwNormal read/write0USB Reset Enable
DISSCONNEVTEN 0rwNormal read/write0Disconnect Detected Event Enable