Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > Enable (SPI) Register

Enable (SPI) Register

Enable (SPI) Register Description

Register NameEnable
Relative Address0x0000000014
Absolute Address 0x00FF040014 (SPI0)
0x00FF050014 (SPI1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSPI_Enable

Enable (SPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0Reserved, read as zero, ignored on write.
SPI_EN 0rwNormal read/write0x0SPI_Enable
1: enable the SPI
0: disable the SPI
Change only when controller is not actively transmitting or receiving data.