Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_DEC_TOP Module > AXI_WBW1 (VCU_DEC_TOP) Register
Register Name | AXI_WBW1 |
---|---|
Relative Address | 0x000000921C |
Absolute Address | 0x00A002921C (VCU_DECODE) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | AXI Write Bandwidth Status 1 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
AxiWriteBwStatus1 | 31:0 | roRead-only | 0x0 | Returns the number of 128-bit words written by the AXI master port 1 during the preceding bandwidth measurement window (when enabled by AXI_BW). |