Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > VIDEO_PSS_CLK_SEL (IOU_SLCR) Register
Register Name | VIDEO_PSS_CLK_SEL |
---|---|
Relative Address | 0x0000000404 |
Absolute Address | 0x00FF180404 (IOU_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Select VIDEO_REF_CLK and ALT_REF_CLK from MIO. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
PSS_ALT_CLK | 1 | rwNormal read/write | 0x0 | PS Alternate Reference Clock source selection: 0: MIO[28]. 1: MIO[51]. |
VIDEO_CLK | 0 | rwNormal read/write | 0x0 | Video Reference Clock source selection: 0: MIO[27] 1: MIO[50] |