Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > PORTLI_20 (USB3_XHCI) Register
Register Name | PORTLI_20 |
---|---|
Relative Address | 0x0000000428 |
Absolute Address |
0x00FE200428 (USB3_0_XHCI) 0x00FE300428 (USB3_1_XHCI) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:16 | roRead-only | 0x0 | Reserved |
Reserved | 15:0 | roRead-only | 0x0 | Reserved For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |