Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DPLL_CTRL (CRF_APB) Register

DPLL_CTRL (CRF_APB) Register

DPLL_CTRL (CRF_APB) Register Description

Register NameDPLL_CTRL
Relative Address0x000000002C
Absolute Address 0x00FD1A002C (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00002C09
DescriptionDPLL Clock Unit Control

DPLL_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:27rwNormal read/write0x0reserved.
POST_SRC26:24rwNormal read/write0x0Select the pass-thru clock source for PLL Bypass mode.
0xx: PS_REF_CLK
100: VIDEO_REF_CLK
101: ALT_REF_CLK
110: AUX_REF_CLK
111: GT_REF_CLK
Reserved23rwNormal read/write0x0reserved.
PRE_SRC22:20rwNormal read/write0x0Select the clock source for PLL input.
0xx: PS_REF_CLK
100: VIDEO_REF_CLK
101: ALT_REF_CLK
110: AUX_REF_CLK
111: GT_REF_CLK
Reserved19:18rwNormal read/write0x0reserved.
Reserved17rwNormal read/write0x0reserved.
DIV216rwNormal read/write0x0Enable the divide by 2 function inside of the PLL.
0: no effect.
1: divide clock by 2.
Note: this does not change the VCO frequency, just the output frequency.
Reserved15rwNormal read/write0x0reserved.
FBDIV14:8rwNormal read/write0x2CFeedback divisor integer portion for the PLL.
Reserved 7:4rwNormal read/write0x0reserved.
BYPASS 3rwNormal read/write0x1PLL Clock Bypass Mode.
0: normal PLL mode; the source clock is selected using [PRE_SRC].
1: bypass the PLL; the source clock is selected using [POST_SRC].
Reserved 2:1rwNormal read/write0x0reserved.
RESET 0rwNormal read/write0x1PLL reset.
0: active.
1: reset.
Note: Program the PLL into bypass mode before resetting the PLL.