Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB7_TLBIVAL_high (SMMU500) Register

SMMU_CB7_TLBIVAL_high (SMMU500) Register

SMMU_CB7_TLBIVAL_high (SMMU500) Register Description

Register NameSMMU_CB7_TLBIVAL_high
Relative Address0x0000017624
Absolute Address 0x00FD817624 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation.

SMMU_CB7_TLBIVAL_high (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ASID31:16woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
Address 4:0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details