Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_WB1_TARGET_PIXEL_FORMAT (GPU) Register
Register Name | PP0_WB1_TARGET_PIXEL_FORMAT |
---|---|
Relative Address | 0x0000008208 |
Absolute Address | 0x00FD4B8208 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | WB1 Target Pixel Format Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
_ | 31:4 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
WB1_TARGET_PIXEL_FORMAT | 3:0 | rwNormal read/write | 0x0 | Contains the pixel format of the target buffer |