Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU_REG Module > ISR_0 (SMMU_REG) Register

ISR_0 (SMMU_REG) Register

ISR_0 (SMMU_REG) Register Description

Register NameISR_0
Relative Address0x0000000010
Absolute Address 0x00FD5F0010 (SMMU_REG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Status Register. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

ISR_0 (SMMU_REG) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err31wtcReadable, write a 1 to clear0x0Address Decode Error
Reserved30:5roRead-only0x0Reserved
gbl_flt_irpt_ns 4wtcReadable, write a 1 to clear0x0non-secure global fault interrupt
gbl_flt_irpt_s 3wtcReadable, write a 1 to clear0x0Secure global fault interrupt
comb_perf_irpt_TBU 2wtcReadable, write a 1 to clear0x0Combined Performance counter interrupt
comb_irpt_s 1wtcReadable, write a 1 to clear0x0secure combined interrupt
comb_irpt_ns 0wtcReadable, write a 1 to clear0x0non-secure combined interrupt