Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_ILL12 (SERDES) Register

L0_TM_ILL12 (SERDES) Register

L0_TM_ILL12 (SERDES) Register Description

Register NameL0_TM_ILL12
Relative Address0x0000001990
Absolute Address 0x00FD401990 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_ILL12 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_ILL12_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
g1a_pll_ctr_byp_val 7:0rwNormal read/write0x0Value generated by PCW.