Zynq UltraScale+ Devices Register Reference > Module Summary > ZDMA Module > ZDMA_CH_CTRL2 (ZDMA) Register
Register Name | ZDMA_CH_CTRL2 |
---|---|
Relative Address | 0x0000000200 |
Absolute Address |
0x00FFA80200 (ADMA_CH0) 0x00FFA90200 (ADMA_CH1) 0x00FFAA0200 (ADMA_CH2) 0x00FFAB0200 (ADMA_CH3) 0x00FFAC0200 (ADMA_CH4) 0x00FFAD0200 (ADMA_CH5) 0x00FFAE0200 (ADMA_CH6) 0x00FFAF0200 (ADMA_CH7) 0x00FD500200 (GDMA_CH0) 0x00FD510200 (GDMA_CH1) 0x00FD520200 (GDMA_CH2) 0x00FD530200 (GDMA_CH3) 0x00FD540200 (GDMA_CH4) 0x00FD550200 (GDMA_CH5) 0x00FD560200 (GDMA_CH6) 0x00FD570200 (GDMA_CH7) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | zDMA Control Register 2 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | razRead as zero | 0x0 | Reserved for future use |
EN | 0 | rwNormal read/write | 0x0 | Channel is enabled. SW sets this 1 to trigger. If DMA channel is in pause and this bit is cleared by software then DMA channel goes to disable state when SW set CONT bit. HW clears this flag after finishing DMA operation. |