Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > ISR (QSPI) Register
Register Name | ISR |
---|---|
Relative Address | 0x0000000004 |
Absolute Address | 0x00FF0F0004 (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000104 |
Description | Interrupt Status |
This register is set when the described event occurs and the interrupt is enabled in the mask register. When any of these bits are set the interrupt output is asserted high. In the default configuration, these bits are all cleared simultaneously by reading this register, though this may be configured for an individual write-one-to-clear scheme.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:9 | roRead-only | 0x0 | reserved |
TXFIFO_EMPTY | 8 | roRead-only | 0x1 | TX FIFO Empty interrupt: 0: TX FIFO is not empty. 1: TX FIFO is empty. |
Reserved | 7 | roRead-only | 0x0 | reserved |
TX_FIFO_underflow | 6 | wtcReadable, write a 1 to clear | 0x0 | TX FIFO underflow status: 0: no underflow has been detected. 1: underflow is detected. Write 1 to this bit location to clear |
RX_FIFO_full | 5 | roRead-only | 0x0 | RX FIFO full (current FIFO status): 0: FIFO is not full. 1: FIFO is full. |
RX_FIFO_not_empty | 4 | roRead-only | 0x0 | RX FIFO not empty (current FIFO status): 0: FIFO has less than RX THRESHOLD entries. 1: FIFO has more than or equal to RX THRESHOLD entries. |
TX_FIFO_full | 3 | roRead-only | 0x0 | TX FIFO full (current FIFO status): 0: FIFO is not full 1: FIFO is full |
TX_FIFO_not_full | 2 | roRead-only | 0x1 | TX FIFO not full (current FIFO status): 0: FIFO has more than or equal to TX THRESHOLD entries. 1: FIFO has less than TX THRESHOLD entries. |
Reserved | 1 | roRead-only | 0x0 | reserved |
RX_OVERFLOW | 0 | wtcReadable, write a 1 to clear | 0x0 | Receive Overflow interrupt: 0: no overflow occurred. 1: overflow occurred. Write 1 to this bit location to clear. |