Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > ACBDLR5 (DDR_PHY) Register

ACBDLR5 (DDR_PHY) Register

ACBDLR5 (DDR_PHY) Register Description

Register NameACBDLR5
Relative Address0x0000000554
Absolute Address 0x00FD080554 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAC Bit Delay Line Register 5

ACBDLR5 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Reserved. Return zeroes on reads.
Reserved29:24roRead-only0x0reserved.
Reserved23:22roRead-only0x0Reserved. Return zeroes on reads.
Reserved21:16roRead-only0x0reserved.
Reserved15:14roRead-only0x0Reserved. Return zeroes on reads.
CKE1BD13:8rwNormal read/write0x0Delay select for the BDL on CKE[1].
Reserved 7:6roRead-only0x0Reserved. Return zeroes on reads.
CKE0BD 5:0rwNormal read/write0x0Delay select for the BDL on CKE[0].