Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > BLOCKONLY_RST (CRL_APB) Register
Register Name | BLOCKONLY_RST |
---|---|
Relative Address | 0x000000021C |
Absolute Address | 0x00FF5E021C (CRL_APB) |
Width | 4 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Records the Reason for the Block-only Reset. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 3 | wtcReadable, write a 1 to clear | 0x0 | reserved. |
Reserved | 2:1 | roRead-only | 0x0 | reserved. |
debug_only | 0 | wtcReadable, write a 1 to clear | 0x0 | Only SOC debug will be reset. |