Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_POLARITY (DISPLAY_PORT) Register
Register Name | DP_MAIN_STREAM_POLARITY |
---|---|
Relative Address | 0x0000000188 |
Absolute Address | 0x00FD4A0188 (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Provides the polarity values for the video sync signals |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | razRead as zero | 0x0 | |
VSYNC_POLARITY | 1 | rwNormal read/write | 0x0 | Polarity of the vertical sync pulse |
HSYNC_POLARITY | 0 | rwNormal read/write | 0x0 | Polarity of the horizontal sync pulse. |