Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > LQSPI_CFG (QSPI) Register

LQSPI_CFG (QSPI) Register

LQSPI_CFG (QSPI) Register Description

Register NameLQSPI_CFG
Relative Address0x00000000A0
Absolute Address 0x00FF0F00A0 (QSPI)
Width32
TyperwNormal read/write
Reset Value0x000002EB
DescriptionConfiguration

Specifically for the Linear Quad-SPI Controller Note: Change register value only when controller is not communicating with the memory device.

LQSPI_CFG (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LQ_MODE31rwNormal read/write0x0Controller Select:
0: Generic Quad-SPI.
1: Legacy LQSPI, Linear Quad-SPI.
Note: Change this value only when controller is not communicating with the memory device.
TWO_MEM30rwNormal read/write0x0I/O Configuration:
0: One memory device.
1: Two memory devices.
Note: Change this value only when controller is not communicating with the memory device.
SEP_BUS29rwNormal read/write0x0I/O Configuration:
0: Single memory interface.
1: Separate memory intefaces.
This bit only has meaning if [TWO_MEM] = 1.
Note: Change this value only when controller is not communicating with the memory device.
U_PAGE28rwNormal read/write0x0Upper Page Select:
0: Lower memory page.
1: Upper memory page.
This bit only has meaning if there are 2 memory devices are present and single interface. i.e. when following are TRUE
[TWO_MEM] = 1 (two devices)
[SEP_BUS] = 0 (one interface)
IO mode is not supported in LQSPI;
[U_PAGE] selects the lower or upper memory for configuration or read/write operations.
Note: Change this value only when controller is not communicating with the memory device.
Note: Change this value only when controller is not communicating with the memory device.
ADDR_32BIT27rwNormal read/write0x0When this bit is set to one, lower 27 bits of AXI address appended with 5 zeroes in the MSB are used as
address to the flash.
When set to zero, lower 24 bits of AXI address on linear port are used as address to the flash.
This is a static signal - should not be changed while controller is actively transmitting/receiving data to/from Flash device
Note: Change this value only when controller is not communicating with the memory device.
Reserved26rwNormal read/write0x0reserved
MODE_EN25rwNormal read/write0x0IO mode is not supported in LQSPI; program this bit to 0.
MODE_ON24rwNormal read/write0x0IO mode is not supported in LQSPI; program this bit to 0.
MODE_BITS23:16rwNormal read/write0x0IO mode is not supported in LQSPI; program these bits to 0.
Reserved15:11rwNormal read/write0x0Reserved, value is undefined when read.
DUMMY_BYTE10:8rwNormal read/write0x2Number of dummy bytes between address and return read data
INST_CODE 7:0rwNormal read/write0xEBRead instruction code.
The known read instruction codes are:
8'h03 - Read
8'h0B - Fast read
8'h3B - Fast read dual output
8'h6B - Fast read quad output
8'hBB - Fast read dual I/O
8'hEB - Fast read quad I/O
8'h13 - Four Byte Address Read
8'h0C - Four Byte Address Fast read
8'h3C - Four Byte Address Fast read dual output
8'h6C - Four Byte Address Fast read quad output
8'hBC - Four Byte Address Fast read dual I/O
8'hEC - Four Byte Address Fast read quad I/O