Zynq UltraScale+ Devices Register Reference > Module Summary > SIOU Module > reg_ctrl (SIOU) Register

reg_ctrl (SIOU) Register

reg_ctrl (SIOU) Register Description

Register Namereg_ctrl
Relative Address0x0000000000
Absolute Address 0x00FD3D0000 (SIOU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMiscellaneous control functions for SIOU

reg_ctrl (SIOU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0Reserved
slverr_enable 0rwNormal read/write0x0By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur.
Enable/Disable SLVERR during address decode failure.
0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0.
1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0.