Register Name | Address | Width | Type | Reset Value | Description |
periph_id_4 | 0x0000001FD0 | 32 | roRead-only | 0x00000004 | 4KB count, JEP106 continuation code |
periph_id_5 | 0x0000001FD4 | 32 | roRead-only | 0x00000000 | Reserved |
periph_id_6 | 0x0000001FD8 | 32 | roRead-only | 0x00000000 | Reserved |
periph_id_7 | 0x0000001FDC | 32 | roRead-only | 0x00000000 | Reserved |
periph_id_0 | 0x0000001FE0 | 32 | roRead-only | 0x00000000 | Part Number [7:0] |
periph_id_1 | 0x0000001FE4 | 32 | roRead-only | 0x000000B4 | JEP106[3:0], part number [11:8] |
periph_id_2 | 0x0000001FE8 | 32 | roRead-only | 0x0000002B | Revision, JEP106 code flag, JEP106[6:4] |
periph_id_3 | 0x0000001FEC | 32 | roRead-only | 0x00000000 | You can set this using the AMBA Designer Graphical User Interface (GUI) |
comp_id_0 | 0x0000001FF0 | 32 | roRead-only | 0x0000000D | Preamble |
comp_id_1 | 0x0000001FF4 | 32 | roRead-only | 0x000000F0 | Generic IP component class, preamble |
comp_id_2 | 0x0000001FF8 | 32 | roRead-only | 0x00000005 | Preamble |
comp_id_3 | 0x0000001FFC | 32 | roRead-only | 0x000000B1 | Preamble |
intlpd_ocm_fn_mod_iss_bm | 0x0000002008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_rpuS0_fn_mod_iss_bm | 0x0000005008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_rpuS1_fn_mod_iss_bm | 0x0000006008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_usb0S_fn_mod_iss_bm | 0x0000007008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_usb1S_fn_mod_iss_bm | 0x0000008008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_afifs2_fn_mod_iss_bm | 0x0000009008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_intiou_ib_fn_mod_iss_bm | 0x000000A008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
intlpd_intiou_ib_fn_mod | 0x000000A108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
slave_11_ib_fn_mod_iss_bm | 0x000000D008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
rpuM0_intlpd_read_qos | 0x0000042100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
rpuM0_intlpd_write_qos | 0x0000042104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
rpuM0_intlpd_fn_mod | 0x0000042108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
rpuM0_intlpd_qos_cntl | 0x000004210C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
rpuM0_intlpd_max_ot | 0x0000042110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
rpuM0_intlpd_max_comb_ot | 0x0000042114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
rpuM0_intlpd_aw_p | 0x0000042118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
rpuM0_intlpd_aw_b | 0x000004211C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
rpuM0_intlpd_aw_r | 0x0000042120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
rpuM0_intlpd_ar_p | 0x0000042124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
rpuM0_intlpd_ar_b | 0x0000042128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
rpuM0_intlpd_ar_r | 0x000004212C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
rpuM1_intlpd_read_qos | 0x0000043100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
rpuM1_intlpd_write_qos | 0x0000043104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
rpuM1_intlpd_fn_mod | 0x0000043108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
rpuM1_intlpd_qos_cntl | 0x000004310C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
rpuM1_intlpd_max_ot | 0x0000043110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
rpuM1_intlpd_max_comb_ot | 0x0000043114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
rpuM1_intlpd_aw_p | 0x0000043118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
rpuM1_intlpd_aw_b | 0x000004311C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
rpuM1_intlpd_aw_r | 0x0000043120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
rpuM1_intlpd_ar_p | 0x0000043124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
rpuM1_intlpd_ar_b | 0x0000043128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
rpuM1_intlpd_ar_r | 0x000004312C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
admaM_intlpd_ib_fn_mod2 | 0x0000044024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
admaM_intlpd_ib_fn_mod | 0x0000044108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
admaM_intlpd_ib_qos_cntl | 0x000004410C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
admaM_intlpd_ib_max_ot | 0x0000044110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
admaM_intlpd_ib_max_comb_ot | 0x0000044114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
admaM_intlpd_ib_aw_p | 0x0000044118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
admaM_intlpd_ib_aw_b | 0x000004411C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
admaM_intlpd_ib_aw_r | 0x0000044120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
admaM_intlpd_ib_ar_p | 0x0000044124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
admaM_intlpd_ib_ar_b | 0x0000044128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
admaM_intlpd_ib_ar_r | 0x000004412C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
afifm6M_intlpd_ib_fn_mod | 0x0000045108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
afifm6M_intlpd_ib_qos_cntl | 0x000004510C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
afifm6M_intlpd_ib_max_ot | 0x0000045110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
afifm6M_intlpd_ib_max_comb_ot | 0x0000045114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
afifm6M_intlpd_ib_aw_p | 0x0000045118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
afifm6M_intlpd_ib_aw_b | 0x000004511C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
afifm6M_intlpd_ib_aw_r | 0x0000045120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
afifm6M_intlpd_ib_ar_p | 0x0000045124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
afifm6M_intlpd_ib_ar_b | 0x0000045128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
afifm6M_intlpd_ib_ar_r | 0x000004512C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
dap_intlpd_ib_fn_mod2 | 0x0000047024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
dap_intlpd_ib_read_qos | 0x0000047100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
dap_intlpd_ib_write_qos | 0x0000047104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
dap_intlpd_ib_fn_mod | 0x0000047108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
dap_intlpd_ib_qos_cntl | 0x000004710C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
dap_intlpd_ib_max_ot | 0x0000047110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
dap_intlpd_ib_max_comb_ot | 0x0000047114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
dap_intlpd_ib_aw_p | 0x0000047118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
dap_intlpd_ib_aw_b | 0x000004711C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
dap_intlpd_ib_aw_r | 0x0000047120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
dap_intlpd_ib_ar_p | 0x0000047124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
dap_intlpd_ib_ar_b | 0x0000047128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
dap_intlpd_ib_ar_r | 0x000004712C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
usb0M_intlpd_ib_read_qos | 0x0000048100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
usb0M_intlpd_ib_write_qos | 0x0000048104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
usb0M_intlpd_ib_fn_mod | 0x0000048108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
usb0M_intlpd_ib_qos_cntl | 0x000004810C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
usb0M_intlpd_ib_max_ot | 0x0000048110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
usb0M_intlpd_ib_max_comb_ot | 0x0000048114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
usb0M_intlpd_ib_aw_p | 0x0000048118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
usb0M_intlpd_ib_aw_b | 0x000004811C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
usb0M_intlpd_ib_aw_r | 0x0000048120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
usb0M_intlpd_ib_ar_p | 0x0000048124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
usb0M_intlpd_ib_ar_b | 0x0000048128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
usb0M_intlpd_ib_ar_r | 0x000004812C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
usb1M_intlpd_ib_read_qos | 0x0000049100 | 32 | rwNormal read/write | 0x00000000 | Read channel QoS value |
usb1M_intlpd_ib_write_qos | 0x0000049104 | 32 | rwNormal read/write | 0x00000000 | Write channel QoS value |
usb1M_intlpd_ib_fn_mod | 0x0000049108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
usb1M_intlpd_ib_qos_cntl | 0x000004910C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
usb1M_intlpd_ib_max_ot | 0x0000049110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
usb1M_intlpd_ib_max_comb_ot | 0x0000049114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
usb1M_intlpd_ib_aw_p | 0x0000049118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
usb1M_intlpd_ib_aw_b | 0x000004911C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
usb1M_intlpd_ib_aw_r | 0x0000049120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
usb1M_intlpd_ib_ar_p | 0x0000049124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
usb1M_intlpd_ib_ar_b | 0x0000049128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
usb1M_intlpd_ib_ar_r | 0x000004912C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
intiou_intlpd_ib_fn_mod | 0x000004A108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
intiou_intlpd_ib_qos_cntl | 0x000004A10C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
intiou_intlpd_ib_max_ot | 0x000004A110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
intiou_intlpd_ib_max_comb_ot | 0x000004A114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
intiou_intlpd_ib_aw_p | 0x000004A118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
intiou_intlpd_ib_aw_b | 0x000004A11C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
intiou_intlpd_ib_aw_r | 0x000004A120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
intiou_intlpd_ib_ar_p | 0x000004A124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
intiou_intlpd_ib_ar_b | 0x000004A128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
intiou_intlpd_ib_ar_r | 0x000004A12C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
intcsupmu_intlpd_ib_fn_mod | 0x000004B108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
intcsupmu_intlpd_ib_qos_cntl | 0x000004B10C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
intcsupmu_intlpd_ib_max_ot | 0x000004B110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
intcsupmu_intlpd_ib_max_comb_ot | 0x000004B114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
intcsupmu_intlpd_ib_aw_p | 0x000004B118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
intcsupmu_intlpd_ib_aw_b | 0x000004B11C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
intcsupmu_intlpd_ib_aw_r | 0x000004B120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
intcsupmu_intlpd_ib_ar_p | 0x000004B124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
intcsupmu_intlpd_ib_ar_b | 0x000004B128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
intcsupmu_intlpd_ib_ar_r | 0x000004B12C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
intlpdinbound_intlpdmain_fn_mod | 0x000004C108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
intlpdinbound_intlpdmain_qos_cntl | 0x000004C10C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
intlpdinbound_intlpdmain_max_ot | 0x000004C110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
intlpdinbound_intlpdmain_max_comb_ot | 0x000004C114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
intlpdinbound_intlpdmain_aw_p | 0x000004C118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
intlpdinbound_intlpdmain_aw_b | 0x000004C11C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
intlpdinbound_intlpdmain_aw_r | 0x000004C120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
intlpdinbound_intlpdmain_ar_p | 0x000004C124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
intlpdinbound_intlpdmain_ar_b | 0x000004C128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
intlpdinbound_intlpdmain_ar_r | 0x000004C12C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
intfpd_intlpdocm_fn_mod | 0x000004D108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
intfpd_intlpdocm_qos_cntl | 0x000004D10C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
intfpd_intlpdocm_max_ot | 0x000004D110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
intfpd_intlpdocm_max_comb_ot | 0x000004D114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
intfpd_intlpdocm_aw_p | 0x000004D118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
intfpd_intlpdocm_aw_b | 0x000004D11C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
intfpd_intlpdocm_aw_r | 0x000004D120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
intfpd_intlpdocm_ar_p | 0x000004D124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
intfpd_intlpdocm_ar_b | 0x000004D128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
intfpd_intlpdocm_ar_r | 0x000004D12C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
ib9_fn_mod_iss_bm | 0x00000C2008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib9_fn_mod | 0x00000C2108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib5_fn_mod_iss_bm | 0x00000C3008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib5_fn_mod2 | 0x00000C3024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
ib5_fn_mod | 0x00000C3108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib5_qos_cntl | 0x00000C310C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
ib5_max_ot | 0x00000C3110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
ib5_max_comb_ot | 0x00000C3114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
ib5_aw_p | 0x00000C3118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
ib5_aw_b | 0x00000C311C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
ib5_aw_r | 0x00000C3120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
ib5_ar_p | 0x00000C3124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
ib5_ar_b | 0x00000C3128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
ib5_ar_r | 0x00000C312C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
ib6_fn_mod_iss_bm | 0x00000C4008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib6_fn_mod2 | 0x00000C4024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
ib6_fn_mod | 0x00000C4108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib6_qos_cntl | 0x00000C410C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
ib6_max_ot | 0x00000C4110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
ib6_max_comb_ot | 0x00000C4114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
ib6_aw_p | 0x00000C4118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
ib6_aw_b | 0x00000C411C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
ib6_aw_r | 0x00000C4120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
ib6_ar_p | 0x00000C4124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
ib6_ar_b | 0x00000C4128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
ib6_ar_r | 0x00000C412C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
ib8_fn_mod_iss_bm | 0x00000C5008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib8_fn_mod2 | 0x00000C5024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
ib8_fn_mod | 0x00000C5108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib8_qos_cntl | 0x00000C510C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
ib8_max_ot | 0x00000C5110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
ib8_max_comb_ot | 0x00000C5114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
ib8_aw_p | 0x00000C5118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
ib8_aw_b | 0x00000C511C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
ib8_aw_r | 0x00000C5120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
ib8_ar_p | 0x00000C5124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
ib8_ar_b | 0x00000C5128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
ib8_ar_r | 0x00000C512C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
ib0_fn_mod_iss_bm | 0x00000C6008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib0_fn_mod2 | 0x00000C6024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
ib0_fn_mod | 0x00000C6108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib0_qos_cntl | 0x00000C610C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
ib0_max_ot | 0x00000C6110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
ib0_max_comb_ot | 0x00000C6114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
ib0_aw_p | 0x00000C6118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
ib0_aw_b | 0x00000C611C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
ib0_aw_r | 0x00000C6120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
ib0_ar_p | 0x00000C6124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
ib0_ar_b | 0x00000C6128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
ib0_ar_r | 0x00000C612C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
ib11_fn_mod_iss_bm | 0x00000C7008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib11_fn_mod2 | 0x00000C7024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
ib11_fn_mod | 0x00000C7108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib11_qos_cntl | 0x00000C710C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
ib11_max_ot | 0x00000C7110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
ib11_max_comb_ot | 0x00000C7114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
ib11_aw_p | 0x00000C7118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
ib11_aw_b | 0x00000C711C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
ib11_aw_r | 0x00000C7120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
ib11_ar_p | 0x00000C7124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
ib11_ar_b | 0x00000C7128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
ib11_ar_r | 0x00000C712C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |
ib12_fn_mod_iss_bm | 0x00000C8008 | 32 | rwNormal read/write | 0x00000000 | Bus matrix issuing functionality modification register |
ib12_fn_mod2 | 0x00000C8024 | 32 | rwNormal read/write | 0x00000000 | This register is only present if upsizing or downsizing happens |
ib12_fn_mod | 0x00000C8108 | 32 | rwNormal read/write | 0x00000000 | Issuing functionality modification register |
ib12_qos_cntl | 0x00000C810C | 32 | rwNormal read/write | 0x00000000 | The QoS control register contains the enable bits for all the regulators. |
ib12_max_ot | 0x00000C8110 | 32 | rwNormal read/write | 0x00000000 | Maximum number of outstanding transactions |
ib12_max_comb_ot | 0x00000C8114 | 32 | rwNormal read/write | 0x00000000 | Maximum number of combined outstanding transactions |
ib12_aw_p | 0x00000C8118 | 32 | rwNormal read/write | 0x00000000 | AW channel peak rate |
ib12_aw_b | 0x00000C811C | 32 | rwNormal read/write | 0x00000000 | AW channel burstiness allowance |
ib12_aw_r | 0x00000C8120 | 32 | rwNormal read/write | 0x00000000 | AW channel average rate |
ib12_ar_p | 0x00000C8124 | 32 | rwNormal read/write | 0x00000000 | AR channel peak rate |
ib12_ar_b | 0x00000C8128 | 32 | rwNormal read/write | 0x00000000 | AR channel burstiness allowance |
ib12_ar_r | 0x00000C812C | 32 | rwNormal read/write | 0x00000000 | AR channel average rate |