Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_28 (PCIE_ATTRIB) Register
Register Name | ATTR_28 |
---|---|
Relative Address | 0x0000000070 |
Absolute Address | 0x00FD480070 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | ATTR_28 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 9 | rwNormal read/write | 0x0 | reserved. |
attr_dev_control_aux_power_supported | 8 | rwNormal read/write | 0x0 | Determines if Device Control[10] is writable. |
attr_dev_cap_rsvd_31_29 | 7:5 | rwNormal read/write | 0x0 | Reserved bits [31:29] in Device Capability register |
attr_dev_cap_rsvd_17_16 | 4:3 | rwNormal read/write | 0x0 | Reserved bits [17:16] in Device Capability register. |
attr_dev_cap_rsvd_14_12 | 2:0 | rwNormal read/write | 0x0 | Reserved bits [14:12] in Device Capability register. Were previously power indicator, attention indicator and attention button |