Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_109 (PCIE_ATTRIB) Register
Register Name | ATTR_109 |
---|---|
Relative Address | 0x00000001B4 |
Absolute Address | 0x00FD4801B4 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00007E04 |
Description | ATTR_109 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_tecrc_ep_inv | 15 | rwNormal read/write | 0x0 | Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted. |
attr_recrc_chk_trim | 14 | rwNormal read/write | 0x1 | Enables td bit clear and ECRC trim on received TLPs FALSE == dont trim TRUE == trim. |
attr_recrc_chk | 13:12 | rwNormal read/write | 0x3 | Enables ECRC check on received TLPs 0 == dont check 1 == always check 3 == check if enabled by ECRC check enable bit of AER cap structure |
attr_vc0_tx_lastpacket | 11:7 | rwNormal read/write | 0x1C | Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the number of brams configured for transmit |
attr_vc0_total_credits_ph | 6:0 | rwNormal read/write | 0x4 | Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non posted, and completion header credits must be <= 80 |