Zynq UltraScale+ Devices Register Reference > Module Summary > IPI Module > IPI_CTRL (IPI) Register

IPI_CTRL (IPI) Register

IPI_CTRL (IPI) Register Description

Register NameIPI_CTRL
Relative Address0x0000080000
Absolute Address 0x00FF380000 (IPI)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionIPI Controller Error Signal Control.

IPI_CTRL (IPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
slverr_enable 0rwNormal read/write0x0Unimplemented Register Access. Enable the PSLVERR signal back to APB master when an unimplemented register is accessed.
0: do not send PSLVERR.
1: assert PSLVERR for unimplemented register accesses.
Note: The [addr_decode_err] interrupt bit is set in the IPI_ISR regardless of the setting of this bit.