Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_15 (PCIE_ATTRIB) Register

ATTR_15 (PCIE_ATTRIB) Register

ATTR_15 (PCIE_ATTRIB) Register Description

Register NameATTR_15
Relative Address0x000000003C
Absolute Address 0x00FD48003C (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000004
DescriptionATTR_15

This register should only be written to during reset of the PCIe block

ATTR_15 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_bar415:0rwNormal read/write0x4For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of {BAR4,BAR3} if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32h00000000. See BAR3 description if this functions as the upper bits of a 64-bit BAR.
For a switch or root:
This must be set to FFF0_FFF0.
For an endpoint, bits are defined as follows:
Memory Space BAR (not upper bits of BAR3)
[0]
= Mem Space Indicator (set to 0)
[2:1]
= Type field (10 for 64-bit, 00 for 32-bit)
[3]
= Prefetchable (0 or 1)
[31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of {BAR5,BAR4} to 1.
IO Space BAR
0]
= IO Space Indicator (set to 1)
[1]
= Reserved (set to 0)
[31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.