Zynq UltraScale+ Devices Register Reference > Module Summary > CSUDMA Module > CSUDMA_DST_CTRL2 (CSUDMA) Register

CSUDMA_DST_CTRL2 (CSUDMA) Register

CSUDMA_DST_CTRL2 (CSUDMA) Register Description

Register NameCSUDMA_DST_CTRL2
Relative Address0x0000000824
Absolute Address 0x00FFC80824 (CSUDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x081BFFF8
DescriptionGeneral DST DMA Control Register 2

CSUDMA_DST_CTRL2 (CSUDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
Reserved27rwNormal read/write0x1reserved.
AWCACHE26:24rwNormal read/write0x0Sets the AWCACHE bits on the AXI Write channel as follows:
Bit 0 - Sets the AXI AwCache[0] signal
Bit 1 - Sets the AXI AwCache[2] signal
Bit 2 - Sets the AXI AwCache[3] signal
Note that AwCache[1] is always driven to 1
ROUTE_BIT23rwNormal read/write0x00: Command will be routed based normally
1: Command will be routed to APU's cache controller
TIMEOUT_EN22rwNormal read/write0x00: The 2 Timeout counters are disabled
1: The 2 Timeout counters are enabled
Reserved21:19rwNormal read/write0x3reserved.
Reserved18:16rwNormal read/write0x3reserved.
TIMEOUT_PRE15:4rwNormal read/write0xFFFSet the prescaler value for the timeout in clk (~2.5ns) cycles (Refer to TIMEOUT_VAL description). The TIMEOUT_PRE field is interpreted as follows:
12h000: Prescaler enables timer every cycle
12h001: Prescaler enables timer every 2 cycles
etc
12hFFF: Prescaler enables timer every 4096 cycles
MAX_OUTS_CMDS 3:0rwNormal read/write0x8Controls the maximumum number of outstanding AXI write commands issued. The field is interpreted as follows:
4h0: Up to 1 Outstanding Write command allowed
4h1: Up to 2 Outstanding Write commands allowed
etc
4h8: Up to 9 Outstanding Write commands allowed
4h9 - 4hF: Invalid. Valid range is 4h0 to 4h8.