Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_PERF_CNT_0_ENABLE (GPU) Register
Register Name | PP1_PERF_CNT_0_ENABLE |
---|---|
Relative Address | 0x000000B080 |
Absolute Address | 0x00FD4BB080 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | WB2 Global Test Compare Function Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
PERF_CNT_0_LIM_EN | 1 | rwNormal read/write | 0x0 | When set to 1, the PERF_CNT_0_LIMIT Register becomes active. If the PERF_CNT_0_VALUE Register exceeds the Performance Counter 0 Limit value, then an interrupt is asserted and the BUS_STOPPED mechanism stops the bus. The PERF_CNT_0_VALUE Register is reset to zero if you write to PERF_CNT_0_ENABLE while the counter is enabled, that is, the PERF_CNT_0_ENABLE bit is 1. |
PERF_CNT_0_ENABLE | 0 | rwNormal read/write | 0x0 | When set to 1, the performance counter 0 is reset to zero and activated. The PERF_CNT_0_SRC Register selects the event to be counted during a frame. |