Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > HEBSR (STM) Register
Register Name | HEBSR |
---|---|
Relative Address | 0x0000000D60 |
Absolute Address | 0x00FE9C0D60 (CORESIGHT_SOC_STM) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Select the Hardware Event bank. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
HEBS | 0 | rwNormal read/write | 0 | Selects the bank of 32 hardware events to control |