Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > RST_FPD_TOP (CRF_APB) Register
Register Name | RST_FPD_TOP |
---|---|
Relative Address | 0x0000000100 |
Absolute Address | 0x00FD1A0100 (CRF_APB) |
Width | 24 |
Type | rwNormal read/write |
Reset Value | 0x000F9FFE |
Description | Software Controlled FPD Resets. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 23:20 | rwNormal read/write | 0x0 | reserved. |
pcie_cfg_reset | 19 | rwNormal read/write | 0x1 | PCIe Configuration reset. |
pcie_bridge_reset | 18 | rwNormal read/write | 0x1 | PCIe Bridge reset. |
pcie_ctrl_reset | 17 | rwNormal read/write | 0x1 | PCIe Controller reset. |
dp_reset | 16 | rwNormal read/write | 0x1 | DisplayPort Controller and DMA reset. |
swdt_reset | 15 | rwNormal read/write | 0x1 | FPD_SWDT reset. |
Reserved | 14 | rwNormal read/write | 0x0 | reserved. |
Reserved | 13 | rwNormal read/write | 0x0 | reserved. |
s_axi_hpc_3_fpd_reset | 12 | rwNormal read/write | 0x1 | S_AXI_HP3_FPD reset. |
s_axi_hpc_2_fpd_reset | 11 | rwNormal read/write | 0x1 | S_AXI_HP2_FPD reset. |
s_axi_hp_1_fpd_reset | 10 | rwNormal read/write | 0x1 | S_AXI_HP1_FPD reset. |
s_axi_hp_0_fpd_reset | 9 | rwNormal read/write | 0x1 | S_AXI_HP0_FPD reset. |
s_axi_hpc_1_fpd_reset | 8 | rwNormal read/write | 0x1 | S_AXI_HPC1_FPD reset. |
s_axi_hpc_0_fpd_reset | 7 | rwNormal read/write | 0x1 | S_AXI_HPC0_FPD reset. |
fpd_dma_reset | 6 | rwNormal read/write | 0x1 | FPD_DMA reset. (gdma) |
gpu_pp1_reset | 5 | rwNormal read/write | 0x1 | GPU PP1 reset. |
gpu_pp0_reset | 4 | rwNormal read/write | 0x1 | GPU PP0 reset. |
gpu_reset | 3 | rwNormal read/write | 0x1 | GPU and PPx reset. |
gt_reset | 2 | rwNormal read/write | 0x1 | PS GTR reset. |
sata_reset | 1 | rwNormal read/write | 0x1 | SATA Controller reset. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved. |