Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_CORE_ID (DISPLAY_PORT) Register
Register Name | DP_CORE_ID |
---|---|
Relative Address | 0x00000000FC |
Absolute Address | 0x00FD4A00FC (DISPLAY_PORT) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x01020000 |
Description | Returns the unique identification code of the core and the current revision level |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ID | 31:0 | roRead-only | 0x1020000 | The value is 32'h01_02_00_00. |