Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DRAMTMG14 (DDRC) Register

DRAMTMG14 (DDRC) Register

DRAMTMG14 (DDRC) Register Description

Register NameDRAMTMG14
Relative Address0x0000000138
Absolute Address 0x00FD070138 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x000000A0
DescriptionSDRAM Timing Register 14

This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG14 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
t_xsr11:0rwNormal read/write0xA0tXSR: Exit Self Refresh to any command.
Program this to the above value divided by 2 and round up to next integer value.
Note: Used only for LPDDR3/LPDDR4 mode.