Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > TSSTIMR (STM) Register
Register Name | TSSTIMR |
---|---|
Relative Address | 0x0000000E84 |
Absolute Address | 0x00FE9C0E84 (CORESIGHT_SOC_STM) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | Force Timestamp Output. |
This write-only register is used to force the next packet caused by a stimulus port write to have a timestamp output.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
FORCETS | 0 | woWrite-only | 0 | Force Timestamp Stimulus. A write of 1 to this register bit will request the next stimulus port write which causes trace to be upgraded to have a timestamp. 0: ignored. 1: force time stamp. |