Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_38 (PCIE_ATTRIB) Register
Register Name | ATTR_38 |
---|---|
Relative Address | 0x0000000098 |
Absolute Address | 0x00FD480098 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000120 |
Description | ATTR_38 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_mps_force | 9 | rwNormal read/write | 0x0 | If set, causes the core to use the MPS value on cfg_force_mps for checking the payload size of received TLPs and for replay/acknak timeouts, instead of using Device Ctrl[7:5]. It does not change Device Ctrl[7:5]. |
attr_link_status_slot_clock_config | 8 | rwNormal read/write | 0x1 | Slot Clock Configuration. Indicates where the component uses the same physical reference clock that the platform provides on the connector. For a port that connects to the slot, indicates that it uses a clock with a common source to that used by the slot. For an adaptor inserted in the slot, indicates that it uses the same clock source as the slot, not a locally-derived clock source. Transferred to the Link Status register. |
attr_link_ctrl2_target_link_speed | 7:4 | rwNormal read/write | 0x2 | Set an upper limit on the speed advertised by the Upstream component (Root). The value is transferred to the Link Control2[3:0] Register. |
attr_link_ctrl2_hw_autonomous_speed_disable | 3 | rwNormal read/write | 0x0 | When TRUE disables hardware from changing the link speed for reasons other than reliability. The value is transferred to the Link Control2 Register[5]. |
attr_link_ctrl2_deemphasis | 2 | rwNormal read/write | 0x0 | Sets the de-emphasis level used by upstream component in 5.0 GT/s mode. The value is transferred to the Link Control2 Register[12]. 0b = -6db 1b = -3.5db. |
attr_link_control_rcb | 1 | rwNormal read/write | 0x0 | 1 implies read completion boundary is 128 bits; 0 implies 64 bits. Transferred to the Link Control register. Only non-zero for a downstream-facing port. |
attr_link_cap_surprise_down_error_capable | 0 | rwNormal read/write | 0x0 | Set on a downstream port if the detection and reporting of a surprise down event is supported |