Zynq UltraScale+ Devices Register Reference > Module Summary > SIOU Module > dp_stc_clkctrl (SIOU) Register
Register Name | dp_stc_clkctrl |
---|---|
Relative Address | 0x0000000430 |
Absolute Address | 0x00FD3D0430 (SIOU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000001 |
Description | dp_stc_ref_clk control register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:11 | roRead-only | 0x0 | Reserved |
refsel | 10 | rwNormal read/write | 0x0 | 0 - bypass divider; 1 - Use divider output |
lanesel | 9:8 | rwNormal read/write | 0x0 | Select which lane refclk should be used as STC clock source |
uptog | 7 | rwNormal read/write | 0x0 | Pulse this bit after divisor value change |
divisor | 6:1 | rwNormal read/write | 0x0 | Divisor value for the divider |
soft_rst | 0 | rwNormal read/write | 0x1 | Reset for the clock divider |