Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L1_TM_DIG_10 (SERDES) Register

L1_TM_DIG_10 (SERDES) Register

L1_TM_DIG_10 (SERDES) Register Description

Register NameL1_TM_DIG_10
Relative Address0x000000507C
Absolute Address 0x00FD40507C (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000001
DescriptionRegister value is generated by Vivado PCW.

L1_TM_DIG_10 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_DIG_10_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
Reserved 7:4roRead-only0x0Value generated by PCW.
cdr_bit_lock_time 3:0rwNormal read/write0x1Value generated by PCW.