Zynq UltraScale+ Devices Register Reference > Module Summary > DPDMA Module > DPDMA_CH5_DSCR_STRT_ADDRE (DPDMA) Register

DPDMA_CH5_DSCR_STRT_ADDRE (DPDMA) Register

DPDMA_CH5_DSCR_STRT_ADDRE (DPDMA) Register Description

Register NameDPDMA_CH5_DSCR_STRT_ADDRE
Relative Address0x0000000700
Absolute Address 0x00FD4C0700 (DPDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDescriptor Start Address Extension Register

DPDMA_CH5_DSCR_STRT_ADDRE (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0Reserved for future use
MSB15:0rwNormal read/write0x04 bit address the extension for first descriptor fetch