Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > ACBDLR0 (DDR_PHY) Register

ACBDLR0 (DDR_PHY) Register

ACBDLR0 (DDR_PHY) Register Description

Register NameACBDLR0
Relative Address0x0000000540
Absolute Address 0x00FD080540 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAC Bit Delay Line Register 0

ACBDLR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Return zeroes on reads.
Reserved29:24rwNormal read/write0x0reserved.
Reserved23:22roRead-only0x0Return zeroes on reads.
Reserved21:16rwNormal read/write0x0reserved.
Reserved15:14roRead-only0x0Return zeroes on reads.
CK1BD13:8rwNormal read/write0x0CK1 Bit Delay: Delay select for the BDL on CK1.
Reserved 7:6roRead-only0x0Return zeroes on reads.
CK0BD 5:0rwNormal read/write0x0CK0 Bit Delay: Delay select for the BDL on CK0.