Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module
Module Name | SDIO Module |
---|---|
Modules of this Type | SD0, SD1 |
Base Address | 0x00FF160000 (SD0) 0x00FF170000 (SD1) |
Description | SDIO Controller, SDIO 0 Controller |
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
reg_sdmasysaddrlo | 0x0000000000 | 16 | rwNormal read/write | 0x00000000 | Dual purpose: low SDMA address, Auto CMD23 arg. |
reg_sdmasysaddrhi | 0x0000000002 | 16 | rwNormal read/write | 0x00000000 | Dual purpose: high SDMA address, Auto CMD23 arg. |
reg_blocksize | 0x0000000004 | 16 | rwNormal read/write | 0x00000000 | Configure the Number of Bytes in a Data Block. |
reg_blockcount | 0x0000000006 | 16 | rwNormal read/write | 0x00000000 | Configure the number of data blocks |
reg_argument1lo | 0x0000000008 | 16 | rwNormal read/write | 0x00000000 | Lower bits of SD Command Argument |
reg_argument1hi | 0x000000000A | 16 | rwNormal read/write | 0x00000000 | Upper bits of SD Command Argument |
reg_transfermode | 0x000000000C | 16 | rwNormal read/write | 0x00000000 | Control the Data Transfer Operations. |
reg_command | 0x000000000E | 16 | rwNormal read/write | 0x00000000 | Controller Commands. |
reg_response0 | 0x0000000010 | 16 | roRead-only | 0x00000000 | Response 0 from SD Card. |
reg_response1 | 0x0000000012 | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_response2 | 0x0000000014 | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_response3 | 0x0000000016 | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_response4 | 0x0000000018 | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_response5 | 0x000000001A | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_response6 | 0x000000001C | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_response7 | 0x000000001E | 16 | roRead-only | 0x00000000 | This register is used to store responses from SD Cards |
reg_dataport | 0x0000000020 | 32 | rwNormal read/write | 0x00000000 | Read/write internal buffer. |
reg_presentstate | 0x0000000024 | 32 | roRead-only | 0x00080000 | SDIO Controller Status, read-only. |
reg_hostcontrol1 | 0x0000000028 | 8 | rwNormal read/write | 0x00000000 | Controller Configuration. |
reg_powercontrol | 0x0000000029 | 8 | rwNormal read/write | 0x00000000 | SD Bus Power and Voltage Level. |
reg_blockgapcontrol | 0x000000002A | 8 | mixedMixed types. See bit-field details. | 0x00000080 | This register is used to program the block gap request, read wait control and interrupt at block gap |
reg_wakeupcontrol | 0x000000002B | 8 | rwNormal read/write | 0x00000000 | Wakeup Functionality Control. |
reg_clockcontrol | 0x000000002C | 16 | mixedMixed types. See bit-field details. | 0x00000000 | Clock Frequency Control and State. |
reg_timeoutcontrol | 0x000000002E | 8 | rwNormal read/write | 0x00000000 | Set the Data Timeout Counter Value. |
reg_softwarereset | 0x000000002F | 8 | clronwrReadable, clears value on write | 0x00000000 | Software reset for data, command and all. |
reg_normalintrsts | 0x0000000030 | 16 | mixedMixed types. See bit-field details. | 0x00000000 | Status of all Interrupts |
reg_errorintrsts | 0x0000000032 | 16 | wtcReadable, write a 1 to clear | 0x00000000 | Error Interrupts Status |
reg_normalintrstsena | 0x0000000034 | 16 | mixedMixed types. See bit-field details. | 0x00000000 | Normal-type Interrupts Status Enables. |
reg_errorintrstsena | 0x0000000036 | 16 | rwNormal read/write | 0x00000000 | Error-type Interrupts Status Enables. |
reg_normalintrsigena | 0x0000000038 | 16 | mixedMixed types. See bit-field details. | 0x00000000 | Normal-type Interrupts Signal Enables. |
reg_errorintrsigena | 0x000000003A | 16 | mixedMixed types. See bit-field details. | 0x00000000 | Error-type Interrupts Signal Enables. |
reg_autocmderrsts | 0x000000003C | 16 | roRead-only | 0x00000000 | CMD12 response error of Auto CMD12 and CMD23. |
reg_hostcontrol2 | 0x000000003E | 16 | mixedMixed types. See bit-field details. | 0x00000000 | UHS Mode, I/O Drive, Tuning, Clocking, Intr, and Presets. |
reg_capabilities | 0x0000000040 | 64 | roRead-only | 0x280737EC6481 | Host controller implementation. |
reg_maxcurrentcap | 0x0000000048 | 64 | roRead-only | 0x00000000 | Maximum current capability for each voltage. |
reg_ForceEventforAUTOCMDErrorStatus | 0x0000000050 | 16 | woWrite-only | 0x00000000 | Generate Auto CMD Error Status Interrupts, write-only. |
reg_forceeventforerrintsts | 0x0000000052 | 16 | mixedMixed types. See bit-field details. | 0x00000000 | Generate Error Interrupt Status Interrupts. |
reg_admaerrsts | 0x0000000054 | 8 | roRead-only | 0x00000000 | SDIO ADMA Error State and Address. |
reg_admasysaddr0 | 0x0000000058 | 16 | rwNormal read/write | 0x00000000 | Lower physical address for ADMA data transfer. |
reg_admasysaddr1 | 0x000000005A | 16 | rwNormal read/write | 0x00000000 | ADMA Physical Address, 16 LSBs. |
reg_admasysaddr2 | 0x000000005C | 16 | rwNormal read/write | 0x00000000 | ADMA Physical Address, 16 bits. |
reg_admasysaddr3 | 0x000000005E | 16 | rwNormal read/write | 0x00000000 | ADMA Physical Address, 16 MSBs. |
reg_presetvalue0 | 0x0000000060 | 16 | roRead-only | 0x00000100 | This register is used to read the SDCLK Frequency Select Value,Clock Generator Select Value,Driver Strength Select Value |
reg_presetvalue1 | 0x0000000062 | 16 | roRead-only | 0x00000004 | Default Clock and I/O Drive Preset Values. Read clock select values and I/O drive. |
reg_presetvalue2 | 0x0000000064 | 16 | roRead-only | 0x00000002 | High-Speed Clock and I/O Drive Preset Values. Read clock select values and I/O drive. |
reg_presetvalue3 | 0x0000000066 | 16 | roRead-only | 0x00000004 | SDR12 Clock and I/O Drive Preset Values. |
reg_presetvalue4 | 0x0000000068 | 16 | roRead-only | 0x00000002 | SDR25 Clock and I/O Drive Preset Values. |
reg_presetvalue5 | 0x000000006A | 16 | roRead-only | 0x00000001 | SDR50 Clock and I/O Drive Preset Values. |
reg_presetvalue6 | 0x000000006C | 16 | roRead-only | 0x00000000 | SDR 104 Mode Clock and I/O Drive Preset Values. |
reg_presetvalue7 | 0x000000006E | 16 | roRead-only | 0x00000002 | DDR50 Clock and I/O Drive Preset Values. |
reg_boottimeoutcnt | 0x0000000070 | 32 | rwNormal read/write | 0x00000000 | Program the boot timeout value counter. |
reg_slotintrsts | 0x00000000FC | 16 | roRead-only | 0x00000000 | Read the interrupt signal for each slot. |
reg_hostcontrollerver | 0x00000000FE | 16 | roRead-only | 0x00001002 | Controller version and specification numbers. |