Zynq UltraScale+ Devices Register Reference > Module Summary > PLSYSMON Module > ANALOG_BUS (PLSYSMON) Register

ANALOG_BUS (PLSYSMON) Register

ANALOG_BUS (PLSYSMON) Register Description

Register NameANALOG_BUS
Relative Address0x0000000114
Absolute Address 0x00FFA50D14 (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionAnalog Bus Control

Note: this register is marked private because the Wizard in the Vivado design suite takes care of this. The voltage measurement is done with a unipolar sampling circuit to produce an unsigned result with a 0 to 3V range. Bits [3:0] = NorthWest region. Bits [7:4] = NorthEast region. Bits [11:8] = SouthEast region. Bits [15:12] = SouthWest region.

ANALOG_BUS (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
vuser315:12rwNormal read/write0x0Selects the analog bus to monitor for VUser3
vuser211:8rwNormal read/write0x0Selects the analog bus to monitor for VUser2
vuser1 7:4rwNormal read/write0x0Selects the analog bus to monitor for VUser1
vuser0 3:0rwNormal read/write0x0Selects the analog bus to monitor for VUser0