Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > DALEPENA (USB3_XHCI) Register

DALEPENA (USB3_XHCI) Register

DALEPENA (USB3_XHCI) Register Description

Register NameDALEPENA
Relative Address0x000000C720
Absolute Address 0x00FE20C720 (USB3_0_XHCI)
0x00FE30C720 (USB3_1_XHCI)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDevice Active USB Endpoint Enable Register.
This register indicates whether a USB endpoint is active in a given configuration or interface.

DALEPENA (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
USBACTEP31:0rwNormal read/write0x0USBACTEP
USB Active Endpoints (USBActEP)
This field indicates if a USB endpoint is active in the current configuration and interface. It applies to USB IN endpoints 0.15 and OUT endpoints 0.15, with one bit for each of the 32 possible endpoints. Even numbers are for USB OUT endpoints, and odd numbers are for USB IN endpoints, as follows:
- Bit[0]: USB EP0-OUT
- Bit[1]: USB EP0-IN
- Bit[2]: USB EP1-OUT
- Bit[3]: USB EP1-IN
The entity programming this register must set bits 0 and 1 because they enable control endpoints that map to physical endpoints (resources) after USBReset.
Hardware clears these bits for all endpoints (other than EP0-OUT and EP0-IN) after detecting a USB reset event. After receiving SetConfiguration and SetInterface requests, the application must program endpoint registers accordingly and set these bits.