Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > MASK_DATA_5_LSW (GPIO) Register

MASK_DATA_5_LSW (GPIO) Register

MASK_DATA_5_LSW (GPIO) Register Description

Register NameMASK_DATA_5_LSW
Relative Address0x0000000028
Absolute Address 0x00FF0A0028 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMaskable Output Data (GPIO Bank5, EMIO, Lower 16bits)

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16 bits of bank5, which corresponds to EMIO[70:64].

MASK_DATA_5_LSW (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MASK_5_LSW31:16woWrite-only0x0Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW]
DATA_5_LSW15:0rwNormal read/write0x0Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW]