Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DQMAP1 (DDRC) Register

DQMAP1 (DDRC) Register

DQMAP1 (DDRC) Register Description

Register NameDQMAP1
Relative Address0x0000000284
Absolute Address 0x00FD070284 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDQ Map Register 1

This register is static. Static registers can only be written when the controller is in reset.

DQMAP1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dq_nibble_map_28_3131:24rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [28-31]
dq_nibble_map_24_2723:16rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [24-27]
dq_nibble_map_20_2315:8rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [20-23]
dq_nibble_map_16_19 7:0rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [16-19]