Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX4LCDLR4 (DDR_PHY) Register

DX4LCDLR4 (DDR_PHY) Register

DX4LCDLR4 (DDR_PHY) Register Description

Register NameDX4LCDLR4
Relative Address0x0000000B90
Absolute Address 0x00FD080B90 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDATX8 n Local Calibrated Delay Line Register 4

DX4LCDLR4 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Return zeroes on reads.
Reserved24:16roRead-only0x0Returns zeroes on reads.
Caution: Do not write to this register field.
Reserved15:9roRead-only0x0Return zeroes on reads.
RDQSND 8:0rwNormal read/write0x0Read DQSN Delay: Delay select for the read DQSN (RDQSN) LCDL
for the byte when in x8 mode