Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > IR_STATUS (CRF_APB) Register

IR_STATUS (CRF_APB) Register

IR_STATUS (CRF_APB) Register Description

Register NameIR_STATUS
Relative Address0x0000000004
Absolute Address 0x00FD1A0004 (CRF_APB)
Width 1
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionAPB Register Address Decode Error Interrupt Status and Clear.

Access Violation. READ: 0: no interrupt. 1: interrupt flagged. WRITE: 0: no effect. 1: clear bit to 0. Once flagged, the interrrupt bit stays set until cleared with a write of 1. If a Status bit is 1 and its Mask is 0 (enabled), then the IRQ interrupt signal is active to the interrupt controllers.

IR_STATUS (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0wtcReadable, write a 1 to clear0x0Register Access Decode Error on APB interface.