Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ECCUSYN1 (DDRC) Register

ECCUSYN1 (DDRC) Register

ECCUSYN1 (DDRC) Register Description

Register NameECCUSYN1
Relative Address0x00000000B0
Absolute Address 0x00FD0700B0 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionECC Uncorrected Syndrome Register 1

ECCUSYN1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_uncorr_syndromes_63_3231:0roRead-only0x0Data pattern that resulted in an uncorrected error, one for each ECC lane, all concatenated together. For 32-bit ECC, this register is not used.