Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU_SINK Module > err_ctrl (XPPU_SINK) Register

err_ctrl (XPPU_SINK) Register

err_ctrl (XPPU_SINK) Register Description

Register Nameerr_ctrl
Relative Address0x000000FFEC
Absolute Address 0x00FF9CFFEC (LPD_XPPU_SINK)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionError Control. APB error signal SLVERR.

err_ctrl (XPPU_SINK) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1rwNormal read/write0x0reserved.
pslverr 0rwNormal read/write0x0Enable the PSLVERR error signal back to APB interconnect when an access violation occurs.
0: disable error signal.
1: assert error signal for access violations.
Note: The [addr_decode_err] interrupt bit is set in the ISR regardless of the setting of this bit.