Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > VIDEO_PSS_CLK_SEL (IOU_SLCR) Register

VIDEO_PSS_CLK_SEL (IOU_SLCR) Register

VIDEO_PSS_CLK_SEL (IOU_SLCR) Register Description

Register NameVIDEO_PSS_CLK_SEL
Relative Address0x0000000404
Absolute Address 0x00FF180404 (IOU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSelect VIDEO_REF_CLK and ALT_REF_CLK from MIO.

VIDEO_PSS_CLK_SEL (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0Reserved. Writes are ignored, read data is zero.
PSS_ALT_CLK 1rwNormal read/write0x0PS Alternate Reference Clock source selection:
0: MIO[28].
1: MIO[51].
VIDEO_CLK 0rwNormal read/write0x0Video Reference Clock source selection:
0: MIO[27]
1: MIO[50]