Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > QSPIDMA_DST_SIZE (QSPI) Register

QSPIDMA_DST_SIZE (QSPI) Register

QSPIDMA_DST_SIZE (QSPI) Register Description

Register NameQSPIDMA_DST_SIZE
Relative Address0x0000000804
Absolute Address 0x00FF0F0804 (QSPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDMA transfer payload

For DMA stream-to-memory data transfer.

QSPIDMA_DST_SIZE (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
SIZE28:2woWrite-only0x0Specifies the number of 4-byte words the DMA will transfer from stream to memory
Size is word aligned, so this field is only 27-bits. (2 lsbs are 0)
The action of writing to this register starts a DMA transfer of length SIZE, moving data from the stream interface to ADDR. In this case, it indicates the total payload that the DMA will move from stream to memory.
Note: Change this value only when controller is not communicating with the memory device.
Reserved 1:0razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.