Zynq UltraScale+ Devices Register Reference > Module Summary > CAN Module > ISR (CAN) Register
Register Name | ISR |
---|---|
Relative Address | 0x000000001C |
Absolute Address |
0x00FF06001C (CAN0) 0x00FF07001C (CAN1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00006000 |
Description | Interrupt Status |
The Interrupt Status Register (ISR) contains bits that are set when a particular interrupt condition occurs. If the corresponding mask bit in the Interrupt Enable Register is set, an interrupt is generated. Interrupt bits in the ISR can be cleared by writing to the Interrupt Clear Register. For all bits in the ISR, a set condition takes priority over the clear condition and the bit continues to remain 1.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:15 | rwNormal read/write | 0x0 | reserved |
TXFEMP | 14 | roRead-only | 0x1 | Transmit FIFO EmptyInterrupt A 1 indicates that the Transmit FIFO is empty. The interrupt continues to assert as long as the TX FIFO is empty. This bit can be cleared only by writing to the ICR. |
TXFWMEMP | 13 | roRead-only | 0x1 | Transmit FIFO Watermark Empty Interrupt A 1 indicates that the TX FIFO is empty based on watermark programming. The interrupt continues to assert as long as the number of empty spaces in the TX FIFO is greater than TX FIFO empty watermark. This bit can be cleared only by writing to the Interrupt Clear Register. |
RXFWMFLL | 12 | roRead-only | 0x0 | Receive FIFO Watermark Full Interrupt A 1 indicates that the RX FIFO is full based on watermark programming. The interrupt continues to assert as long as the RX FIFO count is above RX FIFO Full watermark. This bit can be cleared only by writing to the Interrupt Clear Register. |
WKUP | 11 | roRead-only | 0x0 | Wake up Interrupt A 1 indicates that the CAN controller entered Normal mode from Sleep Mode. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |
SLP | 10 | roRead-only | 0x0 | Sleep Interrupt A 1 indicates that the CAN controller entered Sleep mode. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |
BSOFF | 9 | roRead-only | 0x0 | Bus Off Interrupt A 1 indicates that the CAN controller entered the Bus Off state. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |
ERROR | 8 | roRead-only | 0x0 | Error Interrupt A 1 indicates that an error occurred during message transmission or reception. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |
RXNEMP | 7 | roRead-only | 0x0 | Receive FIFO Not Empty Interrupt A 1 indicates that the Receive FIFO is not empty. This bit can be cleared only by writing to the ICR. |
RXOFLW | 6 | roRead-only | 0x0 | RX FIFO Overflow Interrupt A 1 indicates that a message has been lost. This condition occurs when a new message is being received and the Receive FIFO is Full. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |
RXUFLW | 5 | roRead-only | 0x0 | RX FIFO Underflow Interrupt A 1 indicates that a read operation was attempted on an empty RX FIFO. This bit can be cleared only by writing to the ICR. |
RXOK | 4 | roRead-only | 0x0 | New Message Received Interrupt A 1 indicates that a message was received successfully and stored into the RX FIFO. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |
TXBFLL | 3 | roRead-only | 0x0 | High Priority Transmit Buffer Full Interrupt A 1 indicates that the High Priority Transmit Buffer is full. The status of the bit is unaffected if write transactions occur on the High Priority Transmit Buffer when it is already full. This bit can be cleared only by writing to the ICR. |
TXFLL | 2 | roRead-only | 0x0 | Transmit FIFO Full Interrupt A 1 indicates that the TX FIFO is full. The status of the bit is unaffected if write transactions occur on the Transmit FIFO when it is already full. This bit can be cleared only by writing to the Interrupt Clear Register. |
TXOK | 1 | roRead-only | 0x0 | Transmission Successful Interrupt A 1 indicates that a message was transmitted successfully. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. In Loopback mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit. |
ARBLST | 0 | roRead-only | 0x0 | Arbitration Lost Interrupt A 1 indicates that arbitration was lost during message transmission. This bit can be cleared by writing to the ICR. This bit is also cleared when a 0 is written to the CEN bit in the SRR. |