Zynq UltraScale+ Devices Register Reference > Module Summary > AFIFM Module > WRCTRL (AFIFM) Register
Register Name | WRCTRL |
---|---|
Relative Address | 0x0000000014 |
Absolute Address |
0x00FD360014 (AFIFM0) 0x00FD370014 (AFIFM1) 0x00FD380014 (AFIFM2) 0x00FD390014 (AFIFM3) 0x00FD3A0014 (AFIFM4) 0x00FD3B0014 (AFIFM5) 0x00FF9B0014 (AFIFM6) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x000003B0 |
Description | Write Channel Control Register |
Control fields for Write Channel operation
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:13 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
WR_RELEASE_MODE | 12 | rwNormal read/write | 0x0 | Mode of Write Command Release. 1'b0: Release Wr Command on 'Wlast' enqueue into Write Data FIFO (Or, in the case of longer AXI4 style bursts, release when 16 beats are enqueued in to the Write Data FIFO) 1'b1: Release write command immediately it becomes available |
Reserved | 11 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
Reserved | 10:8 | rwNormal read/write | 0x3 | reserved. |
Reserved | 7 | rwNormal read/write | 0x1 | reserved. |
Reserved | 6:4 | rwNormal read/write | 0x3 | reserved. |
PAUSE | 3 | rwNormal read/write | 0x0 | Pause the issuing of new write commands to the PS-side. Existing write commands will continue to be processed. |
FABRIC_QOS_EN | 2 | rwNormal read/write | 0x0 | Enable control of QoS from the fabric 0: The QoS bits are derived from APB register, AFIFM_WRQoS.staticQoS 1: The QoS bits are dynamically driven from the fabric input, axds_awQoS[3:0] |
FABRIC_WIDTH | 1:0 | rwNormal read/write | 0x0 | Configures the Write Channel Fabric interface width. 2b11: Reserved 2b10: 32-bit Fabric 2b01: 64-bit enabled 2b00: 128-bit enabled |