Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_96 (PCIE_ATTRIB) Register
Register Name | ATTR_96 |
---|---|
Relative Address | 0x0000000180 |
Absolute Address | 0x00FD480180 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000028 |
Description | ATTR_96 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_infer_ei | 10:6 | rwNormal read/write | 0x0 | Directs the Physical Layer to add the inferred electrical idle behavior to the specified LTSSM state when the respective bit is set to 1b. Bit 0 for L0, bit 1 for Recovery.RcvrCfg, bit 2 for Recovery.Speed when successful_speed_negotiation = 1b, bit 3 for Recovery.Speed when successful_speed_negotiation = 0b, bit 4 for Loopback.Active (as slave) |
attr_enter_rvry_ei_l0 | 5 | rwNormal read/write | 0x1 | TRUE is the only allowed setting for this attribute. When set to TRUE the device enters recovery from the L0 state on one of the two conditions, EI inference (if INFER_EI[0] is set to 1b) or analog electrical idle [if INFER_EI[0] is set to 0b) without receiving EIOS. |
attr_disable_scrambling | 4 | rwNormal read/write | 0x0 | When TRUE turn off scrambling of transmit data |
Reserved | 3 | rwNormal read/write | 0x1 | reserved. |
attr_pm_aspm_fastexit | 2 | rwNormal read/write | 0x0 | Not currently in use. |
attr_pm_aspml0s_timeout_func | 1:0 | rwNormal read/write | 0x0 | Defines how PM_ASPML0S_TIMEOUT is to be used, if enabled with PM_ASPML0S_TIMEOUT_EN (otherwise, this is not used). 0 = Absolute Value on PM_ASPML0S_TIMEOUT 1 = Add PM_ASPML0S_TIMEOUT to the built-in table value 2 = Subtract PM_ASPML0S_TIMEOUT from the built-in table value 3 = 7us - PM_ASPML0S_TIMEOUT It is the users responsibility to ensure that if "1" is chosen, the timeout value does not overflow the 15-bit field. The core will prevent underflows if option "2" is chosen (final value will be 0 for that case). |