Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PIDR0 (SMMU500) Register

SMMU_PIDR0 (SMMU500) Register

SMMU_PIDR0 (SMMU500) Register Description

Register NameSMMU_PIDR0
Relative Address0x0000000FE0
Absolute Address 0x00FD800FE0 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00000081
DescriptionPeripheral Identificaation register 0

SMMU_PIDR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PartNumber0 7:0roRead-only0x81Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details