Zynq UltraScale+ Devices Register Reference > Module Summary > NAND Module > Interrupt_Status_Register (NAND) Register
Register Name | Interrupt_Status_Register |
---|---|
Relative Address | 0x000000001C |
Absolute Address | 0x00FF10001C (NAND) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Status. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | reserved |
error_ahb_reg | 7 | rwNormal read/write | 0x0 | This bit is set if the AXI Slave sends error response in AXI Bus. This bit field is used only during MDMA mode of transfer. |
dma_int_reg | 6 | rwNormal read/write | 0x0 | This bit is set if the NFC detects the DMA Buffer Boundary is reached in DMA mode of transaction. This bit field is used only during MDMA mode of transfer. |
ecc_err_intrpt_reg | 5 | rwNormal read/write | 0x0 | This bit is set whenever single bit error is detected in ECC area While using Hamming Error correction. |
err_intrpt_reg | 4 | rwNormal read/write | 0x0 | MLC: This bit is set whenever bch detect error is asserted (for both correctable and non-correctable errors. BCH cant detect uncorrectable errors.) SLC: This bit is set by hardware when single bit error is detected. |
mul_bit_err_reg | 3 | rwNormal read/write | 0x0 | This bit is set whenever multi bit error is asserted. This field is used during Hamming (SLC) Error correction else treated as 0. |
trans_comp_reg | 2 | rwNormal read/write | 0x0 | This bit is set whenever NAND flash controller successfully performed the given operation. |
buff_rd_rdy_reg | 1 | rwNormal read/write | 0x0 | This bit is set whenever Memory read data is ready in buffer. |
buff_wr_rdy_reg | 0 | rwNormal read/write | 0x0 | This bit is set whenever buffer is having enough space to receive a block of data from AXI |