Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_LANE_COUNT_SET (DISPLAY_PORT) Register

DP_LANE_COUNT_SET (DISPLAY_PORT) Register

DP_LANE_COUNT_SET (DISPLAY_PORT) Register Description

Register NameDP_LANE_COUNT_SET
Relative Address0x0000000004
Absolute Address 0x00FD4A0004 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionTo set the lane count

DP_LANE_COUNT_SET (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:5razRead as zero0x0
LANE_CNT 4:0rwNormal read/write0x0Set to 1, 2