Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_N_VID (DISPLAY_PORT) Register

DP_MAIN_STREAM_N_VID (DISPLAY_PORT) Register

DP_MAIN_STREAM_N_VID (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_N_VID
Relative Address0x00000001B4
Absolute Address 0x00FD4A01B4 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionN value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the N value.

DP_MAIN_STREAM_N_VID (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24razRead as zero0x0
N_VID23:0rwNormal read/write0x0Unsigned value computed in the asynchronous clock mode