Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_LMB_BRAM Module > ECC_STATUS (PMU_LMB_BRAM) Register
Register Name | ECC_STATUS |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FFD50000 (PMU_LMB_RAM) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | ECC Status |
This register holds information about correctable and uncorrectable errors. The status bits are independently set to 1 for the first occurrence of each error type. The status bits are cleared by writing a 1 to the corresponding bit position, that is, the status bits can only be cleared to 0 and not set to 1 by means of a register write. The ECC Status register operates independently of the ECC Enable Interrupt register.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | razRead as zero | 0x0 | reserved |
ce_status | 1 | wtcReadable, write a 1 to clear | 0x0 | If 1 a correctable error has occurred. Cleared when 1 is written to this bit position |
ue_status | 0 | wtcReadable, write a 1 to clear | 0x0 | If 1 an uncorrectable error has occurred. Cleared when 1 is written to this bit position |