Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > GHWPARAMS6 (USB3_XHCI) Register
Register Name | GHWPARAMS6 |
---|---|
Relative Address | 0x000000C158 |
Absolute Address |
0x00FE20C158 (USB3_0_XHCI) 0x00FE30C158 (USB3_1_XHCI) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x07BAAC20 |
Description | Global Hardware Parameter Register 6 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ghwparams6_31_16 | 31:16 | roRead-only | 0x7BA | `DWC_USB3_RAM0_DEPTH |
BusFltrsSupport | 15 | roRead-only | 0x1 | `DWC_USB3_EN_BUS_FILTERS |
BCSupport | 14 | roRead-only | 0x0 | `DWC_USB3_EN_BC |
OTG_SS_Support | 13 | roRead-only | 0x1 | OTG 3.0 Support Enabled This bit indicates whether the parameter `DWC_USB3_EN_OTG is set to 2. In other words, it indicates that whether the controller supports OTG 3.0. - 1b0: No OTG 3.0 support - 1b1: Supports OTG 3.0 |
ADPSupport | 12 | roRead-only | 0x0 | `DWC_USB3_EN_ADP |
HNPSupport | 11 | roRead-only | 0x1 | RSP/HNP Support Enabled The application uses this bit to determine the controllers RSP/HNP support. If DWC_USB3_EN_OTG=2, - 1b0: RSP and HNP support is not enabled. The only exception for this rule is for SSPC-OTG devices where RSP support is not enabled, but HNP support is enabled. (Refer to the OCFG.SSPC-OTG bit.) - 1b1: RSP and HNP support is enabled If DWC_USB3_EN_OTG=1, - 1b0: HNP support is not enabled; - 1b1: HNP support is enabled; |
SRPSupport | 10 | roRead-only | 0x1 | SRP Support Enabled The application uses this bit to determine the controllers SRP support. - 1b0: SRP support is not enabled; - 1b1: SRP support is enabled; This bit is 1b1 when the parameter DWC_USB3_EN_OTG is not 0. |
ghwparams6_9_8 | 9:8 | roRead-only | 0x0 | Reserved |
ghwparams6_7 | 7 | roRead-only | 0x0 | `DWC_USB3_EN_FPGA |
ghwparams6_6 | 6 | roRead-only | 0x0 | `DWC_USB3_EN_DBG_PORTS |
ghwparams6_5_0 | 5:0 | roRead-only | 0x20 | `DWC_USB3_PSQ_FIFO_DEPTH |