Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L1_TM_CDR5 (SERDES) Register

L1_TM_CDR5 (SERDES) Register

L1_TM_CDR5 (SERDES) Register Description

Register NameL1_TM_CDR5
Relative Address0x0000005C14
Absolute Address 0x00FD405C14 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L1_TM_CDR5 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_CDR5_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
fphl_fsm_acc_cycles 7:5rwNormal read/write0x0Value generated by PCW.
ffl_ph0_int_gain 4:0rwNormal read/write0x0Value generated by PCW.