Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_LMB_BRAM Module > ECC_EN_IRQ (PMU_LMB_BRAM) Register
Register Name | ECC_EN_IRQ |
---|---|
Relative Address | 0x0000000004 |
Absolute Address | 0x00FFD50004 (PMU_LMB_RAM) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | ECC Enable Interrupt |
This register determines if the value of the CE_STATUS and UE_STATUS bits of the ECC Status Register asserts the Interrupt output signal. If both CE_EN_IRQ and UE_EN_IRQ are set to 1 (enabled), the value of the Interrupt signal is the logical OR between the CE_STATUS and UE_STATUS bits.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | razRead as zero | 0x0 | reserved |
ce_en_irq | 1 | rwNormal read/write | 0x0 | 1: The CE_STATUS bit of ECC Status Register is propagated to the Interrupt signal. 0: The CE_STATUS bit of ECC Status Register is not propagated to the Interrupt signal. |
ue_en_irq | 0 | rwNormal read/write | 0x0 | 1: The UE_STATUS bit of ECC Status Register is propagated to the Interrupt signal. 0: The UE_STATUS bit of ECC Status Register is not propagated to the Interrupt signal. |