Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > MIO_PIN_43 (IOU_SLCR) Register
Register Name | MIO_PIN_43 |
---|---|
Relative Address | 0x00000000AC |
Absolute Address | 0x00FF1800AC (IOU_SLCR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | MIO Device Pin 43 Multiplexer Controls. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | rwNormal read/write | 0x0 | reserved |
L3_SEL | 7:5 | rwNormal read/write | 0x0 | Level 3 Mux Select: 0: GPIO [43] input/output bank 1. 1: CAN0 TX output. 2: I2C0 SDA input/output. 3: LPD SWDT reset output. 4: SPI0 MOSI input/output. 5: TTC2 waveform output. 6: UART0 TxD output. 7: TracePort DQ[3] output. |
L2_SEL | 4:3 | rwNormal read/write | 0x0 | Level 2 Mux Select: 0: Level 3 Mux output 1: SDIO0 Data [2] input/output. 2: SDIO1 Card Bus Power output. 3: reserved |
L1_SEL | 2 | rwNormal read/write | 0x0 | Level 1 Mux Select: 0: Level 2 Mux output 1: reserved |
L0_SEL | 1 | rwNormal read/write | 0x0 | Level 0 Mux Select: 0: Level 1 Mux output 1: GEM1 RGMII Tx Cotnrol output. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved |