Zynq UltraScale+ Devices Register Reference > Module Summary > EFUSE Module > tsu_h_ps_cs (EFUSE) Register

tsu_h_ps_cs (EFUSE) Register

tsu_h_ps_cs (EFUSE) Register Description

Register Nametsu_h_ps_cs
Relative Address0x0000000024
Absolute Address 0x00FFCC0024 (EFUSE)
Width32
TyperwNormal read/write
Reset Value0x0000000B
DescriptionPS to CS timing

tsu_h_ps_cs (EFUSE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
value 7:0rwNormal read/write0xBCount value for the PS to CSB setup/hold timing paramter. The default value is set for a 220MHz clock. This value can be reconfigured using the following equation: ceiling(46ns / efuse_clk period) where efuse_clk is selected by the CFG register.