Zynq UltraScale+ Devices Register Reference > Module Summary > XMPU_DDR Module > R00_CONFIG (XMPU_DDR) Register
Register Name | R00_CONFIG |
---|---|
Relative Address | 0x000000010C |
Absolute Address |
0x00FD00010C (DDR_XMPU0_CFG) 0x00FD01010C (DDR_XMPU1_CFG) 0x00FD02010C (DDR_XMPU2_CFG) 0x00FD03010C (DDR_XMPU3_CFG) 0x00FD04010C (DDR_XMPU4_CFG) 0x00FD05010C (DDR_XMPU5_CFG) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000008 |
Description | Region 0 Configuration. |
If a transaction address is with an enabled Regions start and end addresses, then the [WrAllowed] / [RdAllowed] condition is checked. If the transaction R/W type is allowed, then the security check is performed. When more than one address region includes the transaction address (regions overlap), the Region with the higher number takes precedence.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:5 | roRead-only | 0x0 | reserved |
NSCheckType | 4 | rwNormal read/write | 0x0 | Non-secure Region Check Type. Secure masters may or may not be allowed to access Non-Secure (NS) memory regions. 0: relaxed checking; secure requests may access a non-secure (NS) region. 1: strict checking; secure requests may only access a secure region. |
RegionNS | 3 | rwNormal read/write | 0x1 | Select security level of region: 0: secure. 1: non-secure (NS). |
WrAllowed | 2 | rwNormal read/write | 0x0 | Allow writes to region: 0: not allowed; transaction poisoned. 1: allowed. |
RdAllowed | 1 | rwNormal read/write | 0x0 | Allow reads within region: 0: not allowed; transaction poisoned. 1: allowed. |
Enable | 0 | rwNormal read/write | 0x0 | Enable region: 0: disabled. 1: enabled. |