Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > GEM_CTRL (IOU_SLCR) Register
Register Name | GEM_CTRL |
---|---|
Relative Address | 0x0000000360 |
Absolute Address | 0x00FF180360 (IOU_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | GEM SGMII Signal Detect (PCS) connection: |
00: Connect signal detect to 0. 01: Connect signal detect to 1. 10: Connect signal detect to external optical PHY via EMIO and PL pin. 11: Reserved
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
GEM3_SGMII_SD | 7:6 | rwNormal read/write | 0x0 | GEM3 signal detect. |
GEM2_SGMII_SD | 5:4 | rwNormal read/write | 0x0 | GEM2 signal detect. |
GEM1_SGMII_SD | 3:2 | rwNormal read/write | 0x0 | GEM1 signal detect. |
GEM0_SGMII_SD | 1:0 | rwNormal read/write | 0x0 | GEM0 signal detect. |