Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_WB1_MRT_OFFSET (GPU) Register

PP0_WB1_MRT_OFFSET (GPU) Register

PP0_WB1_MRT_OFFSET (GPU) Register Description

Register NamePP0_WB1_MRT_OFFSET
Relative Address0x0000008220
Absolute Address 0x00FD4B8220 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionWB1 MRT Offset Register

PP0_WB1_MRT_OFFSET (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
WB1_MRT_OFFSET31:3rwNormal read/write0x0Offset value giving the distance in memory between each MRT
_ 2:0rwNormal read/write0x0Reserved, write as zero, read undefined.