Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module > GICP_PMU_IRQ_ENABLE (LPD_SLCR) Register

GICP_PMU_IRQ_ENABLE (LPD_SLCR) Register

GICP_PMU_IRQ_ENABLE (LPD_SLCR) Register Description

Register NameGICP_PMU_IRQ_ENABLE
Relative Address0x00000080A8
Absolute Address 0x00FF4180A8 (LPD_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

GICP_PMU_IRQ_ENABLE (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0Reserved for future use
Reserved 7woWrite-only0x0reserved.
Reserved 6woWrite-only0x0reserved.
Reserved 5woWrite-only0x0reserved.
src4 4woWrite-only0x0Create single interrupt source for PMU from GICP4
src3 3woWrite-only0x0Create single interrupt source for PMU from GICP3
src2 2woWrite-only0x0Create single interrupt source for PMU from GICP2
src1 1woWrite-only0x0Create single interrupt source for PMU from GICP1
src0 0woWrite-only0x0Create single interrupt source for PMU from GICP0