Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > Enable (SPI) Register
Register Name | Enable |
---|---|
Relative Address | 0x0000000014 |
Absolute Address |
0x00FF040014 (SPI0) 0x00FF050014 (SPI1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | SPI_Enable |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
SPI_EN | 0 | rwNormal read/write | 0x0 | SPI_Enable 1: enable the SPI 0: disable the SPI Change only when controller is not actively transmitting or receiving data. |