Zynq UltraScale+ Devices Register Reference > Module Summary > I2C Module > Time_Out (I2C) Register
Register Name | Time_Out |
---|---|
Relative Address | 0x000000001C |
Absolute Address |
0x00FF02001C (I2C0) 0x00FF03001C (I2C1) |
Width | 8 |
Type | rwNormal read/write |
Reset Value | 0x0000001F |
Description | I/O Clock Signal (SCL) Timeout Period |
A timeout interrupt can be generated if the SCL I/O clock signal is held Low for more clocks periods than defined in the [TO] bit field. The sensing is active when the SCL line is held Low by the master or the slave device. This feature detects an interface stall condition.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
TO | 7:0 | rwNormal read/write | 0x1F | Timeout Period Range: 10h to 7Fh. |