Field Name | Bits | Type | Reset Value | Description |
NORMALIZE | 27 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
CACHE_LOCK | 26 | rwNormal read/write | 0x1 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
PAGESIZE | 16 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
S2CRB_TLBEN | 10 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
MMUDISB_TLBEN | 9 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
SMTNMB_TLBEN | 8 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
S1WC2EN | 2 | rwNormal read/write | 0x1 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |