Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > GRXFIFOSIZ0 (USB3_XHCI) Register
Register Name | GRXFIFOSIZ0 |
---|---|
Relative Address | 0x000000C380 |
Absolute Address |
0x00FE20C380 (USB3_0_XHCI) 0x00FE30C380 (USB3_1_XHCI) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000185 |
Description | Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus Instances and presence of Debug Capability; device mode requires only one RxFIFO. The register default values for each mode are assigned based on the maximum packet size, number of packets to be buffered, speed of the host bus instance, bus latency, and mode of operation (host, device, or DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values. For the debug capability mode, the currently mapped RxFIFO number can be read from the GFIFOPRIDBC register. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
RXFSTADDR_N | 31:16 | rwNormal read/write | 0x0 | RxFIFOn RAM Start Address (RxFStAddr_n) This field contains the memory start address for RxFIFOn in MDWIDTH-bit words. |
RXFDEP_N | 15:0 | rwNormal read/write | 0x185 | RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16,384 |