Zynq UltraScale+ Devices Register Reference > Module Summary > A53_DBG_3 Module > CIDR1 (A53_DBG_3) Register

CIDR1 (A53_DBG_3) Register

CIDR1 (A53_DBG_3) Register Description

Register NameCIDR1
Relative Address0x0000000FF4
Absolute Address 0x00FEF10FF4 (CORESIGHT_A53_DBG_3)
Width32
TyperoRead-only
Reset Value0x00000090
DescriptionExternal Debug Component Identification Register 1

CIDR1 (A53_DBG_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLASS 7:4roRead-only0x9Component class. Reads as 0x9, debug component.
PRMBL_1 3:0roRead-only0x0Preamble. RAZ.