Zynq UltraScale+ Devices Register Reference > Module Summary > A53_PMU_2 Module > EVCNTR0_EL0 (A53_PMU_2) Register

EVCNTR0_EL0 (A53_PMU_2) Register

EVCNTR0_EL0 (A53_PMU_2) Register Description

Register NameEVCNTR0_EL0
Relative Address0x0000000000
Absolute Address 0x00FEE30000 (CORESIGHT_A53_PMU_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Event Count Registers

EVCNTR0_EL0 (A53_PMU_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EVCNTR0_EL031:0rwNormal read/write0x0Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.