Zynq UltraScale+ Devices Register Reference > Module Summary > A53_PMU_2 Module > INTENSET_EL1 (A53_PMU_2) Register

INTENSET_EL1 (A53_PMU_2) Register

INTENSET_EL1 (A53_PMU_2) Register Description

Register NameINTENSET_EL1
Relative Address0x0000000C40
Absolute Address 0x00FEE30C40 (CORESIGHT_A53_PMU_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Interrupt Enable Set Register

INTENSET_EL1 (A53_PMU_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
C31rwNormal read/write0x0PMCCNTR_EL0 overflow interrupt request enable bit.
P30:0rwNormal read/write0x0Event counter overflow interrupt request enable bit for EVCNTR<x>_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: