Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_REGS Module > jitter_adjust (USB3_REGS) Register

jitter_adjust (USB3_REGS) Register

jitter_adjust (USB3_REGS) Register Description

Register Namejitter_adjust
Relative Address0x0000000040
Absolute Address 0x00FF9D0040 (USB3_0)
0x00FF9E0040 (USB3_1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000020
DescriptionHigh Speed Jitter Adjustment

jitter_adjust (USB3_REGS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:6razRead as zero0x0reserved for future
fladj 5:0rwNormal read/write0x20Frame length adjustment register. Default value is 125 us