Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_SGFAR_low (SMMU500) Register

SMMU_SGFAR_low (SMMU500) Register

SMMU_SGFAR_low (SMMU500) Register Description

Register NameSMMU_SGFAR_low
Relative Address0x0000000040
Absolute Address 0x00FD800040 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionContains the input address of an erroneous request reported by SMMU_sGFSR.

SMMU_SGFAR_low (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
FADDR31:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details