Zynq UltraScale+ Devices Register Reference > Module Summary > A53_ETM_2 Module > VMIDCVR0 (A53_ETM_2) Register

VMIDCVR0 (A53_ETM_2) Register

VMIDCVR0 (A53_ETM_2) Register Description

Register NameVMIDCVR0
Relative Address0x0000000640
Absolute Address 0x00FEE40640 (CORESIGHT_A53_ETM_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionVMID Comparator Value Register 0

VMIDCVR0 (A53_ETM_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VALUE31:0rwNormal read/write0x0VMID value. The implemented width of this field is IMPLEMENTATION DEFINED, and is set by IDR2.VMIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset, the ETM architecture assumes that the VMID is zero until the processor updates the VMID.