Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PER (SMMU500) Register

SMMU_PER (SMMU500) Register

SMMU_PER (SMMU500) Register Description

Register NameSMMU_PER
Relative Address0x0000002200
Absolute Address 0x00FD802200 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionChecks for parity errors in TCU and TBU RAMs.

SMMU_PER (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PER_TCU15:8roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PER_TBU 7:0roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details