Zynq UltraScale+ Devices Register Reference > Module Summary > APU Module > CONFIG_1 (APU) Register
Register Name | CONFIG_1 |
---|---|
Relative Address | 0x0000000024 |
Absolute Address | 0x00FD5C0024 (APU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | L2 Configuration |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
L2RSTDISABLE | 29 | rwNormal read/write | 0x0 | Set whether to disable L2 cache invalidation at reset. Only change this signal when the MP is in the reset state. |
L1RSTDISABLE | 28 | rwNormal read/write | 0x0 | Set whether to disable L1 cache invalidation at reset. Only change this signal when the MP is in the reset state. |
CP15DISABLE | 3:0 | rwNormal read/write | 0x0 | Set whether to disable write access to certain system registers. |