Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ERROR_EN_1 (PMU_GLOBAL) Register

ERROR_EN_1 (PMU_GLOBAL) Register

ERROR_EN_1 (PMU_GLOBAL) Register Description

Register NameERROR_EN_1
Relative Address0x00000005A0
Absolute Address 0x00FFD805A0 (PMU_GLOBAL)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSystem Error Enables, Reg 1.

Individual errors can be: 0: blocked. 1: propagated. If an error is blocked, it is blocked before the ERROR_STATUS_{1, 2} read registers and does not propogate to the error interrupt logic: ERROR_INT*, ERROR_POR*, ERROR_SRST*, or ERROR_SIG* registers. For details on the bit fields, refer to the ERROR_STATUS_1 register description.

ERROR_EN_1 (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31rwNormal read/write0x0reserved.
Reserved30rwNormal read/write0x0reserved.
Reserved29rwNormal read/write0x0reserved.
Reserved28rwNormal read/write0x0reserved.
CSU_SWDT27rwNormal read/write0x0CSU_SWDT timeout.
CLK_MON26rwNormal read/write0x0Clock Monitor (ClkMon).
XMPU25:24rwNormal read/write0x0XMPU and XPPU error signals.
PWR_SUPPLY23:16rwNormal read/write0x0Eight (8) PS VCC and VCCO power supplies.
Reserved15:14rwNormal read/write0x0reserved
FPD_SWDT13rwNormal read/write0x0FPD_SWDT timeout.
LPD_SWDT12rwNormal read/write0x0LPD_SWDT timeout.
Reserved11:10rwNormal read/write0x0reserved
RPU_CCF 9rwNormal read/write0x0RPU common cause failures.
Reserved 8rwNormal read/write0x0reserved
RPU_LS 7:6rwNormal read/write0x0RPU lockstep error.
FPD_TEMP 5rwNormal read/write0x0FPD over tempurature alarm.
LPD_TEMP 4rwNormal read/write0x0LPD over tempurature alarm.
RPU1 3rwNormal read/write0x0RPU1 RAM (all ECC errors).
RPU0 2rwNormal read/write0x0RPU0 RAM (all ECC errors).
OCM_ECC 1rwNormal read/write0x0OCM (uncorrectable only).
DDR_ECC 0rwNormal read/write0x0DDR (uncorrectable only).