Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AV_BUF_NON_LIVE_LATENCY (DISPLAY_PORT) Register

AV_BUF_NON_LIVE_LATENCY (DISPLAY_PORT) Register

AV_BUF_NON_LIVE_LATENCY (DISPLAY_PORT) Register Description

Register NameAV_BUF_NON_LIVE_LATENCY
Relative Address0x000000B008
Absolute Address 0x00FD4AB008 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000180
DescriptionThe memory fetch latency. This parameter is used to offset the early VTC. The max latency supported is 412. This should have a buffer of 35 pixel clocks than actual maximum latency expected in the system

AV_BUF_NON_LIVE_LATENCY (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10razRead as zero0x0
NL_LATENCY 9:0rwNormal read/write0x180The memory fetch latency.