Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > csu_imr (CSU) Register

csu_imr (CSU) Register

csu_imr (CSU) Register Description

Register Namecsu_imr
Relative Address0x0000000024
Absolute Address 0x00FFCA0024 (CSU)
Width32
TyperoRead-only
Reset Value0xFFFFFFFF
DescriptionCSU Interrupt Mask

csu_imr (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31roRead-only0x1reserved.
Reserved30roRead-only0x1reserved.
Reserved29roRead-only0x1reserved.
Reserved28roRead-only0x1reserved.
Reserved27roRead-only0x1reserved.
Reserved26roRead-only0x1reserved.
Reserved25roRead-only0x1reserved.
Reserved24roRead-only0x1reserved.
Reserved23roRead-only0x1reserved.
Reserved22roRead-only0x1reserved.
Reserved21roRead-only0x1reserved.
Reserved20roRead-only0x1reserved.
Reserved19roRead-only0x1reserved.
Reserved18roRead-only0x1reserved.
Reserved17roRead-only0x1reserved.
Reserved16roRead-only0x1reserved.
CSU_PL_ISO15roRead-only0x1CSU PL isolation interrupt mask
CSU_RAM_ECC_ERROR14roRead-only0x1CSU RAM ECC interrupt error mask
tamper13roRead-only0x1Tamper interrupt mask
Reserved12roRead-only0x1reserved.
apb_slverr11roRead-only0x1APB slave error interrupt mask
tmr_fatal10roRead-only0x1tmr_fatal interrupt mask
pl_seu_error 9roRead-only0x1pl_seu_error interrupt mask
aes_error 8roRead-only0x1aes_error interrupt mask
pcap_wr_overflow 7roRead-only0x1pcap_wr_overflow interrupt mask
pcap_rd_overflow 6roRead-only0x1pcap_rd_overflow interrupt mask
pl_por_b 5roRead-only0x1pl_por_b interrupt mask
pl_init 4roRead-only0x1pl_init interrupt mask
pl_done 3roRead-only0x1pl_done interrupt mask
sha_done 2roRead-only0x1SHA done interrupt mask
rsa_done 1roRead-only0x1RSA done interrupt mask
aes_done 0roRead-only0x1AES done interrupt mask