Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB7_TLBIVAAL_low (SMMU500) Register

SMMU_CB7_TLBIVAAL_low (SMMU500) Register

SMMU_CB7_TLBIVAAL_low (SMMU500) Register Description

Register NameSMMU_CB7_TLBIVAAL_low
Relative Address0x0000017628
Absolute Address 0x00FD817628 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.This register is similar to SMMU_CBn_TLBIVAA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation

SMMU_CB7_TLBIVAAL_low (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Address31:0woWrite-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details