Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > Slave_Idle_count (SPI) Register

Slave_Idle_count (SPI) Register

Slave_Idle_count (SPI) Register Description

Register NameSlave_Idle_count
Relative Address0x0000000024
Absolute Address 0x00FF040024 (SPI0)
0x00FF050024 (SPI1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x000000FF
DescriptionSlave Idle Count

Slave_Idle_count (SPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved, read as zero, ignored on write.
Slave_Idle_coun 7:0rwNormal read/write0xFFSPI in slave mode detects a start only when the
external SPI master serial clock (sclk_in) is stable
(quiescent state/when the Clock is inactive ) for SPI REFERENCE CLOCK cycles
specified by slave idle count register or when the SPI
is deselected.
Change only when controller is not actively transmitting or receiving data.