Zynq UltraScale+ Devices Register Reference > Module Summary > GEM Module > tx_bd_control (GEM) Register
Register Name | tx_bd_control |
---|---|
Relative Address | 0x00000004CC |
Absolute Address |
0x00FF0B04CC (GEM0) 0x00FF0C04CC (GEM1) 0x00FF0D04CC (GEM2) 0x00FF0E04CC (GEM3) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | TX BD control register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:6 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
tx_bd_ts_mode | 5:4 | rwNormal read/write | 0x0 | TX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames |
Reserved | 3:0 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |