Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_35 (PCIE_ATTRIB) Register

ATTR_35 (PCIE_ATTRIB) Register

ATTR_35 (PCIE_ATTRIB) Register Description

Register NameATTR_35
Relative Address0x000000008C
Absolute Address 0x00FD48008C (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000FFD
DescriptionATTR_35

This register should only be written to during reset of the PCIe block

ATTR_35 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_link_cap_dll_link_active_reporting_cap15rwNormal read/write0x0Data Link Layer Link Active status notification is supported. This is optional for Upstream ports.
attr_link_cap_clock_power_management14rwNormal read/write0x0Set if the upstream port supports removal of reference clocks in L1 and L23
attr_link_cap_aspm_support13:12rwNormal read/write0x0Active State PM Support.
Indicates the level of active state power management supported by the selected PCI Express Link, encoded as follows:
0 No ASPM supported, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.
Reserved11:2rwNormal read/write0x3FFreserved.
Reserved 1rwNormal read/write0x0reserved.
attr_interrupt_stat_auto 0rwNormal read/write0x1Causes Interrupt Status to be set if a INTA Assert message is sent via cfg_interrupt*, and to be cleared if a INTA Deassert message is sent.