Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_presetvalue5 (SDIO) Register
Register Name | reg_presetvalue5 |
---|---|
Relative Address | 0x000000006A |
Absolute Address |
0x00FF16006A (SD0) 0x00FF17006A (SD1) |
Width | 16 |
Type | roRead-only |
Reset Value | 0x00000001 |
Description | SDR50 Clock and I/O Drive Preset Values. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DriverStrengthSelectValue | 15:14 | roRead-only | 0x0 | Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 00 Driver Type B is Selected 01 Driver Type A is Selected 10 Driver Type C is Selected 11 Driver Type D is Selected |
ClockGeneratorSelectValue | 10 | roRead-only | 0x0 | This bit is effective when Host Controller supports programmable clock 0 Host Controller Ver2.00 Compatible Clock Generator 1 Programmable Clock Generator |
SDCLKFrequencySelectValue | 9:0 | roRead-only | 0x1 | 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system. |