Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > GUSB2PHYACC_ULPI (USB3_XHCI) Register

GUSB2PHYACC_ULPI (USB3_XHCI) Register

GUSB2PHYACC_ULPI (USB3_XHCI) Register Description

Register NameGUSB2PHYACC_ULPI
Relative Address0x000000C280
Absolute Address 0x00FE20C280 (USB3_0_XHCI)
0x00FE30C280 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGlobal USB 2.0 UTMI PHY Vendor Control Register
The application used this register to access PHY registers. For an ULPI PHY, the core uses the ULPI interface for PHY register access.
The application sets the Vendor Control register for PHY register access and times the PHY register access. The application polls the VStatus Done bit in this register for the completion of the PHY register access.
In Device-only configurations, only one register is needed. In Host mode, per-port registers are implemented

GUSB2PHYACC_ULPI (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:27roRead-only0x0Reserved
DISUIPIDRVR26roRead-only0DISUIPIDRVR
NEWREGREQ25rwNormal read/write0New Register Request
The application sets this bit for a new vendor control access.
Setting this bit to 1 asserts the utmi_vcontrolload_n (1b0) on the UTMI interface.
VSTSDONE24roRead-only0VSTSDONE
VSTSBSY23rwNormal read/write0VSTSBSY
REGWR22rwNormal read/write0Register Write
The application sets this bit for register writes and clears it for register reads.
Note: This bit is applicable for ULPI register read/write access only.
REGADDR21:16rwNormal read/write0Register Address
The 6-bit PHY register address for immediate PHY Register Set access.
Set to 6h2F for Extended PHY Register Set access.
Note: These bits are applicable for ULPI only.
EXTREGADDR15:8rwNormal read/write0EXTREGADDR
REGDATA 7:0rwNormal read/write0REGDATA

Alternate Register GUSB2PHYACC_UTMI, reset=0x0, mask=0xf8000000
Alternate Register Field: REGDATA Offset=0 Width=8 read-only
[[*]] Description: REGDATA
Alternate Register Field: VCTRL Offset=8 Width=8 read-only
[[*]] Description: VCTRL
This field contains the 4-bit register address, and the vendor-defined 4-bit parallel output bus. Bits [11:8] of this field are also placed on bits [3:0] of the utmi_vcontrol output signal.
Alternate Register Field: REGADDR Offset=16 Width=6 read-only
[[*]] Description: REGADDR
Alternate Register Field: REGWR Offset=22 Width=1 read-only
[[*]] Description: REGWR
Alternate Register Field: VSTSBSY Offset=23 Width=1 read-only
[[*]] Description: VSTSBSY
Alternate Register Field: VSTSDONE Offset=24 Width=1 read-only
[[*]] Description: VSTSDONE:
Alternate Register Field: NEWREGREQ Offset=25 Width=1 read-only
[[*]] Description: NEWREGREQ
Alternate Register Field: DISUIPIDRVR Offset=26 Width=1 read-only
[[*]] Description: DISUIPIDRVR
Alternate Register Field: reserved_31_27 Offset=27 Width=5 read-only
[[*]] Description: Reserved