Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_GPV Module > qspiM_intiou_ib_ar_p (IOU_GPV) Register

qspiM_intiou_ib_ar_p (IOU_GPV) Register

qspiM_intiou_ib_ar_p (IOU_GPV) Register Description

Register NameqspiM_intiou_ib_ar_p
Relative Address0x000004A124
Absolute Address 0x00FE04A124 (IOU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAR channel peak rate

qspiM_intiou_ib_ar_p (IOU_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_p31:24rwNormal read/write0x0channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.