Zynq UltraScale+ Devices Register Reference > Module Summary > AFIFM Module > RDCTRL (AFIFM) Register

RDCTRL (AFIFM) Register

RDCTRL (AFIFM) Register Description

Register NameRDCTRL
Relative Address0x0000000000
Absolute Address 0x00FD360000 (AFIFM0)
0x00FD370000 (AFIFM1)
0x00FD380000 (AFIFM2)
0x00FD390000 (AFIFM3)
0x00FD3A0000 (AFIFM4)
0x00FD3B0000 (AFIFM5)
0x00FF9B0000 (AFIFM6)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x000003B0
DescriptionRead Channel Control Register

Control fields for Read Channel operation

RDCTRL (AFIFM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
Reserved10:8rwNormal read/write0x3reserved.
Reserved 7rwNormal read/write0x1reserved.
Reserved 6:4rwNormal read/write0x3reserved.
PAUSE 3rwNormal read/write0x0Pause the issuing of new read commands to the PS-side. Existing outstanding commands will continue to be processed.
FABRIC_QOS_EN 2rwNormal read/write0x0Enable control of QoS from the fabric
0: The QoS bits are derived from APB register, AFIFM_RDQoS.staticQoS
1: The QoS bits are dynamically driven from the fabric input, axds_arQoS[3:0]
FABRIC_WIDTH 1:0rwNormal read/write0x0Configures the Read Channel Fabric interface width.
2b11: Reserved
2b10: 32-bit Fabric
2b01: 64-bit enabled
2b00: 128-bit enabled