Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB12_TLBIVAL_high (SMMU500) Register
Register Name | SMMU_CB12_TLBIVAL_high |
---|---|
Relative Address | 0x000001C624 |
Absolute Address | 0x00FD81C624 (SMMU_GPV) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments, and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA, but it is only required to invalidate cached copies of the last level of translation table walk of the first stage of translation. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ASID | 31:16 | woWrite-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
Address | 4:0 | woWrite-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |