Zynq UltraScale+ Devices Register Reference > Module Summary > RPU Module > RPU_CCF_MASK (RPU) Register
Register Name | RPU_CCF_MASK |
---|---|
Relative Address | 0x0000000024 |
Absolute Address | 0x00FF9A0024 (RPU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Common Cause Signal Mask Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | Reserved for future use |
test_mbist_mode | 7 | rwNormal read/write | 0x0 | CCF MASK for MBIST enable 0 = signal is masked 1 = signal is not masked |
test_scan_mode_lp | 6 | rwNormal read/write | 0x0 | CCF MASK for power island scan enable 0 = signal is masked 1 = signal is not masked |
test_scan_mode | 5 | rwNormal read/write | 0x0 | CCF Mask for scan enable 0 = signal is masked 1 = signal is not masked |
iso | 4 | rwNormal read/write | 0x0 | CCF MASK for Isolation enable 0 = signal is masked 1 = signal is not masked |
pge | 3 | rwNormal read/write | 0x0 | CCF MASK for power island enable 0 = signal is masked 1 = signal is not masked |
r50_dbg_rst | 2 | rwNormal read/write | 0x0 | CCF MASK for R50 debug reset 0 = signal is masked 1 = signal is not masked |
r50_rst | 1 | rwNormal read/write | 0x0 | CCF Mask for R50 CPU reset 0 = signal is masked 1 = signal is not masked |
pge_rst | 0 | rwNormal read/write | 0x0 | CCF Mask for power island reset 0 = signal is masked 1 = signal is not masked |