Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TX_ANA_TM_13 (SERDES) Register

L0_TX_ANA_TM_13 (SERDES) Register

L0_TX_ANA_TM_13 (SERDES) Register Description

Register NameL0_TX_ANA_TM_13
Relative Address0x0000000034
Absolute Address 0x00FD400034 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000002
DescriptionRegister value is generated by Vivado PCW.

L0_TX_ANA_TM_13 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0reserved.
Reserved 7:4roRead-only0x0reserved.
TX_swap_polarity 3rwNormal read/write0x0Value generated by PCW.
force_TX_swap_polarity 2rwNormal read/write0x0Value generated by PCW.
Reserved 1rwNormal read/write0x1reserved.
Reserved 0rwNormal read/write0x0reserved.