Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB9_PMCR (SMMU500) Register

SMMU_CB9_PMCR (SMMU500) Register

SMMU_CB9_PMCR (SMMU500) Register Description

Register NameSMMU_CB9_PMCR
Relative Address0x0000019F04
Absolute Address 0x00FD819F04 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionProvides the equivalent of the PMCR register, in the register map of a translation context bank. PMCR provides controls for the Performance Monitors.

SMMU_CB9_PMCR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
IMP31:24roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
X 4rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P 1roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
E 0rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details