Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module > GICP_PMU_IRQ_STATUS (LPD_SLCR) Register

GICP_PMU_IRQ_STATUS (LPD_SLCR) Register

GICP_PMU_IRQ_STATUS (LPD_SLCR) Register Description

Register NameGICP_PMU_IRQ_STATUS
Relative Address0x00000080A0
Absolute Address 0x00FF4180A0 (LPD_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

GICP_PMU_IRQ_STATUS (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0Reserved for future use
Reserved 7wtcReadable, write a 1 to clear0x0reserved.
Reserved 6wtcReadable, write a 1 to clear0x0reserved.
Reserved 5wtcReadable, write a 1 to clear0x0reserved.
src4 4wtcReadable, write a 1 to clear0x0Create single interrupt source for PMU from GICP4
src3 3wtcReadable, write a 1 to clear0x0Create single interrupt source for PMU from GICP3
src2 2wtcReadable, write a 1 to clear0x0Create single interrupt source for PMU from GICP2
src1 1wtcReadable, write a 1 to clear0x0Create single interrupt source for PMU from GICP1
src0 0wtcReadable, write a 1 to clear0x0Create single interrupt source for PMU from GICP0