Zynq UltraScale+ Devices Register Reference > Module Summary > RPU Module > RPU_CCF_MASK (RPU) Register

RPU_CCF_MASK (RPU) Register

RPU_CCF_MASK (RPU) Register Description

Register NameRPU_CCF_MASK
Relative Address0x0000000024
Absolute Address 0x00FF9A0024 (RPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionCommon Cause Signal Mask Register

RPU_CCF_MASK (RPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0Reserved for future use
test_mbist_mode 7rwNormal read/write0x0CCF MASK for MBIST enable
0 = signal is masked
1 = signal is not masked
test_scan_mode_lp 6rwNormal read/write0x0CCF MASK for power island scan enable
0 = signal is masked
1 = signal is not masked
test_scan_mode 5rwNormal read/write0x0CCF Mask for scan enable
0 = signal is masked
1 = signal is not masked
iso 4rwNormal read/write0x0CCF MASK for Isolation enable
0 = signal is masked
1 = signal is not masked
pge 3rwNormal read/write0x0CCF MASK for power island enable
0 = signal is masked
1 = signal is not masked
r50_dbg_rst 2rwNormal read/write0x0CCF MASK for R50 debug reset
0 = signal is masked
1 = signal is not masked
r50_rst 1rwNormal read/write0x0CCF Mask for R50 CPU reset
0 = signal is masked
1 = signal is not masked
pge_rst 0rwNormal read/write0x0CCF Mask for power island reset
0 = signal is masked
1 = signal is not masked