Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU Module > MASTER_ID05 (XPPU) Register

MASTER_ID05 (XPPU) Register

MASTER_ID05 (XPPU) Register Description

Register NameMASTER_ID05
Relative Address0x0000000114
Absolute Address 0x00FF980114 (LPD_XPPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x03C30081
DescriptionMaster Profile 5. Predefined for APU1.

MASTER_ID05 (XPPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MIDP31rwNormal read/write0x0Parity protection for [MIDR], [MIDM] and [MID].
MIDR30rwNormal read/write0x0Allow only read transactions.
0: read or write okay.
1: read transactions only.
Reserved29:26roRead-only0x0reserved
MIDM25:16rwNormal read/write0x3C3Master ID mask. Applied to transaction Master ID and [MID] bit field.
Reserved15:10roRead-only0x0reserved
MID 9:0rwNormal read/write0x81Master ID; subject to [MIDM] mask. Predefined value may be changed to profile another master or set of masters.