Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TXPMD_TM_45 (SERDES) Register

L3_TXPMD_TM_45 (SERDES) Register

L3_TXPMD_TM_45 (SERDES) Register Description

Register NameL3_TXPMD_TM_45
Relative Address0x000000CCB4
Absolute Address 0x00FD40CCB4 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TXPMD_TM_45 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TXPMD_TM_45_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
ana_dp_byp0_7_6_rsvd 7:6roRead-only0x0Value generated by PCW.
dp_TM_TX_dp_enable_post2_path 5rwNormal read/write0x0Value generated by PCW.
dp_TM_TX_ovrd_dp_enable_post2_path 4rwNormal read/write0x0Value generated by PCW.
dp_TM_TX_dp_enable_post1_path 3rwNormal read/write0x0Value generated by PCW.
dp_TM_TX_ovrd_dp_enable_post1_path 2rwNormal read/write0x0Value generated by PCW.
dp_TM_TX_dp_enable_main_path 1rwNormal read/write0x0Value generated by PCW.
dp_TM_TX_ovrd_dp_enable_main_path 0rwNormal read/write0x0Value generated by PCW.