Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ECCCLR (DDRC) Register

ECCCLR (DDRC) Register

ECCCLR (DDRC) Register Description

Register NameECCCLR
Relative Address0x000000007C
Absolute Address 0x00FD07007C (DDRC)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionECC Clear Register

This register is dynamic. Dynamic registers can be written at any time during operation.

ECCCLR (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_clr_uncorr_err_cnt 3wtcReadable, write a 1 to clear0x0Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCSTAT.ecc_uncorr_err_cnt register is cleared by this operation. When the clear operation is complete, the DDRC automatically clears this bit.
ecc_clr_corr_err_cnt 2wtcReadable, write a 1 to clear0x0Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. When the clear operation is complete, the DDRC automatically clears this bit.
Reserved 1rwNormal read/write0x0reserved.
Reserved 0rwNormal read/write0x0reserved.