Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_LMB_BRAM Module > ECC_EN_IRQ (PMU_LMB_BRAM) Register

ECC_EN_IRQ (PMU_LMB_BRAM) Register

ECC_EN_IRQ (PMU_LMB_BRAM) Register Description

Register NameECC_EN_IRQ
Relative Address0x0000000004
Absolute Address 0x00FFD50004 (PMU_LMB_RAM)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionECC Enable Interrupt

This register determines if the value of the CE_STATUS and UE_STATUS bits of the ECC Status Register asserts the Interrupt output signal. If both CE_EN_IRQ and UE_EN_IRQ are set to 1 (enabled), the value of the Interrupt signal is the logical OR between the CE_STATUS and UE_STATUS bits.

ECC_EN_IRQ (PMU_LMB_BRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0reserved
ce_en_irq 1rwNormal read/write0x01: The CE_STATUS bit of ECC Status Register is propagated to the Interrupt signal.
0: The CE_STATUS bit of ECC Status Register is not propagated to the Interrupt signal.
ue_en_irq 0rwNormal read/write0x01: The UE_STATUS bit of ECC Status Register is propagated to the Interrupt signal.
0: The UE_STATUS bit of ECC Status Register is not propagated to the Interrupt signal.