Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DBG_TSTMP_CTRL (CRF_APB) Register

DBG_TSTMP_CTRL (CRF_APB) Register

DBG_TSTMP_CTRL (CRF_APB) Register Description

Register NameDBG_TSTMP_CTRL
Relative Address0x00000000F8
Absolute Address 0x00FD1A00F8 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00000A00
DescriptionDebug Time Stamp
Clock Generator Control in FPD.

DBG_TSTMP_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25rwNormal read/write0x0reserved.
(This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.
Reserved24rwNormal read/write0x0reserved - clock active is controlled by DBG_FPD_CTRL [CLKACT]
Reserved23:14rwNormal read/write0x0reserved.
DIVISOR013:8rwNormal read/write0xA6-bit divider.
Reserved 7:3rwNormal read/write0x0reserved.
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: IOPLL_TO_FPD
010: DPLL
011: APLL