Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_25 (PCIE_ATTRIB) Register

ATTR_25 (PCIE_ATTRIB) Register

ATTR_25 (PCIE_ATTRIB) Register Description

Register NameATTR_25
Relative Address0x0000000064
Absolute Address 0x00FD480064 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000905
DescriptionATTR_25

This register should only be written to during reset of the PCIe block

ATTR_25 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_dev_cap2_atomicop_routing_supported15rwNormal read/write0x0Drives value on Device Capabilities2[6]. Not supported for EP.
attr_dev_cap2_ari_forwarding_supported14rwNormal read/write0x0Drives value on Device Capabilities2[5]. Not supported for EP.
attr_cpl_timeout_ranges_supported13:10rwNormal read/write0x2Supported range of completion timeouts. Drives Device Capability 2 [3:0]
attr_cpl_timeout_disable_supported 9rwNormal read/write0x0If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root ports. Drives Device Capability 2 [4]
attr_cmd_intx_implemented 8rwNormal read/write0x1INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.
attr_class_code 7:0rwNormal read/write0x5Code identifying basic function, subclass and applicable programming interface.
Transferred to the Class Code register.