Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_HBA Module > GHC (SATA_AHCI_HBA) Register
Register Name | GHC |
---|---|
Relative Address | 0x0000000004 |
Absolute Address | 0x00FD0C0004 (SATA_AHCI_HBA) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x80000000 |
Description | Global HBA Control |
Controls various global actions of the HBA.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
AE | 31 | rwNormal read/write | 0x1 | AHCI Enable (AE): When set, indicates that communication to the HBA shall be via AHCI mechanisms. This can be used by an HBA that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the HBA is running under an AHCI driver. When set, software shall only communicate with the HBA using AHCI. When cleared, software shall only communicate with the HBA using legacy mechanisms. When cleared FISes are not posted to memory and no commands are sent via AHCI mechanisms. Software shall set this bit to 1 before accessing other AHCI registers. The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is 0, then GHC.AE shall be read-write and shall have a reset value of 0. If CAP.SAM is 1, then AE shall be read-only and shall have a reset value of 1. |
Reserved | 30:3 | roRead-only | 0x0 | Reserved |
MRSM | 2 | roRead-only | 0x0 | MSI Revert to Single Message (MRSM): When set to 1 by hardware, indicates that the HBA requested more than one MSI vector but has reverted to using the first vector only. When this bit is cleared to 0, the HBA has not reverted to single MSI mode (i.e. hardware is already in single MSI mode, software has allocated the number of messages requested, or hardware is sharing interrupt vectors if MC.MME < MC.MMC). The HBA may revert to single MSI mode when the number of vectors allocated by the host is less than the number requested. This bit shall only be set to 1 when the following conditions hold: * MC.MSIE = 1 (MSI is enabled) * MC.MMC > 0 (multiple messages requested) * MC.MME > 0 (more than one message allocated) * MC.MME != MC.MMC (messages allocated not equal to number requested) When this bit is set to 1, single MSI mode operation is in use and software is responsible for clearing bits in the IS register to clear interrupts. This bit shall be cleared to 0 by hardware when any of the four conditions stated is false. This bit is also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this case, the hardware has been programmed to use single MSI mode, and is not reverting to that mode. |
IE | 1 | rwNormal read/write | 0x0 | Interrupt Enable (IE): This global bit enables interrupts from the HBA. When cleared (reset default), all interrupt sources from all ports are disabled. When set, interrupts are enabled. |
HR | 0 | rwNormal read/write | 0x0 | HBA Reset (HR): When set by SW, this bit causes an internal reset of the HBA. All state machines that relate to data transfers and queuing shall return to an idle condition, and all ports shall be re-initialized via COMRESET (if staggered spin-up is not supported). If staggered spin-up is supported, then it is the responsibility of software to spin-up each port after the reset has completed. When the HBA has performed the reset action, it shall reset this bit to 0. A software write of 0 shall have no effect. For a description on which bits are reset when this bit is set, see section 10.4.3. |