Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_98 (PCIE_ATTRIB) Register
Register Name | ATTR_98 |
---|---|
Relative Address | 0x0000000188 |
Absolute Address | 0x00FD480188 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x0000FFFF |
Description | ATTR_98 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_n_fts_comclk_gen2 | 15:8 | rwNormal read/write | 0xFF | Sets the number of FTS sequences advertised in the TS1 Ordered Sets when the Link Configuration register shows that a common clock source is selected (used for all lanes when operating at 5.0 GT/s) |
attr_n_fts_comclk_gen1 | 7:0 | rwNormal read/write | 0xFF | Sets the number of FTS sequences advertised in the TS1 Ordered Sets when the Link Configuration register shows that a common clock source is selected (used for all lanes when operating at 2.5 GT/s) |