Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_MAIN Module > E_MSXT_BASE_LO (AXIPCIE_MAIN) Register

E_MSXT_BASE_LO (AXIPCIE_MAIN) Register

E_MSXT_BASE_LO (AXIPCIE_MAIN) Register Description

Register NameE_MSXT_BASE_LO
Relative Address0x0000000250
Absolute Address 0x00FD0E0250 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEgress MSI-X Table Translation - Source Address Low

E_MSXT_BASE_LO (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
msxt_base_lo31:12rwNormal read/write0x0This field must be set to 0xFD0F1
Reserved11:0roRead-only0x0