Zynq UltraScale+ Devices Register Reference > Module Summary > I2C Module > Control_Reg (I2C) Register

Control_Reg (I2C) Register

Control_Reg (I2C) Register Description

Register NameControl_Reg
Relative Address0x0000000000
Absolute Address 0x00FF020000 (I2C0)
0x00FF030000 (I2C1)
Width16
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionControl Register

Control_Reg (I2C) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
divisor_a15:14rwNormal read/write0x0Divisor for stage A clock divider.
0 - 3: Divides the input APB bus clock frequency by divisor_a + 1.
divisor_b13:8rwNormal read/write0x0Divisor for stage B clock divider.
0 - 63: Divides the output frequency from divisor_a by divisor_b + 1.
Reserved 7roRead-only0x0Reserved, read as zero, ignored on write.
CLR_FIFO 6rwNormal read/write0x00: no effect.
1: initialize the FIFO to all zeros and clears the transfer size register; self-clearing bit.
SLVMON 5rwNormal read/write0x0Slave monitor mode
1 - monitor mode.
0 - normal operation.
HOLD 4rwNormal read/write0x0hold_bus
1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host.
0 - allow the transfer to terminate as soon as all the data has been transmitted or received.
ACK_EN 3rwNormal read/write0x0This bit needs to be set to 1
1 - acknowledge enabled, ACK transmitted
0 - acknowledge disabled, NACK transmitted.
NEA 2rwNormal read/write0x0Addressing mode: This bit is used in master
mode only.
1 - normal (7-bit) address
0 - extended (10-bit) address
MS 1rwNormal read/write0x0Overall interface mode:
1 - master
0 - slave
RW 0rwNormal read/write0x0Direction of transfer:
This bit is used in master mode only.
1 - master receiver
0 - master transmitter.