Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L1_TM_RST_DLY (SERDES) Register

L1_TM_RST_DLY (SERDES) Register

L1_TM_RST_DLY (SERDES) Register Description

Register NameL1_TM_RST_DLY
Relative Address0x00000059A4
Absolute Address 0x00FD4059A4 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L1_TM_RST_DLY (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_RST_DLY_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
apb_rst_dly 7:0rwNormal read/write0x0Value generated by PCW.