Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > APM1_TRG (VCU_SLCR) Register

APM1_TRG (VCU_SLCR) Register

APM1_TRG (VCU_SLCR) Register Description

Register NameAPM1_TRG
Relative Address0x0000000208
Absolute Address 0x00A0040208 (VCU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAPM1_TRG

APM1_TRG (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0reserved
start_stop 0rwNormal read/write0x01: defines the active operating window in case of Mode 1. Rising edge(Updating this register from 0 to 1) and falling edge (Updating this register from 1 to 0) will be used as start and stop trigger for operating timing mode 2.