Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_Z_CLEAR_VALUE (GPU) Register

PP1_Z_CLEAR_VALUE (GPU) Register

PP1_Z_CLEAR_VALUE (GPU) Register Description

Register NamePP1_Z_CLEAR_VALUE
Relative Address0x000000A010
Absolute Address 0x00FD4BA010 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionZ Clear Value Register

PP1_Z_CLEAR_VALUE (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24rwNormal read/write0x0Reserved, write as zero, read undefined.
Z_CLEAR_VALUE23:0rwNormal read/write0x0The 24-bit depth value of the Z tile buffer is logically cleared whenever processing of a
new tile starts. If you do not want the Z tile buffer to be cleared, the content of the Z tile
buffer can be pre-loaded by using a textured quad and Z-replacement technique. For
more information see the explanation of subword 3 in Render state word data structures
on page 3-132. See also Table 3-231 on page 3-181 and the corresponding description
of texel format value 50.