Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > enable_spi_pending_clr1 (PL390) Register

enable_spi_pending_clr1 (PL390) Register

enable_spi_pending_clr1 (PL390) Register Description

Register Nameenable_spi_pending_clr1
Relative Address0x0000000288
Absolute Address 0x00F9000288 (RCPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPending Clear Register (ICDICPR)

enable_spi_pending_clr1 (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.