Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > pcap_ctrl (CSU) Register

pcap_ctrl (CSU) Register

pcap_ctrl (CSU) Register Description

Register Namepcap_ctrl
Relative Address0x0000003008
Absolute Address 0x00FFCA3008 (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionPCAP Control

pcap_ctrl (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved 3rwNormal read/write0x0reserved.
Reserved 2rwNormal read/write0x0reserved.
pcfg_por_cnt_4k 1rwNormal read/write0x0If set, this register will reduce the internal PL POR counter and shorten the POR time of the PL.
pcap_pr 0rwNormal read/write0x1Controls the method for PL partial reconfiguraiton
0x0 - ICAP / MCAP
0x1 - PCAP