Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_HBA Module > CCC_CTL (SATA_AHCI_HBA) Register

CCC_CTL (SATA_AHCI_HBA) Register

CCC_CTL (SATA_AHCI_HBA) Register Description

Register NameCCC_CTL
Relative Address0x0000000014
Absolute Address 0x00FD0C0014 (SATA_AHCI_HBA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00010110
DescriptionCommand Completion Coalescing Control

The command completion coalescing control register is used to configure the command completion coalescing feature for the entire HBA. HBA state variables (examples include hCccComplete and hCccTimer) are used to describe the required externally visible behavior. Implementations are not required to have internal state values that directly correspond to these variables.

CCC_CTL (SATA_AHCI_HBA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TV31:16rwNormal read/write0x1Timeout Value (TV): The timeout value is specified in 1 millisecond intervals.
The timer accuracy shall be within 5%.
hCccTimer is loaded with this timeout value.
hCccTimer is only decremented when commands are outstanding on selected ports, as defined in section 11.2.
The HBA will signal a CCC interrupt when hCccTimer has decremented to 0.
hCccTimer is reset to the timeout value on the assertion of each CCC interrupt.
A timeout value of 0
is reserved.
CC15:8rwNormal read/write0x1Command Completions (CC): Specifies the number of command completions that are necessary to cause a CCC interrupt.
The HBA has an internal command completion counter, hCccComplete.
hCccComplete is incremented by one each time a selected port has a command completion.
When hCccComplete is equal to the command completions value, a CCC interrupt is signaled.
The internal command completion counter is reset to 0 on the assertion of each CCC interrupt.
A value of 0 for this field shall disable CCC interrupts being generated based on the number of commands completed, i.e. CCC interrupts are only generated based on the timer in this case.
INT 7:3roRead-only0x2Interrupt (INT): Specifies the interrupt used by the CCC feature.
This interrupt must be marked as unused in the Ports Implemented (PI) register by the corresponding bit being set to 0.
Thus, the CCC interrupt corresponds to the interrupt for an unimplemented port on the controller.
When a CCC interrupt occurs, the IS.IPS[INT] bit shall be asserted to 1.
This field also specifies the interrupt vector used for MSI.
Reserved 2:1roRead-only0x0Reserved
EN 0rwNormal read/write0x0Enable (EN): When cleared to 0, the command completion coalescing feature is disabled and no CCC interrupts are generated.
When set to 1, the command completion coalescing feature is enabled and CCC interrupts may be generated based on timeout or command completion conditions.
Software shall only change the contents of the TV and CC fields when EN is cleared to 0. On transition of this bit from 0 to 1, any updated values for the TV and CC fields shall take effect.