Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > SD_CONFIG_REG1 (IOU_SLCR) Register
Register Name | SD_CONFIG_REG1 |
---|---|
Relative Address | 0x000000031C |
Absolute Address | 0x00FF18031C (IOU_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x32403240 |
Description | SD Configuration, Reg 1. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
SD1_BASECLK | 30:23 | rwNormal read/write | 0x64 | Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. This field is primarily used for defining the input base clock frequency value to the DLL lookup table. The DLL Lookup table ( from RTL) requires a precise value to be programmed |
SD1_TUNIGCOUNT | 22:17 | rwNormal read/write | 0x20 | Configures the Number of Taps (Phases) of the rxclk_in that is supported. |
SD1_ASYNCWKPENA | 16 | rwNormal read/write | 0x0 | Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/ Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated. The Assertion and deassertion of the wakeup Event signal synchronous to xin_clk. 1: Asyncrhonous Wakeup Mode: The xin_clk and the host_clk can be stopped in this mode and the Wake up Event is asynchronously generated based on the Card Insertion/Removal/Interrupt Events. The Assertion and deassertion of the wakeup Event signal is asynchronous. |
Reserved | 15 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
SD0_BASECLK | 14:7 | rwNormal read/write | 0x64 | Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. This field is primarily used for defining the input base clock frequency value to the DLL lookup table. The DLL Lookup table ( from RTL) requires a precise value to be programmed so that it chooses appropriate divisor. The valid range of values for this field is 50 or 100 or 200 any other value other than this will not result in a proper look up of the DLL to choose the divisor value appropriately. |
SD0_TUNIGCOUNT | 6:1 | rwNormal read/write | 0x20 | Configures the Number of Taps (Phases) of the rxclk_in that is supported for auto tuning mode |
SD0_ASYNCWKPENA | 0 | rwNormal read/write | 0x0 | Select the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated. The Assertion and deassertion of the wakeup Event signal synchronous to xin_clk. 1: Asyncrhonous Wakeup Mode: The xin_clk and the host_clk can be stopped in this mode and the Wake up Event is asynchronously generated based on the Card Insertion/Removal/Interrupt Events. The Assertion and deassertion of the wakeup Event signal is asynchronous. |