Zynq UltraScale+ Devices Register Reference > Module Summary > TSGEN Module > CIDR3 (TSGEN) Register
Register Name | CIDR3 |
---|---|
Relative Address | 0x0000000FFC |
Absolute Address | 0x00FE900FFC (CORESIGHT_SOC_TSGEN) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x000000B1 |
Description | A component identification register, that indicates that the identification registers are present. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PRMBL_3 | 7:0 | roRead-only | 0xB1 | Contains bits[31:24] of the component identification code. |