Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU_REG Module > MISC (SMMU_REG) Register
Register Name | MISC |
---|---|
Relative Address | 0x0000000054 |
Absolute Address | 0x00FD5F0054 (SMMU_REG) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000016 |
Description | Miscellaneous signals |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:13 | rwNormal read/write | 0x0 | reserved |
spniden | 12 | rwNormal read/write | 0x0 | allow counting of secure events by performance monitors |
Reserved | 11:8 | roRead-only | 0x0 | reserved. |
awakeup_prog | 7 | rwNormal read/write | 0x0 | Wakeup signal for Programming interface |
Reserved | 6 | rwNormal read/write | 0x0 | reserved. |
Reserved | 5:4 | rwNormal read/write | 0x1 | reserved. |
Reserved | 3:1 | rwNormal read/write | 0x3 | reserved. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved |