Zynq UltraScale+ Devices Register Reference > Module Summary > R5_ROM Module
Module Name | R5_ROM Module |
---|---|
Modules of this Type | CORESIGHT_R5_ROM |
Base Address | 0x00FEBE0000 (CORESIGHT_R5_ROM) |
Description | R5 Integration ROM |
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
ENTRY00 | 0x0000000000 | 32 | roRead-only | 0x00010003 | CPU 0 Debug Component |
ENTRY01 | 0x0000000004 | 32 | roRead-only | 0x00012003 | CPU 0 CTI Component |
ENTRY02 | 0x0000000008 | 32 | roRead-only | 0x00018003 | CPU 0 ETM Component |
ENTRY03 | 0x000000000C | 32 | roRead-only | 0x00019003 | CPU 1 Debug Component |
ENTRY04 | 0x0000000010 | 32 | roRead-only | 0x0001C003 | CPU 1 CTI Component |
ENTRY05 | 0x0000000014 | 32 | roRead-only | 0x0001D003 | CPU 1 ETM Component |
DEVID | 0x0000000FC8 | 32 | roRead-only | 0x00000000 | This register indicates the capabilities. |
DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000000 | It provides a debugger with information about the component. |
PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000004 | ROM Peripheral ID 4 |
PIDR5 | 0x0000000FD4 | 32 | roRead-only | 0x00000000 | ROM Peripheral ID 5 |
PIDR6 | 0x0000000FD8 | 32 | roRead-only | 0x00000000 | ROM Peripheral ID 6 |
PIDR7 | 0x0000000FDC | 32 | roRead-only | 0x00000000 | ROM Peripheral ID 7 |
PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x000000B5 | ROM Peripheral ID 0 |
PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x000000B4 | ROM Peripheral ID 1 |
PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x0000000B | ROM Peripheral ID 2 |
PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | ROM Peripheral ID 3 |
CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x0000000D | ROM Component ID 0 |
CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000010 | ROM Component ID 1 |
CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000005 | ROM Component ID 2 |
CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x000000B1 | ROM Component ID 3 |