Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AUD_CH_A_DATA_REG0 (DISPLAY_PORT) Register

AUD_CH_A_DATA_REG0 (DISPLAY_PORT) Register

AUD_CH_A_DATA_REG0 (DISPLAY_PORT) Register Description

Register NameAUD_CH_A_DATA_REG0
Relative Address0x000000C020
Absolute Address 0x00FD4AC020 (DISPLAY_PORT)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAUD_CH_A_DATA_REG0: User data bits 31 to 0

AUD_CH_A_DATA_REG0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
USER_DATA031:0rwNormal read/write0x0-