Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_MISC1 (DISPLAY_PORT) Register

DP_MAIN_STREAM_MISC1 (DISPLAY_PORT) Register

DP_MAIN_STREAM_MISC1 (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_MISC1
Relative Address0x00000001A8
Absolute Address 0x00FD4A01A8 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMAIN_STREAM_MISC1. Miscellaneous stream attributes.Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard.

DP_MAIN_STREAM_MISC1 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0
Y_ONLY_EN 7rwNormal read/write0x0Y Only Enable
Reserved 6:3rwNormal read/write0x0
STEREO_VID_ATTR 2:1rwNormal read/write0x0Stereo video attribute
Reserved 0rwNormal read/write0x0