Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > V_BLEND_BG_CLR_0 (DISPLAY_PORT) Register

V_BLEND_BG_CLR_0 (DISPLAY_PORT) Register

V_BLEND_BG_CLR_0 (DISPLAY_PORT) Register Description

Register NameV_BLEND_BG_CLR_0
Relative Address0x000000A000
Absolute Address 0x00FD4AA000 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionV_BLEND_BG_CLR_0: Sets background color of the layers

V_BLEND_BG_CLR_0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:12razRead as zero0x0
CLR011:0rwNormal read/write0x0Set R/Cr Value