Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > APU_PWR_STATUS_INIT (PMU_GLOBAL) Register
Register Name | APU_PWR_STATUS_INIT |
---|---|
Relative Address | 0x0000000008 |
Absolute Address | 0x00FFD80008 (PMU_GLOBAL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | APU Power Initialization Status. |
Provides a location in the PMU to hold the initialization value for CPUPWRDWNREQ field of the APU PWRCTL register during an FPD power-down. The bit associated with an ACPU is loaded by the PMU ROM code in the CPUPWRDWNREQ field of the PWRCTL register right after the routine releases the reset to the ACPU core after an FP-domain power up. 0 = Normal Cold Reset (Default) 1 = Reset after a Power up after Shutdown Mode.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:4 | roRead-only | 0x0 | reserved |
ACPU3 | 3 | rwNormal read/write | 0x0 | APU3 power cycle process. |
ACPU2 | 2 | rwNormal read/write | 0x0 | APU2 power cycle process. |
ACPU1 | 1 | rwNormal read/write | 0x0 | APU1 power cycle process. |
ACPU0 | 0 | rwNormal read/write | 0x0 | APU0 power cycle process. |