Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module
Module Name | USB3_XHCI Module |
---|---|
Modules of this Type | USB3_0_XHCI, USB3_1_XHCI |
Base Address | 0x00FE200000 (USB3_0_XHCI) 0x00FE300000 (USB3_1_XHCI) |
Description | USB Extensible Host Controller Interface, USB Port 0 XHCI |
Register Name | Address | Width | Type | Reset Value | Description |
---|---|---|---|---|---|
CAPLENGTH | 0x0000000000 | 32 | roRead-only | 0x00000000 | Capability Registers Length Host Controller Operational Registers = Base address + CAPLENGTH where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h. |
HCSPARAMS1 | 0x0000000004 | 32 | roRead-only | 0x00000000 | Structural Parameters 1 Register For register definitions, refer to the xHCI specification. |
HCSPARAMS2 | 0x0000000008 | 32 | roRead-only | 0x00000000 | Structural Parameters 2 Register For register definitions, refer to the xHCI specification. |
HCSPARAMS3 | 0x000000000C | 32 | roRead-only | 0x00000000 | Structural Parameters 3 Register For register definitions, refer to the xHCI specification. |
HCCPARAMS1 | 0x0000000010 | 32 | roRead-only | 0x0238F66D | Capability Parameters 1 Register For register definitions, refer to the xHCI specification. |
DBOFF | 0x0000000014 | 32 | roRead-only | 0x00000000 | Doorbell Offset Register For register definitions, refer to the xHCI specification. |
RTSOFF | 0x0000000018 | 32 | roRead-only | 0x00000000 | Runtime Register Space Offset Register |
HCCPARAMS2 | 0x000000001C | 32 | roRead-only | 0x0000000B | Host Controller Capability Parameters 2 For register definitions, refer to the xHCI specification. |
USBCMD | 0x0000000020 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
USBSTS | 0x0000000024 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USB Status Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
PAGESIZE | 0x0000000028 | 32 | roRead-only | 0x00000000 | Page Size Register Bit Definitions Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received. A Notification Enable (Nx, where x = 0 to 15) flag is defined for each of the 16 possible device notification types. If a flag is set for a specific notification type, a Device Notification Event is generated when the respective notification packet is received. After reset, all notifications are disabled. This register is written as a Dword. Byte writes produce undefined results. |
DNCTRL | 0x0000000034 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Notification Register Bit Definitions For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
CRCR_LO | 0x0000000038 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | CRCR_LO For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
CRCR_HI | 0x000000003C | 32 | rwNormal read/write | 0x00000000 | CRCR_HI |
DCBAAP_LO | 0x0000000050 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DCBAAP_LO |
DCBAAP_HI | 0x0000000054 | 32 | rwNormal read/write | 0x00000000 | DCBAAP_HI For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
CONFIG | 0x0000000058 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Configure Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). |
PORTSC_20 | 0x0000000420 | 32 | mixedMixed types. See bit-field details. | 0x000002A0 | Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC |
PORTPMSC_20 | 0x0000000424 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
PORTLI_20 | 0x0000000428 | 32 | roRead-only | 0x00000000 | Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
PORTHLPMC_20 | 0x000000042C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
PORTSC_30 | 0x0000000430 | 32 | mixedMixed types. See bit-field details. | 0x000002A0 | Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC - WPR |
PORTPMSC_30 | 0x0000000434 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
PORTLI_30 | 0x0000000438 | 32 | roRead-only | 0x00000000 | Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
PORTHLPMC_30 | 0x000000043C | 32 | roRead-only | 0x00000000 | USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
MFINDEX | 0x0000000440 | 32 | roRead-only | 0x00000000 | Microframe Index Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
RsvdZ | 0x0000000444 | 32 | roRead-only | 0x00000000 | RsvdZ For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
IMAN_0 | 0x0000000460 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupter Management Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 0 of an array of 4. |
IMOD_0 | 0x0000000464 | 32 | rwNormal read/write | 0x00000FA0 | Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions. To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric. Instance 0 of an array of 4. |
ERSTSZ_0 | 0x0000000468 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 0 of an array of 4. |
RsvdP_0 | 0x000000046C | 32 | roRead-only | 0x00000000 | RsvdP Instance 0 of an array of 4. |
ERSTBA_LO_0 | 0x0000000470 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERSTBA_LO Instance 0 of an array of 4. |
ERSTBA_HI_0 | 0x0000000474 | 32 | rwNormal read/write | 0x00000000 | ERSTBA_HI Instance 0 of an array of 4. |
ERDP_LO_0 | 0x0000000478 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERDP_LO For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 0 of an array of 4. |
ERDP_HI_0 | 0x000000047C | 32 | rwNormal read/write | 0x00000000 | ERDP_HI Instance 0 of an array of 4. |
IMAN_1 | 0x0000000480 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupter Management Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 1 of an array of 4. |
IMOD_1 | 0x0000000484 | 32 | rwNormal read/write | 0x00000FA0 | Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions. To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric. Instance 1 of an array of 4. |
ERSTSZ_1 | 0x0000000488 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 1 of an array of 4. |
RsvdP_1 | 0x000000048C | 32 | roRead-only | 0x00000000 | RsvdP Instance 1 of an array of 4. |
ERSTBA_LO_1 | 0x0000000490 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERSTBA_LO Instance 1 of an array of 4. |
ERSTBA_HI_1 | 0x0000000494 | 32 | rwNormal read/write | 0x00000000 | ERSTBA_HI Instance 1 of an array of 4. |
ERDP_LO_1 | 0x0000000498 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERDP_LO For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 1 of an array of 4. |
ERDP_HI_1 | 0x000000049C | 32 | rwNormal read/write | 0x00000000 | ERDP_HI Instance 1 of an array of 4. |
IMAN_2 | 0x00000004A0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupter Management Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 2 of an array of 4. |
IMOD_2 | 0x00000004A4 | 32 | rwNormal read/write | 0x00000FA0 | Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions. To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric. Instance 2 of an array of 4. |
ERSTSZ_2 | 0x00000004A8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 2 of an array of 4. |
RsvdP_2 | 0x00000004AC | 32 | roRead-only | 0x00000000 | RsvdP Instance 2 of an array of 4. |
ERSTBA_LO_2 | 0x00000004B0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERSTBA_LO Instance 2 of an array of 4. |
ERSTBA_HI_2 | 0x00000004B4 | 32 | rwNormal read/write | 0x00000000 | ERSTBA_HI Instance 2 of an array of 4. |
ERDP_LO_2 | 0x00000004B8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERDP_LO For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 2 of an array of 4. |
ERDP_HI_2 | 0x00000004BC | 32 | rwNormal read/write | 0x00000000 | ERDP_HI Instance 2 of an array of 4. |
IMAN_3 | 0x00000004C0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupter Management Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 3 of an array of 4. |
IMOD_3 | 0x00000004C4 | 32 | rwNormal read/write | 0x00000FA0 | Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions. To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric. Instance 3 of an array of 4. |
ERSTSZ_3 | 0x00000004C8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 3 of an array of 4. |
RsvdP_3 | 0x00000004CC | 32 | roRead-only | 0x00000000 | RsvdP Instance 3 of an array of 4. |
ERSTBA_LO_3 | 0x00000004D0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERSTBA_LO Instance 3 of an array of 4. |
ERSTBA_HI_3 | 0x00000004D4 | 32 | rwNormal read/write | 0x00000000 | ERSTBA_HI Instance 3 of an array of 4. |
ERDP_LO_3 | 0x00000004D8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ERDP_LO For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Instance 3 of an array of 4. |
ERDP_HI_3 | 0x00000004DC | 32 | rwNormal read/write | 0x00000000 | ERDP_HI Instance 3 of an array of 4. |
DB0 | 0x00000004E0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB1 | 0x00000004E4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB2 | 0x00000004E8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB3 | 0x00000004EC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB4 | 0x00000004F0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB5 | 0x00000004F4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB6 | 0x00000004F8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB7 | 0x00000004FC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB8 | 0x0000000500 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB9 | 0x0000000504 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB10 | 0x0000000508 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB11 | 0x000000050C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB12 | 0x0000000510 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB13 | 0x0000000514 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB14 | 0x0000000518 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB15 | 0x000000051C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB16 | 0x0000000520 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB17 | 0x0000000524 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB18 | 0x0000000528 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB19 | 0x000000052C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB20 | 0x0000000530 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB21 | 0x0000000534 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB22 | 0x0000000538 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB23 | 0x000000053C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB24 | 0x0000000540 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB25 | 0x0000000544 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB26 | 0x0000000548 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB27 | 0x000000054C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB28 | 0x0000000550 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB29 | 0x0000000554 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB30 | 0x0000000558 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB31 | 0x000000055C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB32 | 0x0000000560 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB33 | 0x0000000564 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB34 | 0x0000000568 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB35 | 0x000000056C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB36 | 0x0000000570 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB37 | 0x0000000574 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB38 | 0x0000000578 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB39 | 0x000000057C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB40 | 0x0000000580 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB41 | 0x0000000584 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB42 | 0x0000000588 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB43 | 0x000000058C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB44 | 0x0000000590 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB45 | 0x0000000594 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB46 | 0x0000000598 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB47 | 0x000000059C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB48 | 0x00000005A0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB49 | 0x00000005A4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB50 | 0x00000005A8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB51 | 0x00000005AC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB52 | 0x00000005B0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB53 | 0x00000005B4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB54 | 0x00000005B8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB55 | 0x00000005BC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB56 | 0x00000005C0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB57 | 0x00000005C4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB58 | 0x00000005C8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB59 | 0x00000005CC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB60 | 0x00000005D0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB61 | 0x00000005D4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB62 | 0x00000005D8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
DB63 | 0x00000005DC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Doorbell Register Bit Field Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended. |
USBLEGSUP | 0x00000008E0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USBLEGSUP |
USBLEGCTLSTS | 0x00000008E4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | USBLEGCTLSTS |
SUPTPRT2_DW0 | 0x00000008F0 | 32 | roRead-only | 0x02000402 | SUPTPRT2_DW0 |
SUPTPRT2_DW1 | 0x00000008F4 | 32 | roRead-only | 0x20425355 | Register SUPTPRT2_DW1 |
SUPTPRT2_DW2 | 0x00000008F8 | 32 | roRead-only | 0x00080201 | xHCI Supported Protocol Capability_ Data Word 2 For a description of other register fields, see section 7.2 of the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
SUPTPRT2_DW3 | 0x00000008FC | 32 | roRead-only | 0x00000000 | Register SUPTPRT2_DW3 |
SUPTPRT3_DW0 | 0x0000000900 | 32 | roRead-only | 0x03000002 | Register SUPTPRT3_DW0 |
SUPTPRT3_DW1 | 0x0000000904 | 32 | roRead-only | 0x20425355 | Register SUPTPRT3_DW1 |
SUPTPRT3_DW2 | 0x0000000908 | 32 | roRead-only | 0x00000002 | SUPTPRT3_DW2 For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
SUPTPRT3_DW3 | 0x000000090C | 32 | roRead-only | 0x00000000 | SUPTPRT3_DW3 |
DCID | 0x0000000910 | 32 | roRead-only | 0x00000000 | DCID |
DCDB | 0x0000000914 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Register DCDB |
DCERSTSZ | 0x0000000918 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DCERSTSZ |
DCERSTBA_LO | 0x0000000920 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DCERSTBA_LO |
DCERSTBA_HI | 0x0000000924 | 32 | rwNormal read/write | 0x00000000 | Register DCERSTBA_HI |
DCERDP_LO | 0x0000000928 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DCERDP_LO |
DCERDP_HI | 0x000000092C | 32 | rwNormal read/write | 0x00000000 | DCERDP_HI |
DCCTRL | 0x0000000930 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DCCTRL |
DCST | 0x0000000934 | 32 | roRead-only | 0x00000000 | DCST |
DCPORTSC | 0x0000000938 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Register DCPORTSC |
DCCP_LO | 0x0000000940 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DCCP_LO |
DCCP_HI | 0x0000000944 | 32 | rwNormal read/write | 0x00000000 | Register DCCP_HI |
DCDDI1 | 0x0000000948 | 32 | rwNormal read/write | 0x00000000 | Register DCDDI1 |
DCDDI2 | 0x000000094C | 32 | rwNormal read/write | 0x00000000 | Register DCDDI2 |
GSBUSCFG0 | 0x000000C100 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the master bus, which may be configured as AHB, AXI, or Native. Options include burst length and cache type (bufferable/posted, cacheable/snoop, and so on). The application can program this register upon power-on, or a change in mode of operation after the DMA engine is halted. xHCI Register Power-On Value: The standard xHCI driver does not access this register. |
GSBUSCFG1 | 0x000000C104 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: The standard xHCI driver does not access this register. |
GTXTHRCFG | 0x000000C108 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Tx Threshold Control Register For more information on - Using this register, refer to Architecture Details chapter. - Selecting values for the fields of this register. Note: - All the fields in GTXTHRCFG register are valid only in Host mode. - GTXTHRCFG register is not applicable for Debug Target. - GTXTHRCFG register is not applicable in USB 2.0-only mode. |
GRXTHRCFG | 0x000000C10C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Rx Threshold Control Register In a normal case, a Tx burst starts as soon as one packet is prefetched; an Rx burst starts as soon as 1-packet space is available. This works well as long as the system bus is faster than the USB 3.0 bus (a 1024-bytes packet takes ~2.2 microseconds on the USB bus in SS mode). If the system bus latency is larger than 2.2 microseconds to access a 1024-byte packet, then starting a burst on 1-packet condition leads to an early abort of the burst causing unnecessary performance reduction. To avoid underrun and overrun during the burst, in a high-latency bus system (like USB), threshold and burst size control is provided through GTXTHRCFG and GRXTHRCFG registers. Bit [29] of the GTXTHRCFG and GRXTHRCFG registers enables this feature. For more information on - Using this register, refer to Architecture Details chapter. - Selecting values for the fields of this register. Note: - GRXTHRCFG register is not applicable for Debug Target. - GRXTHRCFG register is not applicable in USB 2.0-only mode. |
GCTL | 0x000000C110 | 32 | rwNormal read/write | 0x00693004 | Global Core Control Register Note: When Hibernation is not enabled, you can write any value to GblHibernationEn. It always returns 0 when read. |
GPMSTS | 0x000000C114 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Power Management Status Register This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information, and is for use only for debugging purposes. This register is not applicable in USB 2.0-only mode. |
GSTS | 0x000000C118 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Status Register |
GUCTL1 | 0x000000C11C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global User Control Register 1 |
GSNPSID | 0x000000C120 | 32 | roRead-only | 0x5533290A | Global ID Register This is a read-only register that contains the release number of the core. |
GGPIO | 0x000000C124 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global General Purpose Input/Output Register The application can use this register for general purpose input and output ports or for debugging. |
GUID | 0x000000C128 | 32 | rwNormal read/write | 0x12345678 | Global User ID Register This is a read/write register containing the User ID. This register can be used in the following ways: - To store the version or revision of your system; - To store hardware configurations that are outside the core; - As a scratch register. |
GUCTL | 0x000000C12C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global User Control Register: This register provides a few options for the software to control the core behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices. |
GBUSERRADDRLO | 0x000000C130 | 32 | roRead-only | 0x00000000 | Gobal SoC Bus Error Address Register - Low This is an alternate register for the GBUSERRADDR register. |
GBUSERRADDRHI | 0x000000C134 | 32 | roRead-only | 0x00000000 | Gobal SoC Bus Error Address Register - High This is an alternate register for the GBUSERRADDR register. |
GPRTBIMAPLO | 0x000000C138 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global SS Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP register. Note: For reset values, refer to the corresponding values in the GPRTBIMAP register. |
GPRTBIMAPHI | 0x000000C13C | 32 | roRead-only | 0x00000000 | Global SS Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP register. Note: For reset values, refer to the corresponding values in the GPRTBIMAP register. |
GHWPARAMS0 | 0x000000C140 | 32 | roRead-only | 0x4020404A | Global Hardware Parameter Register 0 |
GHWPARAMS1 | 0x000000C144 | 32 | roRead-only | 0x8262493B | Global Hardware Parameter Register 1 |
GHWPARAMS2 | 0x000000C148 | 32 | roRead-only | 0x12345678 | Global Hardware Parameter Register 2 |
GHWPARAMS3 | 0x000000C14C | 32 | roRead-only | 0x0618C089 | Global Hardware Parameter Register 3 |
GHWPARAMS4 | 0x000000C150 | 32 | roRead-only | 0x47822004 | Global Hardware Parameter Register 4 |
GHWPARAMS5 | 0x000000C154 | 32 | roRead-only | 0x04204108 | Global Hardware Parameter Register 5 |
GHWPARAMS6 | 0x000000C158 | 32 | roRead-only | 0x07BAAC20 | Global Hardware Parameter Register 6 |
GHWPARAMS7 | 0x000000C15C | 32 | roRead-only | 0x030807D6 | Global Hardware Parameter Register 7 |
GDBGFIFOSPACE | 0x000000C160 | 32 | mixedMixed types. See bit-field details. | 0x00420000 | Global Debug Queue/FIFO Space Available Register Bit Bash test should not be done on this debug register. |
GDBGLTSSM | 0x000000C164 | 32 | roRead-only | 0x01000442 | Global Debug LTSSM Register In multi-port host configuration, the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be done on this debug register. |
GDBGLNMCC | 0x000000C168 | 32 | roRead-only | 0x00000000 | Global Debug LNMCC Register Bit Bash test should not be done on this debug register. |
GDBGBMU | 0x000000C16C | 32 | roRead-only | 0x00000000 | Global Debug BMU Register Bit Bash test should not be done on this debug register. |
GDBGLSPMUX_HST | 0x000000C170 | 32 | mixedMixed types. See bit-field details. | 0x003F0000 | Global Debug LSP MUX Register - Host This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined). Bit Bash test should not be done on this debug register. |
GDBGLSP | 0x000000C174 | 32 | roRead-only | 0x00000000 | Global Debug LSP Register This register is for internal debug purposes only. This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined). Bit Bash test should not be done on this debug register. |
GDBGEPINFO0 | 0x000000C178 | 32 | roRead-only | 0x00000000 | Global Debug Endpoint Information Register 0 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined). Bit Bash test should not be done on this debug register. |
GDBGEPINFO1 | 0x000000C17C | 32 | roRead-only | 0x00800000 | Global Debug Endpoint Information Register 1 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined). Bit Bash test should not be done on this debug register. |
GPRTBIMAP_HSLO | 0x000000C180 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global High-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_HS register. Note: For reset values, refer to the corresponding values in the GPRTBIMAP_HS register. |
GPRTBIMAP_HSHI | 0x000000C184 | 32 | roRead-only | 0x00000000 | Global High-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_HS register. Note: For reset values, refer to the corresponding values in the GPRTBIMAP register. |
GPRTBIMAP_FSLO | 0x000000C188 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Full-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_FS register. Note: For reset values, refer to the corresponding values in the GPRTBIMAP_FS register. |
GPRTBIMAP_FSHI | 0x000000C18C | 32 | roRead-only | 0x00000000 | Global Full-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_FS register. Note: For reset values, refer to the corresponding values in the GPRTBIMAP_FS register. |
Reserved_94 | 0x000000C194 | 32 | roRead-only | 0x00000000 | Future Register |
Reserved_98 | 0x000000C198 | 32 | roRead-only | 0x00000000 | Future Register |
GUSB2PHYCFG | 0x000000C200 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either the SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are implemented. |
GUSB2I2CCTL | 0x000000C240 | 32 | roRead-only | 0x00000000 | Reserved Register |
GUSB2PHYACC_ULPI | 0x000000C280 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global USB 2.0 UTMI PHY Vendor Control Register The application used this register to access PHY registers. For an ULPI PHY, the core uses the ULPI interface for PHY register access. The application sets the Vendor Control register for PHY register access and times the PHY register access. The application polls the VStatus Done bit in this register for the completion of the PHY register access. In Device-only configurations, only one register is needed. In Host mode, per-port registers are implemented |
GUSB3PIPECTL | 0x000000C2C0 | 32 | mixedMixed types. See bit-field details. | 0x010C0002 | Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode, registers are implemented for each port. Note: - GUSB3PIPECTLn registers are not applicable for USB 2.0-only mode. |
GTXFIFOSIZ0 | 0x000000C300 | 32 | rwNormal read/write | 0x00000042 | Global Transmit FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device IN Endpoints, number of Host Bus Instances, and presence of Debug Capability. The register default values for each mode are assigned based on the maximum packet size, number of packets to be buffered, speed of host bus instance, bus latency, and mode of operation (host, device, or, DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values. For the debug capability mode, the currently mapped EP0 IN and EP1 IN TxFIFO numbers can be read from the GFIFOPRIDBC register. For OTG mode of operation, when the core is transitioning to host mode, program GTXFIFOSIZ register to the correct value only after OCTL.PeriMode is programmed to 1b0. |
GTXFIFOSIZ1 | 0x000000C304 | 32 | rwNormal read/write | 0x00420184 | Register GTXFIFOSIZ 1 |
GTXFIFOSIZ2 | 0x000000C308 | 32 | rwNormal read/write | 0x01C60184 | Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words. |
GTXFIFOSIZ3 | 0x000000C30C | 32 | rwNormal read/write | 0x034A0184 | Register GTXFIFOSIZ 3 |
GTXFIFOSIZ4 | 0x000000C310 | 32 | rwNormal read/write | 0x04CE0184 | Register GTXFIFOSIZ 4 |
GTXFIFOSIZ5 | 0x000000C314 | 32 | rwNormal read/write | 0x06520184 | Register GTXFIFOSIZ 5 |
GRXFIFOSIZ0 | 0x000000C380 | 32 | rwNormal read/write | 0x00000185 | Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus Instances and presence of Debug Capability; device mode requires only one RxFIFO. The register default values for each mode are assigned based on the maximum packet size, number of packets to be buffered, speed of the host bus instance, bus latency, and mode of operation (host, device, or DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values. For the debug capability mode, the currently mapped RxFIFO number can be read from the GFIFOPRIDBC register. |
GRXFIFOSIZ1 | 0x000000C384 | 32 | rwNormal read/write | 0x01850000 | Register |
GRXFIFOSIZ2 | 0x000000C388 | 32 | rwNormal read/write | 0x01850000 | Register |
GEVNTADRLO_0 | 0x000000C400 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register. Instance 0 of an array of 4. |
GEVNTADRHI_0 | 0x000000C404 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register. Instance 0 of an array of 4. |
GEVNTSIZ_0 | 0x000000C408 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 0 of an array of 4. |
GEVNTCOUNT_0 | 0x000000C40C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed. Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 0 of an array of 4. |
GEVNTADRLO_1 | 0x000000C410 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register. Instance 1 of an array of 4. |
GEVNTADRHI_1 | 0x000000C414 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register. Instance 1 of an array of 4. |
GEVNTSIZ_1 | 0x000000C418 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 1 of an array of 4. |
GEVNTCOUNT_1 | 0x000000C41C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed. Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 1 of an array of 4. |
GEVNTADRLO_2 | 0x000000C420 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register. Instance 2 of an array of 4. |
GEVNTADRHI_2 | 0x000000C424 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register. Instance 2 of an array of 4. |
GEVNTSIZ_2 | 0x000000C428 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 2 of an array of 4. |
GEVNTCOUNT_2 | 0x000000C42C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed. Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 2 of an array of 4. |
GEVNTADRLO_3 | 0x000000C430 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register. Instance 3 of an array of 4. |
GEVNTADRHI_3 | 0x000000C434 | 32 | rwNormal read/write | 0x00000000 | Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register. Instance 3 of an array of 4. |
GEVNTSIZ_3 | 0x000000C438 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 3 of an array of 4. |
GEVNTCOUNT_3 | 0x000000C43C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed. Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 3 of an array of 4. |
GHWPARAMS8 | 0x000000C600 | 32 | roRead-only | 0x000007BA | Global Hardware Parameters This register contains the hardware configuration options selected during implementation. |
GTXFIFOPRIDEV | 0x000000C610 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Device TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high, 0: low) of each TXFIFO[n]. When multiple TXFIFOs compete for DMA service at a given time (that is, multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner: - 1. High-priority TXFIFOs are granted access using round-robin arbitration - 2. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full). For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed. When configuring periodic IN endpoints, software must set register bit[n]=1, where n is the TXFIFO assignment. This ensures that the DMA for isochronous or interrupt IN endpoints are prioritized over bulk or control IN endpoints. This register is present only when the core is configured to operate in the device mode (includes DRD and OTG modes). The register size corresponds to the number of Device IN endpoints. Note - Since the device mode uses only one RXFIFO, there is no Device RXFIFO DMA Priority Register. |
GTXFIFOPRIHST | 0x000000C618 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Host TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of TXFIFO[n] within a speed group. When multiple TXFIFOs compete for DMA service at a given time (i.e., multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner: - 1. Among the FIFOs in the same speed group (SS or HS/FSLS): a. High-priority TXFIFOs are granted access using round-robin arbitration b. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full). - 2. The TX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register. For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed. This register is present only when the core is configured to operate in the host mode (includes DRD and OTG modes). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS). |
GRXFIFOPRIHST | 0x000000C61C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Host RX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of RXFIFO[n] within a speed group. When multiple RXFIFOs compete for DMA service at a given time (i.e., multiple RXQs contain RX DMA requests and their corresponding RXFIFOs have data available), the RX DMA arbiter grants access on a packet-basis in the following manner: - 1. Among the FIFOs in the same speed group (SS or HS/FSLS): a. High-priority RXFIFOs are granted access using round-robin arbitration b. Low-priority RXFIFOs are granted access using round-robin arbitration only after high-priority RXFIFOs have no further processing to do (that is, either the RXQs are empty or the corresponding RXFIFOs do not have the required data). - 2. The RX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register. For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed. This register is present only when the core is configured to operate in the host mode (includes DRD and OTG modes). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS). |
GFIFOPRIDBC | 0x000000C620 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Host Debug Capability DMA Priority Register This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and TXFIFO DMA priority registers, when the DbC mode is enabled. Priority settings are specified in relation to the low-priority SS speed group: - 1. Normal priority indicates that the DbC FIFOs are considered identical to the Host SS low-priority FIFOs. - 2. Low priority indicates that the DbC FIFOs are considered to have lower priority than all Host SS FIFOs. - 3. High priority indicates that the DbC FIFOs are considered higher priority than the Host SS low-priority FIFOs but lower priority than the Host SS high-priority FIFOs. This register is present only when the core is configured to operate in Host Debug Capability (DbC) mode. |
GDMAHLRATIO | 0x000000C624 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low Priority Ratio grants as indicated in the register separately for TX and RX. To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is 4. SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, and so on. If FIFOs from both speed groups are not requesting access simultaneously then, - if SS got grants 4 out of the last 4 times, then HS/FSLS get the priority on any future request. - if HS/FSLS got the grant last time, SS gets the priority on the next request. - if there is a valid request on either SS or HS/FSLS, a grant is always awarded; there is no idle. This register is present if the core is configured to operate in host mode (includes DRD and OTG). |
GFLADJ | 0x000000C630 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an option to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely from the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. |
DCFG | 0x000000C700 | 32 | mixedMixed types. See bit-field details. | 0x00000800 | Device Configuration Register. This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. |
DCTL | 0x000000C704 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Control Register Note: When Hibernation is not enabled using GCTL.GblHibernationEn field, - you can write any value to CSS, CRS, L1HibernationEn, and KeepConnect fields - L1HibernationEn, and KeepConnect fields always return 0 when read in this hibernation-disabled state |
DEVTEN | 0x000000C708 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Event Enable Register This register controls the generation of device-specific events. If an enable bit is set to 0, the event will not be generated. |
DSTS | 0x000000C70C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled, RSS and SSS fields always return 0 when read. |
DGCMDPAR | 0x000000C710 | 32 | rwNormal read/write | 0x00000000 | Device Generic Command Parameter Register This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register. |
DGCMD | 0x000000C714 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Generic Command Register This register enables software to program the core using a single generic command interface to send link management packets and notifications. This register contains command, control, and status fields relevant to the current generic command, while the DGCMDPAR register provides the command parameter. |
DALEPENA | 0x000000C720 | 32 | rwNormal read/write | 0x00000000 | Device Active USB Endpoint Enable Register. This register indicates whether a USB endpoint is active in a given configuration or interface. |
Rsvd0 | 0x000000C724 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd1 | 0x000000C728 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd2 | 0x000000C72C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd3 | 0x000000C730 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd4 | 0x000000C734 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd5 | 0x000000C738 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd6 | 0x000000C73C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd7 | 0x000000C740 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd8 | 0x000000C744 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd9 | 0x000000C748 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd10 | 0x000000C74C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd11 | 0x000000C750 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd12 | 0x000000C754 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd13 | 0x000000C758 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd14 | 0x000000C75C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd15 | 0x000000C760 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd16 | 0x000000C764 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd17 | 0x000000C768 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd18 | 0x000000C76C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd19 | 0x000000C770 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd20 | 0x000000C774 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd21 | 0x000000C778 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd22 | 0x000000C77C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd23 | 0x000000C780 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd24 | 0x000000C784 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd25 | 0x000000C788 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd26 | 0x000000C78C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd27 | 0x000000C790 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd28 | 0x000000C794 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd29 | 0x000000C798 | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd30 | 0x000000C79C | 32 | roRead-only | 0x00000000 | Reserved |
Rsvd31 | 0x000000C7A0 | 32 | roRead-only | 0x00000000 | Reserved |
DEPCMDPAR2_0 | 0x000000C800 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 0 of an array of 12. |
DEPCMDPAR1_0 | 0x000000C804 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 0 of an array of 12. |
DEPCMDPAR0_0 | 0x000000C808 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 0 of an array of 12. |
DEPCMD_0 | 0x000000C80C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 0 of an array of 12. |
DEPCMDPAR2_1 | 0x000000C810 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 1 of an array of 12. |
DEPCMDPAR1_1 | 0x000000C814 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 1 of an array of 12. |
DEPCMDPAR0_1 | 0x000000C818 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 1 of an array of 12. |
DEPCMD_1 | 0x000000C81C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 1 of an array of 12. |
DEPCMDPAR2_2 | 0x000000C820 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 2 of an array of 12. |
DEPCMDPAR1_2 | 0x000000C824 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 2 of an array of 12. |
DEPCMDPAR0_2 | 0x000000C828 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 2 of an array of 12. |
DEPCMD_2 | 0x000000C82C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 2 of an array of 12. |
DEPCMDPAR2_3 | 0x000000C830 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 3 of an array of 12. |
DEPCMDPAR1_3 | 0x000000C834 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 3 of an array of 12. |
DEPCMDPAR0_3 | 0x000000C838 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 3 of an array of 12. |
DEPCMD_3 | 0x000000C83C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 3 of an array of 12. |
DEPCMDPAR2_4 | 0x000000C840 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 4 of an array of 12. |
DEPCMDPAR1_4 | 0x000000C844 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 4 of an array of 12. |
DEPCMDPAR0_4 | 0x000000C848 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 4 of an array of 12. |
DEPCMD_4 | 0x000000C84C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 4 of an array of 12. |
DEPCMDPAR2_5 | 0x000000C850 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 5 of an array of 12. |
DEPCMDPAR1_5 | 0x000000C854 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 5 of an array of 12. |
DEPCMDPAR0_5 | 0x000000C858 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 5 of an array of 12. |
DEPCMD_5 | 0x000000C85C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 5 of an array of 12. |
DEPCMDPAR2_6 | 0x000000C860 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 6 of an array of 12. |
DEPCMDPAR1_6 | 0x000000C864 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 6 of an array of 12. |
DEPCMDPAR0_6 | 0x000000C868 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 6 of an array of 12. |
DEPCMD_6 | 0x000000C86C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 6 of an array of 12. |
DEPCMDPAR2_7 | 0x000000C870 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 7 of an array of 12. |
DEPCMDPAR1_7 | 0x000000C874 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 7 of an array of 12. |
DEPCMDPAR0_7 | 0x000000C878 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 7 of an array of 12. |
DEPCMD_7 | 0x000000C87C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 7 of an array of 12. |
DEPCMDPAR2_8 | 0x000000C880 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 8 of an array of 12. |
DEPCMDPAR1_8 | 0x000000C884 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 8 of an array of 12. |
DEPCMDPAR0_8 | 0x000000C888 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 8 of an array of 12. |
DEPCMD_8 | 0x000000C88C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 8 of an array of 12. |
DEPCMDPAR2_9 | 0x000000C890 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 9 of an array of 12. |
DEPCMDPAR1_9 | 0x000000C894 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 9 of an array of 12. |
DEPCMDPAR0_9 | 0x000000C898 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 9 of an array of 12. |
DEPCMD_9 | 0x000000C89C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 9 of an array of 12. |
DEPCMDPAR2_10 | 0x000000C8A0 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 10 of an array of 12. |
DEPCMDPAR1_10 | 0x000000C8A4 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 10 of an array of 12. |
DEPCMDPAR0_10 | 0x000000C8A8 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 10 of an array of 12. |
DEPCMD_10 | 0x000000C8AC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 10 of an array of 12. |
DEPCMDPAR2_11 | 0x000000C8B0 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command. Instance 11 of an array of 12. |
DEPCMDPAR1_11 | 0x000000C8B4 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 11 of an array of 12. |
DEPCMDPAR0_11 | 0x000000C8B8 | 32 | rwNormal read/write | 0x00000000 | Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 11 of an array of 12. |
DEPCMD_11 | 0x000000C8BC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information. Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 11 of an array of 12. |
OCFG | 0x000000CC00 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | OTG Configuration Register This register specifies the HNP and SRP capability of the controller |
OCTL | 0x000000CC04 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | OTG Control Register The OTG Control register controls the behavior of the OTG function of the core. |
OEVT | 0x000000CC08 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | OTG Events Register Any event set in this register will cause otg_interrupt signal to go high. Writing 1b1 to the event information bit in this register clears the register bit and the associated interrupt. The otg_interrupt signal goes low when there are no more pending OTG events. |
OEVTEN | 0x000000CC0C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | OTG Events Enable Register Setting a bit in this register enables the generation of corresponding events in OEVT and assertion of otg_interrupt due to this event. When the enable bit is 1b0, the event is not be set in OEVT and otg_interrupt is not asserted due to this event. |
OSTS | 0x000000CC10 | 32 | roRead-only | 0x00000000 | OTG Status Register The OTG Status Register reflects the status of the OTG function of the core. |
ADPEVT | 0x000000CC28 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ADP Event Register |