Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > PMCGCR1 (SMMU500) Register

PMCGCR1 (SMMU500) Register

PMCGCR1 (SMMU500) Register Description

Register NamePMCGCR1
Relative Address0x0000003804
Absolute Address 0x00FD803804 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x04010000
DescriptionControls Counter group behavior.

PMCGCR1 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CGNC27:24roRead-only0x4Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SIDG22:16roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
X12rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
E11rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CBAEN10rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TCEFCFG 9:8rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NDX 3:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details