Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TM_E_ILL9 (SERDES) Register

L0_TM_E_ILL9 (SERDES) Register

L0_TM_E_ILL9 (SERDES) Register Description

Register NameL0_TM_E_ILL9
Relative Address0x0000001944
Absolute Address 0x00FD401944 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L0_TM_E_ILL9 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_E_ILL9_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
UNUSED 7:4roRead-only0x0Value generated by PCW.
ill_bypass_e_lfen 3rwNormal read/write0x0Value generated by PCW.
ill_bypass_e_lfen_val 2rwNormal read/write0x0Value generated by PCW.
ill_bypass_e_cnstgmtrim 1rwNormal read/write0x0Value generated by PCW.
ill_bypass_e_polytim 0rwNormal read/write0x0Value generated by PCW.