Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ECCCLR (DDRC) Register
Register Name | ECCCLR |
---|---|
Relative Address | 0x000000007C |
Absolute Address | 0x00FD07007C (DDRC) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | ECC Clear Register |
This register is dynamic. Dynamic registers can be written at any time during operation.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ecc_clr_uncorr_err_cnt | 3 | wtcReadable, write a 1 to clear | 0x0 | Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCSTAT.ecc_uncorr_err_cnt register is cleared by this operation. When the clear operation is complete, the DDRC automatically clears this bit. |
ecc_clr_corr_err_cnt | 2 | wtcReadable, write a 1 to clear | 0x0 | Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. When the clear operation is complete, the DDRC automatically clears this bit. |
Reserved | 1 | rwNormal read/write | 0x0 | reserved. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved. |