Zynq UltraScale+ Devices Register Reference > Module Summary > ZDMA Module > ZDMA_CH_CTRL0 (ZDMA) Register
Register Name | ZDMA_CH_CTRL0 |
---|---|
Relative Address | 0x0000000110 |
Absolute Address |
0x00FFA80110 (ADMA_CH0) 0x00FFA90110 (ADMA_CH1) 0x00FFAA0110 (ADMA_CH2) 0x00FFAB0110 (ADMA_CH3) 0x00FFAC0110 (ADMA_CH4) 0x00FFAD0110 (ADMA_CH5) 0x00FFAE0110 (ADMA_CH6) 0x00FFAF0110 (ADMA_CH7) 0x00FD500110 (GDMA_CH0) 0x00FD510110 (GDMA_CH1) 0x00FD520110 (GDMA_CH2) 0x00FD530110 (GDMA_CH3) 0x00FD540110 (GDMA_CH4) 0x00FD550110 (GDMA_CH5) 0x00FD560110 (GDMA_CH6) 0x00FD570110 (GDMA_CH7) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000080 |
Description | Channel Control Register 0 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | Reserved for future use |
OVR_FETCH | 7 | rwNormal read/write | 0x1 | 0: DMA channel is not allowed to over-fetch on SRC 1: DMA channel is allowed to over-fetch This field must remain stable while DMA Channel is enabled |
POINT_TYPE | 6 | rwNormal read/write | 0x0 | 0: Simple mode DMA. Descriptor (DMA command) from APB register space. 1: Scatter-gather mode DMA. Descriptor are stored in Memory. This field must remain stable while DMA Channel is enabled |
MODE | 5:4 | rwNormal read/write | 0x0 | 00: Normal read & write DMA (default) 01: Write only (uses data from WR_DMA_DATA*) 10: Read only 11: Reserved for future use This field must remain stable while DMA Channel is enabled |
RATE_CTRL | 3 | rwNormal read/write | 0x0 | Enable/Disable rate control 0: rate control is disabled 1: rate control is enabled, use rate control count to schedule AXI transaction (Read) This field must remain stable while DMA Channel is enabled |
CONT_ADDR | 2 | rwNormal read/write | 0x0 | Coming out of pause 0: use continuous address(calculated from previous DSCR Addr) to fetch next descriptor 1: use address specified in Start Address Register to fetch next descriptor on both SRC & DST side |
CONT | 1 | woWrite-only | 0x0 | Setting to 1 unpause (restarts from current position) the paused DMA SW sets this 1 to trigger. When DMA is unpaused , then hardware clears this bit. SW clear has no effect on it |
Reserved | 0 | razRead as zero | 0x0 | Reserved for future use |