Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > pcap_prog (CSU) Register

pcap_prog (CSU) Register

pcap_prog (CSU) Register Description

Register Namepcap_prog
Relative Address0x0000003000
Absolute Address 0x00FFCA3000 (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPCAP PROG

pcap_prog (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pcfg_prog_b 0rwNormal read/write0x0PROG control to the PL. The PL is reset when this bit is deasserted and will remain in reset until this register is asserted. After PROG is released, wait for PCAP_STATUS[INIT] before sending configuration data.
0x0 - PL in reset
0x1 - PL not in reset