Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_MMU_INT_STATUS (GPU) Register

PP0_MMU_INT_STATUS (GPU) Register

PP0_MMU_INT_STATUS (GPU) Register Description

Register NamePP0_MMU_INT_STATUS
Relative Address0x0000004020
Absolute Address 0x00FD4B4020 (GPU)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionMMU Interrupt Status Register

PP0_MMU_INT_STATUS (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2roRead-only0x0Reserved, read undefined, write as zero
read_bus_error 1roRead-only0x0Read bus error
page_fault 0roRead-only0x0Page fault