Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank2_ctrl3 (IOU_SLCR) Register
Register Name | bank2_ctrl3 |
---|---|
Relative Address | 0x0000000178 |
Absolute Address | 0x00FF180178 (IOU_SLCR) |
Width | 26 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | MIO Bank 2, CMOS input type control. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
schmitt_cmos_n | 25:0 | rwNormal read/write | 0x0 | Select between Schmitt Trigger or CMOS input for MIO pins [52:77]. 0 = CMOS. 1 = Schmitt (hysteresis). Bit [0] controls MIO pin 52. .. Bit [25] controls MIO pin 77. Bits [26] to [31] are reserved. |