Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_DMA Module > DMA_CHANNEL_STAS_Q_LIMIT (AXIPCIE_DMA) Register
Register Name | DMA_CHANNEL_STAS_Q_LIMIT |
---|---|
Relative Address | 0x000000002C |
Absolute Address |
0x00FD0F002C (AXIPCIE_DMA0) 0x00FD0F00AC (AXIPCIE_DMA1) 0x00FD0F012C (AXIPCIE_DMA2) 0x00FD0F01AC (AXIPCIE_DMA3) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Queue Limit Pointer |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
limit | 31:0 | rwNormal read/write | 0x0 | Queue Flow Control - Limit Pointer. Index of the first Queue element still ``owned by software. Incremented by software to give the DMA Channel additional elements to execute. DMA Channel hardware will pause and not utilize queue elements when Q_LIMIT is reached until Q_LIMIT is advanced to provide additional elements to execute. |