Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L0_TXPMA_ST_0 (SERDES) Register

L0_TXPMA_ST_0 (SERDES) Register

L0_TXPMA_ST_0 (SERDES) Register Description

Register NameL0_TXPMA_ST_0
Relative Address0x0000000B00
Absolute Address 0x00FD400B00 (SERDES)
Width32
TyperoRead-only
Reset Value0x00000001
DescriptionRegister value is generated by Vivado PCW.

L0_TXPMA_ST_0 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TXPMA_ST_0_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
TX_phy_mode 7:4roRead-only0x0Value generated by PCW.
TX_phy_gear 3:0roRead-only0x1Value generated by PCW.