Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DRAMTMG14 (DDRC) Register
Register Name | DRAMTMG14 |
---|---|
Relative Address | 0x0000000138 |
Absolute Address | 0x00FD070138 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x000000A0 |
Description | SDRAM Timing Register 14 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
t_xsr | 11:0 | rwNormal read/write | 0xA0 | tXSR: Exit Self Refresh to any command. Program this to the above value divided by 2 and round up to next integer value. Note: Used only for LPDDR3/LPDDR4 mode. |