Zynq UltraScale+ Devices Register Reference > Module Summary > A53_ETM_0 Module > OSLSR (A53_ETM_0) Register
Register Name | OSLSR |
---|---|
Relative Address | 0x0000000304 |
Absolute Address | 0x00FEC40304 (CORESIGHT_A53_ETM_0) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x0000000A |
Description | OS Lock Status Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PRESENT | 3 | roRead-only | 0x1 | Indicates whether the OS Lock is implemented.This bit is RES1, which indicates that the OS Lock is always implemented. |
BIT32 | 2 | roRead-only | 0x0 | Indicates that software must perform a 32-bit write. |
LOCKED | 1 | roRead-only | 0x1 | OS Lock status bit: When the trace unit core power domain is powered down the value is UNKNOWN. The indicates if the trace unit core power domain is powered down. |