Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU Module > CTRL (XPPU) Register
Register Name | CTRL |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FF980000 (LPD_XPPU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Control. |
XPPU enable, parity errors.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:3 | roRead-only | 0x0 | reserved |
APER_PARITY_EN | 2 | rwNormal read/write | 0x0 | Enable parity error checking for the aperture entries {0:400} fetched from the local RAM. 0: disable. 1: enable. |
MID_PARITY_EN | 1 | rwNormal read/write | 0x0 | Enable parity error checking for Master ID entries {0:19} held in local registers. 0: parity errors are ignored. 1: parity errors are flagged in the ISR register. |
ENABLE | 0 | rwNormal read/write | 0x0 | Permission checking. 0: bypass (transactions pass-thru). 1: enable (transactions are validated by the XPPU). |