Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > ERROR_STATUS_1 (PMU_GLOBAL) Register

ERROR_STATUS_1 (PMU_GLOBAL) Register

ERROR_STATUS_1 (PMU_GLOBAL) Register Description

Register NameERROR_STATUS_1
Relative Address0x0000000530
Absolute Address 0x00FFD80530 (PMU_GLOBAL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSystem Errors; Interrupt Clear and Status, Reg 1.

The software can read the status and clear the errors: READ: 0: no error. 1: error detected. WRITE: 0: no effect. 1: clear bit to 0. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers. The system errors can be generated by many areas of the PS and PL. Register is reset only by the PS_POR_B reset signal pin.

ERROR_STATUS_1 (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31wtcReadable, write a 1 to clear0x0reserved.
Reserved30wtcReadable, write a 1 to clear0x0reserved.
Reserved29wtcReadable, write a 1 to clear0x0reserved.
Reserved28wtcReadable, write a 1 to clear0x0reserved.
CSU_SWDT27wtcReadable, write a 1 to clear0x0CSU_SWDT watchdog timeout error.
CLK_MON26wtcReadable, write a 1 to clear0x0Clock Monitor (ClkMon) Error. Selected clock is not within acceptable frequency range. Refer to TRM.
XMPU25:24wtcReadable, write a 1 to clear0x0Protect Unit errors.
Bit [24] is OR of OCM_XMPU, XPPU error signals.
Bit [25] is OR of FPD_XMPU, DDR_MPU error signals.
PWR_SUPPLY23:16wtcReadable, write a 1 to clear0x0Bit [16] is for VCC_PS_LPD.
Bit [17] is for VCC_PS_FPD.
Bit [18] is for VCC_PS_AUX.
Bit [19] is for VCCO_PS_DDR.
Bit [20] is for VCCO_PS_3.
Bit [21] is for VCCO_PS_0.
Bit [22] is for VCCO_PS_1.
Bit [23] is for VCCO_PS_2.
Reserved15:14roRead-only0x0reserved
FPD_SWDT13wtcReadable, write a 1 to clear0x0FPD_SWDT watchdog timeout error.
LPD_SWDT12wtcReadable, write a 1 to clear0x0LPD_SWDT watchdog timeout error.
Reserved11:10roRead-only0x0reserved
RPU_CCF 9wtcReadable, write a 1 to clear0x0RPU Common Cause Failure (CCF) Errors ORed together. Represents one or more errors.
Reserved 8roRead-only0x0reserved
RPU_LS 7:6wtcReadable, write a 1 to clear0x0RPU Lockstep Error detected:
00: no error.
01: lockstep error.
10: lockstep error.
11:
lockstep error.
FPD_TEMP 5wtcReadable, write a 1 to clear0x0FPD Over Temperature sensor, TEMP_FPD_OT from PS SysMon unit.
LPD_TEMP 4wtcReadable, write a 1 to clear0x0LPD Over Temperature sensor, TEMP_LPD_OT from PS SysMon unit.
RPU1 3wtcReadable, write a 1 to clear0x0RPU1 Error including both Correctable and Uncorrectable Errors
RPU0 2wtcReadable, write a 1 to clear0x0RPU0 Error including both Correctable and Uncorrectable Errors
OCM_ECC 1wtcReadable, write a 1 to clear0x0OCM Uncorrectable ECC Error.
DDR_ECC 0wtcReadable, write a 1 to clear0x0DDR Uncorrectable ECC Error.