Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_capabilities (SDIO) Register
Register Name | reg_capabilities |
---|---|
Relative Address | 0x0000000040 |
Absolute Address |
0x00FF160040 (SD0) 0x00FF170040 (SD1) |
Width | 64 |
Type | roRead-only |
Reset Value | 0x280737EC6481 |
Description | Host controller implementation. |
This register provides the host driver with information specific to the host controller implementation
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
corecfg_spiblkmode | 57 | roRead-only | 0x0 | SPI Block Mode is not supported. |
corecfg_spisupport | 56 | roRead-only | 0x0 | SPI Mode is not supported. |
corecfg_clockmultiplier | 55:48 | roRead-only | 0x0 | Clock multiplier is not supported. |
corecfg_retuningmodes | 47:46 | roRead-only | 0x0 | This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. 00: Mode 1 01: Mode 2 10: Mode 3 11: reserved. There are two re-tuning timings:Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue. |
corecfg_tuningforsdr50 | 45 | roRead-only | 0x1 | SDR50 requires tuning. |
corecfg_retuningtimercnt | 43:40 | roRead-only | 0x8 | This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h: Get information via other source 1h: 1 seconds 2h: 2 seconds 3h: 4 seconds 4h: 8 seconds ------ nh: 2 (n-1) seconds ------ Bh: 1024 seconds Others: reserved |
corecfg_ddriversupport | 38 | roRead-only | 0x0 | Driver Type D (1.8 Signaling) is not supported. |
corecfg_cdriversupport | 37 | roRead-only | 0x0 | Driver Type C (1.8 Signaling) is not supported. |
corecfg_adriversupport | 36 | roRead-only | 0x0 | Driver Type A (for 1.8 Signaling) is not supported. |
corecfg_ddr50support | 34 | roRead-only | 0x1 | DDR50 is supported. |
corecfg_sdr104support | 33 | roRead-only | 0x1 | SDR104 is supported (requires tuning). |
corecfg_sdr50support | 32 | roRead-only | 0x1 | SDR50 is supported; bit 45 indicates SDR50 requires tuning. |
corecfg_slottype | 31:30 | roRead-only | 0x0 | This field indicates usage of a slot by a specific Host System. (A host controller register set is defined perslot.) Embedded slot for one device (01b) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (10b) can be set if Host Controller supports Shared Bus Control register. The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (10b), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System. 00 Removable Card Slot 01 Embedded Slot for One Device 10 Shared Bus Slot 11 Reserved |
corecfg_asynchintrsupport | 29 | roRead-only | 0x1 | Asynchronous Interrupt is supported; refer to SDIO Specification Version 3.00. |
corecfg_64bitsupport | 28 | roRead-only | 0x1 | Host controller supports 64-bit system address. |
corecfg_1p8voltsupport | 26 | roRead-only | 0x1 | Host controller supports 1.8V I/O. |
corecfg_3p0voltsupport | 25 | roRead-only | 0x1 | Host controller supports 3.0V I/O. |
corecfg_3p3voltsupport | 24 | roRead-only | 0x1 | Host controller supports 3.3V I/O. |
corecfg_suspressupport | 23 | roRead-only | 0x1 | Host controller supports Suspend / Resume functionality. |
corecfg_sdmasupport | 22 | roRead-only | 0x1 | SMDA is supported; transfers data between system memory and the host controller. |
corecfg_highspeedsupport | 21 | roRead-only | 0x1 | This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC). 0 High Speed Not Supported 1 High Speed Supported |
corecfg_adma2support | 19 | roRead-only | 0x1 | ADMA2 is supported |
corecfg_8bitsupport | 18 | roRead-only | 0x1 | This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case, refer to Bus Width Preset in the Shared Bus resister. 0 Extended Media Bus Not Supported 1 Extended Media Bus Supported |
corecfg_maxblklength | 17:16 | roRead-only | 0x0 | This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below. 00 512byte 01 1024byte 10 2048byte 11 4096byte |
corecfg_baseclkfreq | 15:8 | roRead-only | 0x64 | (1)6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. 11xx xxxxb Not Supported 0011 1111b 63MHz 0000 0010b 2MHz 0000 0001b 1MHz 0000 0000bGet Information via another method (2)8-bit Base Clock Frequency: This mode is supported by the Host Controller Version 3.00.Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h 1MHz 00h Get Information via another method. If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to the SDCLK Frequency Select in the Clock Control register.) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method. |
corecfg_timeoutclkunit | 7 | roRead-only | 0x1 | Base clock frequency to detect Data Timeout Error is measured in MHz. |
corecfg_timeoutclkfreq | 5:0 | roRead-only | 0x1 | Base clock frequency to detect the Data Timeout Error is 1 to 63 MHz |