Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > USBSTS (USB3_XHCI) Register
Register Name | USBSTS |
---|---|
Relative Address | 0x0000000024 |
Absolute Address |
0x00FE200024 (USB3_0_XHCI) 0x00FE300024 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | USB Status Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:13 | roRead-only | 0x0 | Reserved |
HCE | 12 | roRead-only | 0 | Host Controller Error (HCE) - RO Default = 0. 0 = No internal xHC error conditions exist and 1 = Internal xHC error condition. This flag must be set to indicate that an internal error condition has been detected which requires software to reset and reinitialize the xHC. |
CNR | 11 | roRead-only | 0 | Controller Not Ready (CNR) - RO Default = 1. 0 = Ready and 1 = Not Ready. Software must not write to thes Doorbell or Operational register of the xHC, other than the USBSTS register, until CNR = 0. This flag is set by the xHC after a Chip Hardware Reset and cleared when the xHC is ready to begin accepting register writes. This flag remains cleared (0) until the next Chip Hardware Reset. |
SRE | 10 | wtcReadable, write a 1 to clear | 0 | Save/Restore Error This bit is currently not supported. |
RSS | 9 | roRead-only | 0 | Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller has finished the restore process, it completes the command by setting DSTS.RSS to 0. |
SSS | 8 | roRead-only | 0 | Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process, it completes the command by setting DSTS.SSS to 0. |
Reserved | 7:5 | roRead-only | 0x0 | Reserved |
PCD | 4 | wtcReadable, write a 1 to clear | 0 | Reset Value |
EINT | 3 | wtcReadable, write a 1 to clear | 0 | Reset Value |
HSE | 2 | wtcReadable, write a 1 to clear | 0 | HSE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |
Reserved | 1 | roRead-only | 0x0 | Reserved |
HCH | 0 | roRead-only | 0 | HCH For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. |