Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > ACBDLR15 (DDR_PHY) Register

ACBDLR15 (DDR_PHY) Register

ACBDLR15 (DDR_PHY) Register Description

Register NameACBDLR15
Relative Address0x000000057C
Absolute Address 0x00FD08057C (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAC Bit Delay Line Register 15

ACBDLR15 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:22roRead-only0x0Reserved. Return zeroes on reads.
OEBD21:16rwNormal read/write0x0Delay select for the BDL on OE
Reserved15:14roRead-only0x0Reserved. Return zeroes on reads.
TEBD13:8rwNormal read/write0x0Delay select for the BDL on TE
Reserved 7:6roRead-only0x0Reserved. Return zeroes on reads.
PDRBD 5:0rwNormal read/write0x0Delay select for the BDL on PDR