Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > DEC_CORE_CTRL (VCU_SLCR) Register

DEC_CORE_CTRL (VCU_SLCR) Register

DEC_CORE_CTRL (VCU_SLCR) Register Description

Register NameDEC_CORE_CTRL
Relative Address0x0000000038
Absolute Address 0x00A0040038 (VCU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00001000
DescriptionThis register controls this reference clock

DEC_CORE_CTRL (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLKACT12rwNormal read/write0x1Clock active signal. Switch to 0 to disable the clock
Reserved11:10razRead as zero0x0reserved
DIVISOR0 9:4rwNormal read/write0x06 bit divider
Reserved 3:1razRead as zero0x0reserved
SRCSEL 0rwNormal read/write0x00: clock input from PL to be used as decoder core clock.
1: clock derived from VCU PLL to be used as decoder core clock