Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > CHKR0_CLKA_LOWER (CRL_APB) Register

CHKR0_CLKA_LOWER (CRL_APB) Register

CHKR0_CLKA_LOWER (CRL_APB) Register Description

Register NameCHKR0_CLKA_LOWER
Relative Address0x0000000164
Absolute Address 0x00FF5E0164 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionLower Clock Comparison Threshold.

CHKR0_CLKA_LOWER (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
thrshld31:0rwNormal read/write0x0Lower Threshold. This must be set up before a start bit is set (there is no clock crossing from this bus to the comparison logic.)