Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > REQ_PWRUP_STATUS (PMU_GLOBAL) Register
Register Name | REQ_PWRUP_STATUS |
---|---|
Relative Address | 0x0000000110 |
Absolute Address | 0x00FFD80110 (PMU_GLOBAL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Power-up Request; Interrupt Status and Clear. |
READ: 0: no request. 1: unit power-up requested. WRITE: 0: no effect. 1: clear bit to 0. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:24 | roRead-only | 0x0 | reserved |
PL | 23 | wtcReadable, write a 1 to clear | 0x0 | Programmable Logic, PL. Controlled by external FET via MIO pin. This optional control uses MIO pin [33]. This is PMU signal [6], pmu_psio_gpo [1]. |
FP | 22 | wtcReadable, write a 1 to clear | 0x0 | Full-power Domain, FPD. Controlled by external FET via MIO pin. This optional control uses MIO pin [32]. This is PMU signal [5], pmu_psio_gpo [0]. |
USB1 | 21 | wtcReadable, write a 1 to clear | 0x0 | USB 1. |
USB0 | 20 | wtcReadable, write a 1 to clear | 0x0 | USB 0. |
OCM_Bank3 | 19 | wtcReadable, write a 1 to clear | 0x0 | OCM Bank 3. |
OCM_Bank2 | 18 | wtcReadable, write a 1 to clear | 0x0 | OCM Bank 2. |
OCM_Bank1 | 17 | wtcReadable, write a 1 to clear | 0x0 | OCM Bank 1. |
OCM_Bank0 | 16 | wtcReadable, write a 1 to clear | 0x0 | OCM Bank 0. |
TCM1B | 15 | wtcReadable, write a 1 to clear | 0x0 | RPU core 1, TCM_B. |
TCM1A | 14 | wtcReadable, write a 1 to clear | 0x0 | RPU core 1, TCM_A. |
TCM0B | 13 | wtcReadable, write a 1 to clear | 0x0 | RPU core 0, TCM_B. |
TCM0A | 12 | wtcReadable, write a 1 to clear | 0x0 | RPU core 0, TCM_A. |
Reserved | 11 | roRead-only | 0x0 | reserved |
RPU | 10 | wtcReadable, write a 1 to clear | 0x0 | RPU processors. |
Reserved | 9 | roRead-only | 0x0 | reserved |
Reserved | 8 | roRead-only | 0x0 | reserved |
L2_Bank0 | 7 | wtcReadable, write a 1 to clear | 0x0 | APU L2 Cache. |
Reserved | 6 | roRead-only | 0x0 | reserved |
PP1 | 5 | wtcReadable, write a 1 to clear | 0x0 | GPU Pixel Processor 1. |
PP0 | 4 | wtcReadable, write a 1 to clear | 0x0 | GPU Pixel Processor 0. |
ACPU3 | 3 | wtcReadable, write a 1 to clear | 0x0 | APU core 3. |
ACPU2 | 2 | wtcReadable, write a 1 to clear | 0x0 | APU core 2. |
ACPU1 | 1 | wtcReadable, write a 1 to clear | 0x0 | APU core 1. |
ACPU0 | 0 | wtcReadable, write a 1 to clear | 0x0 | APU core 0. |