Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_NSCR0 (SMMU500) Register

SMMU_NSCR0 (SMMU500) Register

SMMU_NSCR0 (SMMU500) Register Description

Register NameSMMU_NSCR0
Relative Address0x0000000400
Absolute Address 0x00FD800400 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00200001
DescriptionProvides top-level control of the SMMU.

SMMU_NSCR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
WACFG27:26rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
RACFG25:24rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SHCFG23:22rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMCFCFG21roRead-only0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MTCFG20rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MemAttr19:16rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
BSU15:14rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
FB13rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PTM12rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
VMIDPNE11rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
USFCFG10rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GSE 9roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
STALLD 8roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TRANSIENTCFG 7:6rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GCFGFIE 5roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GCFGFRE 4roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GFIE 2rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
GFRE 1rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CLIENTPD 0rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details