Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > STAT (DDRC) Register

STAT (DDRC) Register

STAT (DDRC) Register Description

Register NameSTAT
Relative Address0x0000000004
Absolute Address 0x00FD070004 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionOperating Mode Status Register

STAT (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
selfref_state 9:8roRead-only0x0Self refresh state. This indicates self refresh or self refresh power down state for LPDDR4.
This register is used for frequency change and MRR/MRW access during self refresh.
- 00 - SDRAM is not in Self Refresh.
- 01 - Self refresh 1
- 10 - Self refresh power down
- 11 - Self refresh 2
selfref_type 5:4roRead-only0x0Flags if Self Refresh is entered and if it was under Automatic Self Refresh control only or not.
- 00 - SDRAM is not in Self Refresh. If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress.
- 11 - SDRAM is in Self Refresh and Self Refresh was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
- 10 - SDRAM is in Self Refresh and Self Refresh was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity error.
operating_mode 2:0roRead-only0x0Operating mode.
DDR3 designs:
- 000 - Init
- 001 - Normal
- 010 - Power-down
- 011 - Self refresh
LPDDR3 or DDR4 designs:
- 000 - Init
- 001 - Normal
- 010 - Power-down
- 011 - Self refresh
- 1XX - Deep power-down / Maximum Power Saving Mode
LPDDR4 designs:
- 000 - Init
- 001 - Normal
- 010 - Power-down
- 011 - Self refresh / Self refresh power-down