Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_WB1_GLOBAL_TEST_ENABLE (GPU) Register
Register Name | PP1_WB1_GLOBAL_TEST_ENABLE |
---|---|
Relative Address | 0x000000A224 |
Absolute Address | 0x00FD4BA224 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | WB1 Global Test Enable Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
WB1_GLOBAL_TEST_ENABLE | 0 | rwNormal read/write | 0x0 | Set to one to enable global write-back value testing WB1_SOURCE_SELECT FP_TILEBUF_ENABLE Global test data 1 - Z/Stencil Dont care Stencil 8-bit 2 - ARGB Color 0 Alpha 8-bit 3 - ARGB Color 1 Alpha FP16 |