Zynq UltraScale+ Devices Register Reference > Module Summary > RPU Module > RPU1_CFG (RPU) Register
Register Name | RPU1_CFG |
---|---|
Relative Address | 0x0000000200 |
Absolute Address | 0x00FF9A0200 (RPU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000005 |
Description | Configuration Parameters specific to RPU1 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:4 | razRead as zero | 0x0 | Reserved for future use |
CFGNMFI1 | 3 | rwNormal read/write | 0x0 | Enables non-maskable fast interrupts for R5 _1, Low = en FIQ masking by software High = disable FIQ masking by software |
VINITHI | 2 | rwNormal read/write | 0x1 | High = Start executing form 0xFFFF0000 (OCM) out of reset. Low = Start executing from 0x00000000 (ATCM) out of reset. |
COHERENT | 1 | rwNormal read/write | 0x0 | High = All accesses to peripherals will be through APU Cache Controller. Low = All accesses to peripherals will be direct and without any Cache Choerency with APU. |
nCPUHALT | 0 | rwNormal read/write | 0x1 | nCPUHALT bit can be asserted while the processor is in reset to stop the processor from fetching and executing instructions after coming out of reset.When nCPUHALT has been deasserted to start the processor fetching, nCPUHALT must not be asserted again except when the processor is under processor or power-on reset, that is, nRESET asserted. The processor does not halt if the nCPUHALT pin is asserted while the processor is running low = stops CPU from fetching instructions out of reset, processor is halted High = Processor is running |