Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX3GCR5 (DDR_PHY) Register
Register Name | DX3GCR5 |
---|---|
Relative Address | 0x0000000A14 |
Absolute Address | 0x00FD080A14 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x09090909 |
Description | DATX8 n General Configuration Register 5 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
Reserved | 30:24 | rwNormal read/write | 0x9 | reserved. |
Reserved | 23 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
Reserved | 22:16 | rwNormal read/write | 0x9 | reserved. |
Reserved | 15 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
DXREFISELR1 | 14:8 | rwNormal read/write | 0x9 | Byte Lane internal VREF Select for Rank 1: Selects the generated VREF value for internal byte lane differential IO buffers. |
Reserved | 7 | roRead-only | 0x0 | Reserved. Returns zeros on reads. |
DXREFISELR0 | 6:0 | rwNormal read/write | 0x9 | Byte Lane internal VREF Select for Rank0: Selects the generated VREF value for internal byte lane differential IO buffers. |