Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_SACR (SMMU500) Register

SMMU_SACR (SMMU500) Register

SMMU_SACR (SMMU500) Register Description

Register NameSMMU_SACR
Relative Address0x0000000010
Absolute Address 0x00FD800010 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x04000004
DescriptionProvides IMPLEMENTATION DEFINED functionality.

SMMU_SACR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NORMALIZE27rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CACHE_LOCK26rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PAGESIZE16rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S2CRB_TLBEN10rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
MMUDISB_TLBEN 9rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMTNMB_TLBEN 8rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S1WC2EN 2rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details