Zynq UltraScale+ Devices Register Reference > Module Summary > GEM Module > axi_max_pipeline (GEM) Register

axi_max_pipeline (GEM) Register

axi_max_pipeline (GEM) Register Description

Register Nameaxi_max_pipeline
Relative Address0x0000000054
Absolute Address 0x00FF0B0054 (GEM0)
0x00FF0C0054 (GEM1)
0x00FF0D0054 (GEM2)
0x00FF0E0054 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000101
DescriptionUsed to set the maximum amnount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v).
Note:Xilinx recommends to use the default setting for this register.

axi_max_pipeline (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved, read as zero, ignored on write.
aw2w_max_pipeline15:8rwNormal read/write0x1Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel.
ar2r_max_pipeline 7:0rwNormal read/write0x1Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel.