Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX0RSR3 (DDR_PHY) Register

DX0RSR3 (DDR_PHY) Register

DX0RSR3 (DDR_PHY) Register Description

Register NameDX0RSR3
Relative Address0x00000007DC
Absolute Address 0x00FD0807DC (DDR_PHY)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDATX8 n Rank Status Register 3

DX0RSR3 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved. Return zeroes on reads.
WLAERR15:0roRead-only0x0Write Latency Adjustment error: Indicates, for each of the system
ranks, that an error occurred in the WLA algorithm. This is for the
byte in x8 mode