Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > SAFETY_GATE (PMU_GLOBAL) Register

SAFETY_GATE (PMU_GLOBAL) Register

SAFETY_GATE (PMU_GLOBAL) Register Description

Register NameSAFETY_GATE
Relative Address0x0000000650
Absolute Address 0x00FFD80650 (PMU_GLOBAL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000007
DescriptionSafety gates disable hardware functions.

Disable hardware functions against accidental enabling. Register is reset only by a POR reset.

SAFETY_GATE (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:3roRead-only0x0
PMU_LOGCLR_Enable 2rwNormal read/write0x1PMU Logic Clear Gate Function. If set to 0, it would prevent PMU Logic Clear function from being accidentally enabled.
LBIST_Enable 1rwNormal read/write0x1After a POR reset, the PMU hardware generates a signal to the LBIST controllers. Set [LBIST_Enable] = 0 to help prevent an SEU in the signaling hardware from inadvertently causing LBIST operations to occur during normal operating mode.
Scan_Enable 0rwNormal read/write0x1Scan Clear Function Enable. Set [Scan_Enable] = 0 to help prevent inadvertent assertion of the scan clear signal by software or an SEU in the hardware.