Field Name | Bits | Type | Reset Value | Description |
src31 | 31 | roRead-only | 0x1 | PL_IPI2: OR of all of IPIs targeted to RPU PL2 |
src30 | 30 | roRead-only | 0x1 | PL_IPI1: OR of all of IPIs targeted to RPU PL1 |
src29 | 29 | roRead-only | 0x1 | PL_IPI0: OR of all of IPIs targeted to RPU PL0 |
src28 | 28 | roRead-only | 0x1 | Clock monitor coming from CRL |
src27 | 27 | roRead-only | 0x1 | RTC Seconds Interrupt |
src26 | 26 | roRead-only | 0x1 | RTC Alarm Interupt |
src25 | 25 | roRead-only | 0x1 | APM_LPD: Ord of all LPD APMs |
src24 | 24 | roRead-only | 0x1 | CAN1 interrupt |
src23 | 23 | roRead-only | 0x1 | CAN0 interrupt |
src22 | 22 | roRead-only | 0x1 | UART1 interrupt |
src21 | 21 | roRead-only | 0x1 | UART0 interrupt |
src20 | 20 | roRead-only | 0x1 | SPI1 interrupt |
src19 | 19 | roRead-only | 0x1 | SPI0 interrupt |
src18 | 18 | roRead-only | 0x1 | I2C1 interrupt |
src17 | 17 | roRead-only | 0x1 | I2C0 interrupt |
src16 | 16 | roRead-only | 0x1 | GPIO interrupt |
src15 | 15 | roRead-only | 0x1 | SPI interrupt |
src14 | 14 | roRead-only | 0x1 | NAND/NOR/SRAM Static Memory Controller Interrupt |
src13 | 13 | roRead-only | 0x1 | RPU CPU1 ECC errors interrupt. All ECC interrupt of CPU1 are combined into this interrup |
src12 | 12 | roRead-only | 0x1 | RPU CPU0 ECC errors interrupt. All ECC interrupt of CPU0 are combined into this interrupt |
src11 | 11 | roRead-only | 0x1 | LPD_APB_INT: ORd of all APB interrupts from LPD |
src10 | 10 | roRead-only | 0x1 | OCM interrupt (error) |
src9 | 9 | roRead-only | 0x1 | RPU performance monitor |
src8 | 8 | roRead-only | 0x1 | RPU performance monitor |
Reserved | 7 | roRead-only | 0x1 | reserved. |
Reserved | 6 | roRead-only | 0x1 | reserved. |
Reserved | 5 | roRead-only | 0x1 | reserved. |
Reserved | 4 | roRead-only | 0x1 | reserved. |
Reserved | 3 | roRead-only | 0x1 | reserved. |
Reserved | 2 | roRead-only | 0x1 | reserved. |
Reserved | 1 | roRead-only | 0x1 | reserved. |
Reserved | 0 | roRead-only | 0x1 | reserved. |