Zynq UltraScale+ Devices Register Reference > Module Summary > PLSYSMON Module > SEQ_CHANNEL2 (PLSYSMON) Register
Register Name | SEQ_CHANNEL2 |
---|---|
Relative Address | 0x0000000118 |
Absolute Address | 0x00FFA50D18 (AMS_PL_SYSMON) |
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Sequencer Channel Inclusion, Group 2. |
Include or exclude channels in the auto-sequencing routine. 0: exclude channel. 1: include channel. Note: UG580 refers to this register as SEQCHSEL0.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 15:6 | rwNormal read/write | 0x0 | reserved. |
Reserved | 5 | rwNormal read/write | 0x0 | reserved. |
vccams | 4 | rwNormal read/write | 0x0 | VCC_PL_ADC (VCCADC). |
supply10 | 3 | rwNormal read/write | 0x0 | VUser3. |
supply9 | 2 | rwNormal read/write | 0x0 | VUser2. |
supply8 | 1 | rwNormal read/write | 0x0 | VUser1. |
supply7 | 0 | rwNormal read/write | 0x0 | VUser0. |