Zynq UltraScale+ Devices Register Reference > Module Summary > A53_ETM_0 Module > IDR3 (A53_ETM_0) Register
Register Name | IDR3 |
---|---|
Relative Address | 0x00000001EC |
Absolute Address | 0x00FEC401EC (CORESIGHT_A53_ETM_0) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x0D7B0004 |
Description | ID Register 3 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
NOOVERFLOW | 31 | roRead-only | 0x0 | Indicates if NOOVERFLOW is supported |
NUMPROC | 30:28 | roRead-only | 0x0 | Indicates the number of processors available for tracing. |
SYSSTALL | 27 | roRead-only | 0x1 | Indicates if the implementation can support stall control. |
STALLCTL | 26 | roRead-only | 0x1 | Indicates if is supported |
SYNCPR | 25 | roRead-only | 0x0 | Indicates if an implementation has a fixed synchronization period |
TRCERR | 24 | roRead-only | 0x1 | Indicates if VICTLR.TRCERR is supported |
EXLEVEL_NS | 23:20 | roRead-only | 0x7 | In Non-secure state, each bit indicates whether instruction tracing is supported for the corresponding exception level |
EXLEVEL_S | 19:16 | roRead-only | 0xB | In Secure state, each bit indicates whether instruction tracing is supported for the corresponding exception level |
CCITMIN | 11:0 | roRead-only | 0x4 | Indicates the minimum value that can be programmed in THRESHOLD |