Zynq UltraScale+ Devices Register Reference > Module Summary > AMS Module > MISC_CTRL (AMS) Register
Register Name | MISC_CTRL |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FFA50000 (AMS_CTRL) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Register Access Error Signal Enables. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | roRead-only | 0x0 | |
slverr_enable_drp | 1 | rwNormal read/write | 0x0 | Enable the Error signal back to DRP connection when a register access violation occurs. 0: disable error signal (default). 1: assert error signal for access violations. Note: The [addr_decode_err] interrupt bit is set in the ISR_1 register regardless of the setting of this bit. |
slverr_enable | 0 | rwNormal read/write | 0x0 | Enable the SLVERR signal back to APB interconnect when a register access violation occurs. 0: disable error signal (default). 1: assert error signal for access violations. Note: The [addr_decode_err] interrupt bit is set in the ISR_1 register regardless of the setting of this bit. |