Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_SLCR Module > GICP0_IRQ_MASK (LPD_SLCR) Register

GICP0_IRQ_MASK (LPD_SLCR) Register

GICP0_IRQ_MASK (LPD_SLCR) Register Description

Register NameGICP0_IRQ_MASK
Relative Address0x0000008004
Absolute Address 0x00FF418004 (LPD_SLCR)
Width32
TyperoRead-only
Reset Value0xFFFFFFFF
DescriptionInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.

GICP0_IRQ_MASK (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src3131roRead-only0x1PL_IPI2: OR of all of IPIs targeted to RPU PL2
src3030roRead-only0x1PL_IPI1: OR of all of IPIs targeted to RPU PL1
src2929roRead-only0x1PL_IPI0: OR of all of IPIs targeted to RPU PL0
src2828roRead-only0x1Clock monitor coming from CRL
src2727roRead-only0x1RTC Seconds Interrupt
src2626roRead-only0x1RTC Alarm Interupt
src2525roRead-only0x1APM_LPD: Ord of all LPD APMs
src2424roRead-only0x1CAN1 interrupt
src2323roRead-only0x1CAN0 interrupt
src2222roRead-only0x1UART1 interrupt
src2121roRead-only0x1UART0 interrupt
src2020roRead-only0x1SPI1 interrupt
src1919roRead-only0x1SPI0 interrupt
src1818roRead-only0x1I2C1 interrupt
src1717roRead-only0x1I2C0 interrupt
src1616roRead-only0x1GPIO interrupt
src1515roRead-only0x1SPI interrupt
src1414roRead-only0x1NAND/NOR/SRAM Static Memory Controller Interrupt
src1313roRead-only0x1RPU CPU1 ECC errors interrupt. All ECC interrupt of CPU1 are combined into this interrup
src1212roRead-only0x1RPU CPU0 ECC errors interrupt. All ECC interrupt of CPU0 are combined into this interrupt
src1111roRead-only0x1LPD_APB_INT: ORd of all APB interrupts from LPD
src1010roRead-only0x1OCM interrupt (error)
src9 9roRead-only0x1RPU performance monitor
src8 8roRead-only0x1RPU performance monitor
Reserved 7roRead-only0x1reserved.
Reserved 6roRead-only0x1reserved.
Reserved 5roRead-only0x1reserved.
Reserved 4roRead-only0x1reserved.
Reserved 3roRead-only0x1reserved.
Reserved 2roRead-only0x1reserved.
Reserved 1roRead-only0x1reserved.
Reserved 0roRead-only0x1reserved.