Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > GUSB3PIPECTL (USB3_XHCI) Register
Register Name | GUSB3PIPECTL |
---|---|
Relative Address | 0x000000C2C0 |
Absolute Address |
0x00FE20C2C0 (USB3_0_XHCI) 0x00FE30C2C0 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x010C0002 |
Description | Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode, registers are implemented for each port. Note: - GUSB3PIPECTLn registers are not applicable for USB 2.0-only mode. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PHYSoftRst | 31 | rwNormal read/write | 0x0 | USB3 PHY Soft Reset After setting this bit to 1, the software needs to clear this bit. |
HstPrtCmpl | 30 | rwNormal read/write | 0x0 | HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable. This bit enables placing the SS port link into a compliance state. By default, this bit must be set to 1b0. In compliance lab testing, the SS port link enters compliance after failing the first polling sequence after power on. Set this bit to 0, when you run compliance tests. The sequence for using this functionality is as follows: - 1. Disconnect any plugged in devices. - 2. Perform USBCMD.HCRST or power-on-chip reset. - 3. Set PORTSC.PP=0. - 4. Set GUSB3PIPECTL. HstPrtCmpl=1. This places the link into compliance state. To advance the compliance pattern, follow this sequence (toggle the set GUSB3PIPECTL. HstPrtCmpl): - 1. Set GUSB3PIPECTL.HstPrtCmpl=0. - 2. Set GUSB3PIPECTL.HstPrtCmpl=1. This advances the link to the next compliance pattern. To exit from the compliance state perform USBCMD.HCRST or power-on-chip reset. |
U2SSInactP3ok | 29 | rwNormal read/write | 0x0 | P3 OK for U2/SSInactive (u2SSInactP3ok) - 0: During link state U2/SS.Inactive, put PHY in P2 (Default) - 1: During link state U2/SS.Inactive, put PHY in P3. Note: For a port, if GUSB3PIPECTL[7]=1 and GUSB3PIPECTL[29]=1, set GUSB3PIPECTL[11] to 1. |
DisRxDetP3 | 28 | rwNormal read/write | 0x0 | Disabled receiver detection in P3 (DisRxDetP3) - 0: If PHY is in P3 and Core needs to perform receiver detection, The core performs receiver detection in P3. (Default) - 1: If PHY is in P3 and Core needs to perform receiver detection, The core changes the PHY power state to P2 and then performs receiver detection. After receiver detection, the cores changes PHY power state to P3. |
Ux_exit_in_Px | 27 | rwNormal read/write | 0x0 | Ux Exit in Px (Ux_exit_in_Px) - 0: The core does U1/U2/U3 exit in PHY power state P0 (default behavior). - 1: The core does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. This bit is added for SS PHY workaround where SS PHY injects a glitch on pipe3_RxElecIdle while receiving Ux exit LFPS, and pipe3_PowerDown change is in progress. Note: This bit is used by third-party SS PHY. It must be set to 0 for PHY. For configuration, Ux_exit_in_Px field of GUSB3PIPECTL register must never be set to 1 |
ping_enhancement_en | 26 | rwNormal read/write | 0x0 | Ping Enhancement Enable (ping_enhancement_en) When set, the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk). This field is valid for the downstream port only. Note: This bit is used by third-party SS PHY. It must be set to 0 for PHY. |
u1u2exitfail_to_recov | 25 | rwNormal read/write | 0x0 | U1U2exitfail to Recovery (u1u2exitfail_to_recov) When set, and U1/U2 LFPS handshake fails, the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It prevents interoperability issue if the remote link does not do proper handshake. |
request_p1p2p3 | 24 | rwNormal read/write | 0x1 | Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3) When set, the core always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. If this bit is 0, and immediate Ux exit (remotely initiated, or locally initiated) happens, the core does not request P1/P2/P3 power state change. Note: This bit must be set to 1 for PHY. For third-party SS PHY, check with your PHY vendor. |
StartRxDetU3RxDet | 23 | woWrite-only | 0x0 | Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet) If DWC_USB3_GUSB3PIPECTL_INIT[22] is set, and the link is in either U3 or Rx.Detect state, the core starts receiver detection on the rising edge of this bit. This can only be used for Downstream ports. This bit must be set to 0 for Upstream ports. This feature must not be enabled for normal operation. If have to use this feature, contact. |
DisRxDetU3RxDet | 22 | rwNormal read/write | 0x0 | Disable Receiver Detection in U3/Rx.Det When set, the core does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB3_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be used for the downstream port. This bit must be set to 0 for Upstream ports. This feature must not be enabled for normal operation. |
DelayP1P2P3 | 21:19 | rwNormal read/write | 0x1 | Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs, or Pipe3_RxValid drops to 0. |
DELAYP1TRANS | 18 | rwNormal read/write | 0x1 | Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. - 1b1: When entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals, Pipe3_RxElecIlde is 1 and pipe3_RxValid is 0 - 1b0: When entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIlde and pipe3_RxValid. Note: This bit must be set to 1 for PHY. It is also used by third-party SS PHY. |
SUSPENDENABLE | 17 | rwNormal read/write | 0x0 | Suspend USB3.0 SS PHY (Suspend_en) When set, and if Suspend conditions are valid, the USB 3.0 PHY enters Suspend mode. The application must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization is completed. |
DATWIDTH | 16:15 | roRead-only | 0x0 | PIPE Data Width (DatWidth) - 2b00: 32 bits - 2b01: 16 bits - 2b10: 8 bits One clock after reset, these bits receive the value seen on the pipe3_DataBusWidth. |
AbortRxDetInU2 | 14 | rwNormal read/write | 0x0 | Abort Rx Detect in U2 (AbortRxDetInU2) When set, and the link state is U2, then the core will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only. Note: This bit is used by third-party SS PHY. It must be set to 0 for PHY. |
SkipRxDet | 13 | rwNormal read/write | 0x0 | Skip Rx Detect: When set, the core skips Rx Detection if pipe3_RxElecIdle is low. Skip is defined as waiting for the appropriate timeout, then repeating the operation. |
LFPSP0Algn | 12 | rwNormal read/write | 0x0 | LFPS P0 Align: When set, - The core deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1, U2, or U3 low power states. Otherwise, LFPS transmission is asserted one clock earlier. - The core requests symbol transmission two pipe3_rx_pclks periods after the PHY asserts PhyStatus as a result of the PHY switching from P1 or P2 state to P0 state. Currently, this bit is only used in USB 3.0 HUB with PHY. For other USB 3.0 Host, Device, and DRD cores, this bit is not required. |
P3P2TranOK | 11 | rwNormal read/write | 0x0 | P3 P2 Transitions OK (P3P2TranOK) When set, the core transitions directly from Phy power state P2 to P3 or from state P3 to P2. When not set, P0 is always entered as an intermediate state during transitions between P2 and P3, as defined in the PIPE3 Specification. According to the PIPE3 Specification, any direct transition between P3 and P2 is illegal. Note: This bit is used by third-party SS PHY. It must be set to 0 for PHY. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
P3ExSigP2 | 10 | rwNormal read/write | 0x0 | P3 Exit Signal in P2 (P3ExSigP2) When this bit is set, the core always changes the PHY power state to P2, before attempting a U3 exit handshake. This bit is used only for some non- PHYs that cannot do LFPS in P3. Note: This bit is used by third-party SS PHY. It must be set to 0 for PHY. |
LFPSFILTER | 9 | rwNormal read/write | 0x0 | LFPS Filter (LFPSFilt) When set, filter LFPS reception with pipe3_RxValid in PHY power state P0, that is, ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted. |
RX_DETECT_to_Polling_LFPS_Control | 8 | rwNormal read/write | 0x0 | RX_DETECT to Polling.LFPS Control - 1b0 (Default): Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level. - 1b1: Disables the 400us delay to start Polling LFPS after RX_DETECT. During controller certification with third party PHY it is observed that the PHY is not able to meet the Tx AC common mode voltage active (VTX-CM-ACPP_ACTIVE <100mv) if the link starts polling within 80us from the time rx.detect is performed. To meet this VTX-CM-ACPP_ACTIVE specification, the polling must be delayed further. If the PHY does not have issue then they can set this bit to 1 which allows polling to start within 80us. |
SSICEn | 7 | rwNormal read/write | 0x0 | USB3 SSIC Enable (SSICEn) - 1b0: Pipe interface is active. The RMMI interface on the corresponding port is reset by the core. - 1b1: RMMI interface on the corresponding port connected to M-PHY is active, and pipe interface is inactive. This bit needs to be set before accessing the corresponding GUSB3RMMICTLn register. |
TX_SWING | 6 | rwNormal read/write | 0x0 | Tx Swing (TxSwing) Refer to the PIPE3 specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
TX_MARGIN | 5:3 | rwNormal read/write | 0x0 | Tx Margin[2:0] (TxMargin) Refer to Table 5-3 of the PIPE3 Specification. add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
TX_DE_EPPHASIS | 2:1 | rwNormal read/write | 0x1 | Tx Deemphasis (TxDeemphasis) The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode. (Refer to Table 5-3 of the PIPE3 specification.) add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |
ELASTIC_BUFFER_MODE | 0 | rwNormal read/write | 0x0 | Elastic Buffer Mode (ElasticBufferMode) This bit should be set during boot time and not changed afterwards (Refer to Table 5-3 of the PIPE3 specification.) add this as reference https://www.intel.in/content/dam/doc/white-paper/usb3-phy-interface-pci-express-paper.pdf |