Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_REGS Module > bus_filter (USB3_REGS) Register

bus_filter (USB3_REGS) Register

bus_filter (USB3_REGS) Register Description

Register Namebus_filter
Relative Address0x0000000030
Absolute Address 0x00FF9D0030 (USB3_0)
0x00FF9E0030 (USB3_1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDisables internal bus filters that are enabled by DWC_USB3_EN_BUS_FILTERS

bus_filter (USB3_REGS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4razRead as zero0x0reserved for future
bypass 3:0rwNormal read/write0x0This signal must be set or reset at power-on reset and is not changed during normal operation of core. 1b1 means Bus filters disabled. 1b0 means otherwise