Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > IMR (SPI) Register
Register Name | IMR |
---|---|
Relative Address | 0x0000000010 |
Absolute Address |
0x00FF040010 (SPI0) 0x00FF050010 (SPI1) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Interrupt mask |
0: interrupt disabled. 1: interrupt enabled.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:7 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
TX_FIFO_underflow | 6 | roRead-only | 0x0 | TX FIFO underflow enable |
RX_FIFO_full | 5 | roRead-only | 0x0 | RX FIFO full enable |
RX_FIFO_not_empty | 4 | roRead-only | 0x0 | RX FIFO not empty enable |
TX_FIFO_full | 3 | roRead-only | 0x0 | TX FIFO full enable |
TX_FIFO_not_full | 2 | roRead-only | 0x0 | TX FIFO not full enable |
MODE_FAIL | 1 | roRead-only | 0x0 | ModeFail interrupt enable |
RX_OVERFLOW | 0 | roRead-only | 0x0 | Receive Overflow interrupt enable |