Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_0 (PCIE_ATTRIB) Register

ATTR_0 (PCIE_ATTRIB) Register

ATTR_0 (PCIE_ATTRIB) Register Description

Register NameATTR_0
Relative Address0x0000000000
Absolute Address 0x00FD480000 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000003
DescriptionATTR_0

This register should only be written to during reset of the PCIe block

ATTR_0 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_aer_cap_ecrc_gen_capable 1rwNormal read/write0x1Indicates that the core is capable of generating ECRC. Value transferred to bit 5 of the AER Capabilities and Control Register.
attr_aer_cap_ecrc_check_capable 0rwNormal read/write0x1Indicates that the core is capable of checking ECRC. Value transferred to bit 7 of the AER Capabilities and Control Register.