Zynq UltraScale+ Devices Register Reference > Module Summary > A53_DBG_1 Module > EDITR (A53_DBG_1) Register
Register Name | EDITR |
---|---|
Relative Address | 0x0000000084 |
Absolute Address | 0x00FED10084 (CORESIGHT_A53_DBG_1) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | External Debug Instruction Transfer Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
T32Second | 31:16 | woWrite-only | 0 | Second halfword of the T32 instruction to be executed on the processor. |
EDITR | 31:0 | woWrite-only | 0 | A64 instruction to be executed on the processor. |
T32First | 15:0 | woWrite-only | 0 | First halfword of the T32 instruction to be executed on the processor. |