Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > GPU_REF_CTRL (CRF_APB) Register

GPU_REF_CTRL (CRF_APB) Register

GPU_REF_CTRL (CRF_APB) Register Description

Register NameGPU_REF_CTRL
Relative Address0x0000000084
Absolute Address 0x00FD1A0084 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00001500
DescriptionGPU Clock Generator Control.

GPU_REF_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:27rwNormal read/write0x0reserved.
PP1_CLKACT26rwNormal read/write0x0Clock active control for Pixel Processor 1.
0: disable.
1: enable.
PP0_CLKACT25rwNormal read/write0x0Clock active control for Pixel Processor 0.
0: disable.
1: enable.
CLKACT24rwNormal read/write0x0Clock active control for GPU and both Pixel Processors.
0: disable.
1: enable.
Reserved23:14rwNormal read/write0x0reserved.
DIVISOR013:8rwNormal read/write0x156-bit divider.
Reserved 7:3rwNormal read/write0x0reserved.
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: IOPLL_TO_FPD
010: VPLL
011: DPLL