Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_IOMODULE Module > GPI2 (PMU_IOMODULE) Register
Register Name | GPI2 |
---|---|
Relative Address | 0x0000000028 |
Absolute Address | 0x00FFD40028 (PMU_IOMODULE) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | General Purpose Input Register 2 |
Power Control Requests
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
VCC_INT_FP_DISCONNECT | 31 | roRead-only | 0x0 | Interrupt indicating FP Power Supply Disconnected |
VCC_INT_DISCONNECT | 30 | roRead-only | 0x0 | Interrupt indicating PL Power Supply Disconnected |
VCC_AUX_DISCONNECT | 29 | roRead-only | 0x0 | Interrupt indicating AUX Power Supply Disconnected |
Reserved | 28:24 | razRead as zero | 0x0 | reserved |
DBG_ACPU3_RST_REQ | 23 | roRead-only | 0x0 | Warm Reset Request for ACPU3 from the ACPU Debug Logic |
DBG_ACPU2_RST_REQ | 22 | roRead-only | 0x0 | Warm Reset Request for ACPU2 from the ACPU Debug Logic |
DBG_ACPU1_RST_REQ | 21 | roRead-only | 0x0 | Warm Reset Request for ACPU1 from the ACPU Debug Logic |
DBG_ACPU0_RST_REQ | 20 | roRead-only | 0x0 | Warm Reset Request for ACPU0 from the ACPU Debug Logic |
CP_ACPU3_RST_REQ | 19 | roRead-only | 0x0 | Warm Reset Request for ACPU3 from the ACPU CP |
CP_ACPU2_RST_REQ | 18 | roRead-only | 0x0 | Warm Reset Request for ACPU2 from the ACPU CP |
CP_ACPU1_RST_REQ | 17 | roRead-only | 0x0 | Warm Reset Request for ACPU1 from the ACPU CP |
CP_ACPU0_RST_REQ | 16 | roRead-only | 0x0 | Warm Reset Request for ACPU0 from the ACPU CP |
Reserved | 15:10 | razRead as zero | 0x0 | reserved |
DBG_RCPU1_RST_REQ | 9 | roRead-only | 0x0 | Warm Reset Request for RCPU1 from the RCPU Debug Logic |
DBG_RCPU0_RST_REQ | 8 | roRead-only | 0x0 | Warm Reset Request for RCPU0 from the RCPU Debug Logic |
Reserved | 7:6 | razRead as zero | 0x0 | reserved |
R5_1_SLEEP | 5 | roRead-only | 0x0 | Direct Power down request from R5_1 |
R5_0_SLEEP | 4 | roRead-only | 0x0 | Direct Power down request from R5_0 |
ACPU_3_SLEEP | 3 | roRead-only | 0x0 | Direct Power down request from ACPU_3 |
ACPU_2_SLEEP | 2 | roRead-only | 0x0 | Direct Power down request from ACPU_2 |
ACPU_1_SLEEP | 1 | roRead-only | 0x0 | Direct Power down request from ACPU_1 |
ACPU_0_SLEEP | 0 | roRead-only | 0x0 | Direct Power down request from ACPU_0 |
This register reads the value that is input on the corresponding I/O Module GPI1 port input signal bits.