Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AUD_CH_STATUS_REG3 (DISPLAY_PORT) Register
Register Name | AUD_CH_STATUS_REG3 |
---|---|
Relative Address | 0x000000C014 |
Absolute Address | 0x00FD4AC014 (DISPLAY_PORT) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | AUD_CH_STATUS_REG3: Audio Channel status bits 127 to 96 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
STATUS3 | 31:0 | rwNormal read/write | 0x0 | - |