Field Name | Bits | Type | Reset Value | Description |
Reserved | 31:11 | razRead as zero | 0x0 | Status for an address decode error interrupt. |
UE_RMW | 10 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
FIX_BURST_WR | 9 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
FIX_BURST_RD | 8 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
ECC_UE | 7 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
ECC_CE | 6 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
LOCK_ERR_WR | 5 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
LOCK_ERR_RD | 4 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
INV_OCM_WR | 3 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
INV_OCM_RD | 2 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
PWR_DWN | 1 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |
INV_APB | 0 | roRead-only | 0x1 | see OCM_INT_STATUS register for details |