Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_BOUNDING_BOX_LEFT_RIGHT (GPU) Register

PP1_BOUNDING_BOX_LEFT_RIGHT (GPU) Register

PP1_BOUNDING_BOX_LEFT_RIGHT (GPU) Register Description

Register NamePP1_BOUNDING_BOX_LEFT_RIGHT
Relative Address0x000000A028
Absolute Address 0x00FD4BA028 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBounding Box Left Right Register

PP1_BOUNDING_BOX_LEFT_RIGHT (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:20rwNormal read/write0x0Reserved, write as zero, read undefined.
BOUNDING_BOX_LEFT19:16rwNormal read/write0x0Bits [3:0] of the number of pixels from the left initial framebuffer edge to
exclude from write-back, if the bounding box is honored. Bits [13:4] are
always 0. If a greater bounding box than 16 is required, the modulo 16 of the
bounding box is placed in this register. The remaining part is subtracted from
all vertices.
Reserved15:14rwNormal read/write0x0Reserved, write as zero, read undefined.
BOUNDING_BOX_RIGHT13:0rwNormal read/write0x0The number of pixels from the left initial framebuffer edge - 1 to include in
write-back if the bounding box is honored.