Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_Z_CLEAR_VALUE (GPU) Register
Register Name | PP1_Z_CLEAR_VALUE |
---|---|
Relative Address | 0x000000A010 |
Absolute Address | 0x00FD4BA010 (GPU) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Z Clear Value Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:24 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
Z_CLEAR_VALUE | 23:0 | rwNormal read/write | 0x0 | The 24-bit depth value of the Z tile buffer is logically cleared whenever processing of a new tile starts. If you do not want the Z tile buffer to be cleared, the content of the Z tile buffer can be pre-loaded by using a textured quad and Z-replacement technique. For more information see the explanation of subword 3 in Render state word data structures on page 3-132. See also Table 3-231 on page 3-181 and the corresponding description of texel format value 50. |