Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DFILPCFG0 (DDRC) Register

DFILPCFG0 (DDRC) Register

DFILPCFG0 (DDRC) Register Description

Register NameDFILPCFG0
Relative Address0x0000000198
Absolute Address 0x00FD070198 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x07000000
DescriptionDFI Low Power Configuration Register 0

This register is static. Static registers can only be written when the controller is in reset.

DFILPCFG0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dfi_tlp_resp27:24rwNormal read/write0x7Setting for DFIs tlp_resp time.
Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes.
DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
dfi_lp_wakeup_dpd23:20rwNormal read/write0x0LPDDR3: Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered.
Determines the DFIs tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
dfi_lp_en_dpd16rwNormal read/write0x0LPDDR3: Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit.
- 0 - Disabled
- 1 - Enabled
dfi_lp_wakeup_sr15:12rwNormal read/write0x0Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered.
Determines the DFIs tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
dfi_lp_en_sr 8rwNormal read/write0x0Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit.
- 0 - Disabled
- 1 - Enabled
dfi_lp_wakeup_pd 7:4rwNormal read/write0x0Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
Determines the DFIs tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
dfi_lp_en_pd 0rwNormal read/write0x0Enables DFI Low Power interface handshaking during Power Down Entry/Exit.
- 0 - Disabled
- 1 - Enabled