Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > enable_match_d_n (PL390) Register

enable_match_d_n (PL390) Register

enable_match_d_n (PL390) Register Description

Register Nameenable_match_d_n
Relative Address0x0000000DE0
Absolute Address 0x00F9000DE0 (RCPU_GIC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionReturns the status of the match_d<n> tie-off signals for CPU
Interface <n>.

enable_match_d_n (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
match_d31:0roRead-only0x0Returns the status of the match_d<n>[31:0] inputs on the
Distributor:
Bit [X] = 0 match_d<n>[X] is LOW,
Bit [X] = 1 match_d<n>[X] is HIGH.
Where <n> is a number, from 0 to 7, that identifies one of
the CPU Interfaces.