Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > TSSTIMR (STM) Register

TSSTIMR (STM) Register

TSSTIMR (STM) Register Description

Register NameTSSTIMR
Relative Address0x0000000E84
Absolute Address 0x00FE9C0E84 (CORESIGHT_SOC_STM)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionForce Timestamp Output.

This write-only register is used to force the next packet caused by a stimulus port write to have a timestamp output.

TSSTIMR (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
FORCETS 0woWrite-only0Force Timestamp Stimulus. A write of 1 to this register bit will request the next stimulus port write which causes trace to be upgraded to have a timestamp.
0: ignored.
1: force time stamp.