Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_MAIN Module > I_MSII_CONTROL (AXIPCIE_MAIN) Register

I_MSII_CONTROL (AXIPCIE_MAIN) Register

I_MSII_CONTROL (AXIPCIE_MAIN) Register Description

Register NameI_MSII_CONTROL
Relative Address0x0000000308
Absolute Address 0x00FD0E0308 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionIngress PCI Express Received MSI Interrupt Translation - Control

I_MSII_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:21roRead-only0x0
i_msii_size20:16rwNormal read/write0x0Size of this translation window, expressed as 2^(msii_size_offset+msii_size). Constrained by the i_msii_size_max and i_msii_size_offset fields.
i_msii_status_enable15rwNormal read/write0x0-
Reserved14:1roRead-only0x0
i_msii_enable 0rwNormal read/write0x0Translation Enable. The translation is hit when both of the following are true:
* i_msii_enable == 1
* i_msii_src_base[63:(12+i_msii_size)] == AXI Address[63:(12+i_msii_size)]