Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > ISR (QSPI) Register

ISR (QSPI) Register

ISR (QSPI) Register Description

Register NameISR
Relative Address0x0000000004
Absolute Address 0x00FF0F0004 (QSPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000104
DescriptionInterrupt Status

This register is set when the described event occurs and the interrupt is enabled in the mask register. When any of these bits are set the interrupt output is asserted high. In the default configuration, these bits are all cleared simultaneously by reading this register, though this may be configured for an individual write-one-to-clear scheme.

ISR (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9roRead-only0x0reserved
TXFIFO_EMPTY 8roRead-only0x1TX FIFO Empty interrupt:
0: TX FIFO is not empty.
1: TX FIFO is empty.
Reserved 7roRead-only0x0reserved
TX_FIFO_underflow 6wtcReadable, write a 1 to clear0x0TX FIFO underflow status:
0: no underflow has been detected.
1: underflow is detected.
Write 1 to this bit location to clear
RX_FIFO_full 5roRead-only0x0RX FIFO full (current FIFO status):
0: FIFO is not full.
1: FIFO is full.
RX_FIFO_not_empty 4roRead-only0x0RX FIFO not empty (current FIFO status):
0: FIFO has less than RX THRESHOLD entries.
1: FIFO has more than or equal to RX THRESHOLD entries.
TX_FIFO_full 3roRead-only0x0TX FIFO full (current FIFO status):
0: FIFO is not full
1: FIFO is full
TX_FIFO_not_full 2roRead-only0x1TX FIFO not full (current FIFO status):
0: FIFO has more than or equal to TX THRESHOLD entries.
1: FIFO has less than TX THRESHOLD entries.
Reserved 1roRead-only0x0reserved
RX_OVERFLOW 0wtcReadable, write a 1 to clear0x0Receive Overflow interrupt:
0: no overflow occurred.
1: overflow occurred.
Write 1 to this bit location to clear.