Zynq UltraScale+ Devices Register Reference > Module Summary > APMDDR Module > IER (APMDDR) Register
Register Name | IER |
---|---|
Relative Address | 0x0000000034 |
Absolute Address | 0x00FD0B0034 (APM_DDR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Enable |
0: Disabled 1: Enabled.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:13 | razRead as zero | 0x0 | reserved. |
MET_CT9_OVFLINT_EN | 12 | rwNormal read/write | 0x0 | Metric Counter 9 Overflow Interrupt. |
MET_CT8_OVFLINT_EN | 11 | rwNormal read/write | 0x0 | Metric Counter 8 Overflow Interrupt. |
MET_CT7_OVFLINT_EN | 10 | rwNormal read/write | 0x0 | Metric Counter 7 Overflow Interrupt. |
MET_CT6_OVFLINT_EN | 9 | rwNormal read/write | 0x0 | Metric Counter 6 Overflow Interrupt. |
MET_CT5_OVFLINT_EN | 8 | rwNormal read/write | 0x0 | Metric Counter 5 Overflow Interrupt. |
MET_CT4_OVFLINT_EN | 7 | rwNormal read/write | 0x0 | Metric Counter 4 Overflow Interrupt. |
MET_CT3_OVFLINT_EN | 6 | rwNormal read/write | 0x0 | Metric Counter 3 Overflow Interrupt. |
MET_CT2_OVFLINT_EN | 5 | rwNormal read/write | 0x0 | Metric Counter 2 Overflow Interrupt. |
MET_CT1_OVFLINT_EN | 4 | rwNormal read/write | 0x0 | Metric Counter 1 Overflow Interrupt. |
MET_CT0_OVFLINT_EN | 3 | rwNormal read/write | 0x0 | Metric Counter 0 Overflow Interrupt. |
Reserved | 2 | rwNormal read/write | 0x0 | reserved. |
SMPL_INTRVL_OVFLINT_EN | 1 | rwNormal read/write | 0x0 | Sample Interval Counter Overflow Interrupt. |
GLBCLKCNT_OVFLINT_EN | 0 | rwNormal read/write | 0x0 | Global Clock Counter Overflow Interrupt. |