Zynq UltraScale+ Devices Register Reference > Module Summary > CCI_REG Module

CCI_REG Module

CCI_REG Module Description

Module NameCCI_REG Module
Modules of this TypeCCI_REG
Base Address0x00FD5E0000 (CCI_REG)
DescriptionAXI Cache Coherent Interconnect Configuration, AXI Cache Coherent Interconnect Configuration

CCI_REG Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
MISC_CTRL0x0000000000 1rwNormal read/write0x00000000Controls for the register block.
ISR_00x000000001032mixedMixed types. See bit-field details.0x00000000Interrupt Status Register. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
IMR_00x000000001432roRead-only0x8000003FInterrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER.
IER_00x000000001832mixedMixed types. See bit-field details.0x00000000Interrupt Enable Register. A write of 1 to this location will unmask the interrupt
IDR_00x000000001C32mixedMixed types. See bit-field details.0x00000000Interrupt Disable Register. A write of 1 to this location will mask the interrupt
CCI_MISC_CTRL0x000000004032mixedMixed types. See bit-field details.0x00000000Misc control registesr