Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > PORTPMSC_30 (USB3_XHCI) Register

PORTPMSC_30 (USB3_XHCI) Register

PORTPMSC_30 (USB3_XHCI) Register Description

Register NamePORTPMSC_30
Relative Address0x0000000434
Absolute Address 0x00FE200434 (USB3_0_XHCI)
0x00FE300434 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionUSB3 Port Power Management Status and Control Register Bit Definitions
This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST).
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.

PORTPMSC_30 (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:17roRead-only0x0Reserved
FLA16rwNormal read/write0FLA
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
U2_TIMEOUT15:8rwNormal read/write0U2_TIMEOUT
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
U1_TIMEOUT 7:0rwNormal read/write0U1_TIMEOUT
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.