Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP0_WB0_MRT_ENABLE (GPU) Register

PP0_WB0_MRT_ENABLE (GPU) Register

PP0_WB0_MRT_ENABLE (GPU) Register Description

Register NamePP0_WB0_MRT_ENABLE
Relative Address0x000000811C
Absolute Address 0x00FD4B811C (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionWB0 MRT Enable Register

PP0_WB0_MRT_ENABLE (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4rwNormal read/write0x0Reserved, write as zero, read undefined.
WB0_MRT_ENABLE 3:0rwNormal read/write0x00 MRT 0 enabled
1 MRT 1 enabled
2 MRT 2 enabled
3 MRT 3 enabled