Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank0_ctrl3 (IOU_SLCR) Register
Register Name | bank0_ctrl3 |
---|---|
Relative Address | 0x0000000140 |
Absolute Address | 0x00FF180140 (IOU_SLCR) |
Width | 26 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | MIO Bank 0, CMOS input type control. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
schmitt_cmos_n | 25:0 | rwNormal read/write | 0x0 | Select between Schmitt Trigger or CMOS input for MIO pins [0:25]. 0 = CMOS. 1 = Schmitt (hysteresis). Bit [0] controls MIO pin 0. .. Bit [25] controls MIO pin 25. Bits [26] to [31] are reserved. |