Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > GEM_CLK_CTRL (IOU_SLCR) Register
Register Name | GEM_CLK_CTRL |
---|---|
Relative Address | 0x0000000308 |
Absolute Address | 0x00FF180308 (IOU_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | GEM I/O Clock Control |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:23 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
TSU_CLK_LB_SEL | 22 | rwNormal read/write | 0x0 | Selection of TSU Interface clock 0: TSU clock from the PS 1: TSU clock loop backed from the PL |
TSU_CLK_SEL | 21:20 | rwNormal read/write | 0x0 | Selection of TSU clock source. TSU clock is common for all the GEMs 00: TSU clock from PLL 10: TSU clock from PLL 01: reserved 11: TSU clock from MIO[50] or MIO[51] |
Reserved | 19 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
GEM3_FIFO_CLK_SEL | 18 | rwNormal read/write | 0x0 | Selection of FIFO Interface clock 0: Tx clock from the PS 1: Tx clock loop backed from the PL |
GEM3_SGMII_MODE | 17 | rwNormal read/write | 0x0 | Selection of SGMII or Non SGMII mode 0: Non-SGMII mode. 1: SGMII (clock is from GTR SerDes) Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock. |
GEM3_REF_SRC_SEL | 16 | rwNormal read/write | 0x0 | PLL or PHY source selection for gem3_ref_clk generation 0: PLL Reference clock 1: EMIO PLL clock or GTX Clock |
GEM3_RX_SRC_SEL | 15 | rwNormal read/write | 0x0 | Select source for GEM3_RX_CLK: 0: MIO clock 1: EMIO clock |
Reserved | 14 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
GEM2_FIFO_CLK_SEL | 13 | rwNormal read/write | 0x0 | Selection of FIFO Interface clock 0: Tx clock from the PS 1: Tx clock loop backed from the PL |
GEM2_SGMII_MODE | 12 | rwNormal read/write | 0x0 | Selection of SGMII or Non SGMII mode 0: Non-SGMII mode. 1: SGMII (clock is from GTR SerDes) Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock. |
GEM2_REF_SRC_SEL | 11 | rwNormal read/write | 0x0 | PLL or PHY source selection for GEMn_REF_CLK generation 0: PLL Reference clock 1: EMIO PLL clock or GTX Clock |
GEM2_RX_SRC_SEL | 10 | rwNormal read/write | 0x0 | Select source for GEMn_RX_CLK: 0: MIO clock 1: EMIO clock |
Reserved | 9 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
GEM1_FIFO_CLK_SEL | 8 | rwNormal read/write | 0x0 | Selection of FIFO Interface clock 0: Tx clock from the PS 1: Tx clock loop backed from the PL |
GEM1_SGMII_MODE | 7 | rwNormal read/write | 0x0 | Selection of SGMII or Non SGMII mode 0: Non-SGMII mode. 1: SGMII (clock is from GTR SerDes) Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock. |
GEM1_REF_SRC_SEL | 6 | rwNormal read/write | 0x0 | Select source for GEMn_RX_CLK: 0: PLL Reference clock from Internal(PS) PLL 1: Reference/TX clock from EMIO or GTR Clock (route using [GEM0_RX_SRC_SEL]). Valid when: * [GEM0_SGMII_MODE] = 0 (non-SGMII). |
GEM1_RX_SRC_SEL | 5 | rwNormal read/write | 0x0 | Select external source for GEMn_RX_CLK: 0: MIO clock (route using MIO_PIN_xx registers). 1: EMIO clock. Valid when: * [GEM0_SGMII_MODE] = 0 (non-SGMII). * [GEM0_REF_SRC_SEL] = 1. |
Reserved | 4 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
GEM0_FIFO_CLK_SEL | 3 | rwNormal read/write | 0x0 | Selection of FIFO Interface clock 0: Tx clock from the PS 1: Tx clock loop backed from the PL |
GEM0_SGMII_MODE | 2 | rwNormal read/write | 0x0 | Selection of SGMII or Non SGMII mode 0: Non-SGMII mode. 1: SGMII (clock is from GTR SerDes) Note: Irrespective of what Bit 0 is set to, when Bit 2 is selected as SGMII the RX clock is always driven by an internal GT source and so is the reference clock. |
GEM0_REF_SRC_SEL | 1 | rwNormal read/write | 0x0 | Select source for GEMn_RX_CLK: 0: PLL Reference clock from Internal(PS) PLL 1: Reference/TX clock from EMIO or GTR Clock (route using [GEM0_RX_SRC_SEL]). Valid when: * [GEM0_SGMII_MODE] = 0 (non-SGMII). |
GEM0_RX_SRC_SEL | 0 | rwNormal read/write | 0x0 | Select external source for GEMn_RX_CLK: 0: MIO clock (route using MIO_PIN_xx registers). 1: EMIO clock. Valid when: * [GEM0_SGMII_MODE] = 0 (non-SGMII). * [GEM0_REF_SRC_SEL] = 1. |