Zynq UltraScale+ Devices Register Reference > Module Summary > GIC400 Module > GICD_SPISR0 (GIC400) Register

GICD_SPISR0 (GIC400) Register

GICD_SPISR0 (GIC400) Register Description

Register NameGICD_SPISR0
Relative Address0x0000010D04
Absolute Address 0x00F9010D04 (ACPU_GIC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionShared Peripheral Interrupt Status Registers

GICD_SPISR0 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0roRead-only0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.