Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_ENABLE (DISPLAY_PORT) Register

DP_MAIN_STREAM_ENABLE (DISPLAY_PORT) Register

DP_MAIN_STREAM_ENABLE (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_ENABLE
Relative Address0x0000000084
Absolute Address 0x00FD4A0084 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEnable the transmission of main link video information.

DP_MAIN_STREAM_ENABLE (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0
MS_ENABLE 0rwNormal read/write0x0- When set to 0, the active lanes of the DisplayPort transmitter will output only VB-ID information with the NoVideo flag set to 1.