Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > Delay (QSPI) Register

Delay (QSPI) Register

Delay (QSPI) Register Description

Register NameDelay
Relative Address0x0000000018
Absolute Address 0x00FF0F0018 (QSPI)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTiming Control Delay

This register is only used in master mode to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI _REF_CLK/ext_clk, defined in this table as SPI master ref clock. Note: Change this value only when controller is not communicating with the memory device.

Delay (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
d_nss31:24rwNormal read/write0x0Delay in SPI_REF_CLK or ext_clk cycles for the length that the master mode chip select outputs are de-asserted between words when cpha=0.
d_btwn23:16rwNormal read/write0x0Delay in SPI_REF_CLK or ext_clk cycles between one chip select being de-activated and the activation of another.
d_after15:8rwNormal read/write0x0Delay in SPI_REF_CLK or ext_clk cycles between last bit of current word and the first bit of the next word.
d_int 7:0rwNormal read/write0x0Added delay in SPI_REF_CLK or ext_clk cycles between setting n_ss_out low and first bit transfer.