Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > SD_CONFIG_REG1 (IOU_SLCR) Register

SD_CONFIG_REG1 (IOU_SLCR) Register

SD_CONFIG_REG1 (IOU_SLCR) Register Description

Register NameSD_CONFIG_REG1
Relative Address0x000000031C
Absolute Address 0x00FF18031C (IOU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x32403240
DescriptionSD Configuration, Reg 1.

SD_CONFIG_REG1 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD1_BASECLK30:23rwNormal read/write0x64Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. This field is primarily used for defining the input base clock frequency value to the DLL lookup table.
The DLL Lookup table ( from RTL) requires a precise value to be programmed
SD1_TUNIGCOUNT22:17rwNormal read/write0x20Configures the Number of Taps (Phases) of the rxclk_in that is supported.
SD1_ASYNCWKPENA16rwNormal read/write0x0Determines the Wakeup Signal Generation Mode.
0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/ Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated. The Assertion and deassertion of the
wakeup Event signal synchronous to xin_clk.
1: Asyncrhonous Wakeup Mode: The xin_clk and the host_clk can be stopped in this mode and the Wake up Event is asynchronously generated based on the Card Insertion/Removal/Interrupt Events. The Assertion and deassertion of the wakeup Event signal is asynchronous.
Reserved15razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD0_BASECLK14:7rwNormal read/write0x64Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. This field is primarily used for defining the input base clock frequency value to the DLL lookup table.
The DLL Lookup table ( from RTL) requires a precise value to be programmed so that it chooses appropriate divisor. The valid range of values for this field is 50 or 100 or 200 any other value other than this will not result in a proper look up of the DLL to choose the divisor value appropriately.
SD0_TUNIGCOUNT 6:1rwNormal read/write0x20Configures the Number of Taps (Phases) of the rxclk_in that is supported for auto tuning mode
SD0_ASYNCWKPENA 0rwNormal read/write0x0Select the Wakeup Signal Generation Mode.
0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated. The Assertion and deassertion of the
wakeup Event signal synchronous to xin_clk.
1: Asyncrhonous Wakeup Mode: The xin_clk and the host_clk can be stopped in this mode and the Wake up Event is asynchronously generated based on the Card Insertion/Removal/Interrupt Events. The Assertion and deassertion of the wakeup Event signal is asynchronous.