Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_102 (PCIE_ATTRIB) Register
Register Name | ATTR_102 |
---|---|
Relative Address | 0x0000000198 |
Absolute Address | 0x00FD480198 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00008008 |
Description | ATTR_102 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 15:14 | rwNormal read/write | 0x2 | reserved. |
Reserved | 13 | rwNormal read/write | 0x0 | reserved. |
Reserved | 12 | rwNormal read/write | 0x0 | reserved. |
Reserved | 11 | rwNormal read/write | 0x0 | reserved. |
Reserved | 10 | rwNormal read/write | 0x0 | reserved. |
Reserved | 9 | rwNormal read/write | 0x0 | reserved. |
Reserved | 8 | rwNormal read/write | 0x0 | reserved. |
Reserved | 7 | rwNormal read/write | 0x0 | reserved. |
Reserved | 6 | rwNormal read/write | 0x0 | reserved. |
Reserved | 5 | rwNormal read/write | 0x0 | reserved. |
Reserved | 4 | rwNormal read/write | 0x0 | reserved. |
Reserved | 3:2 | rwNormal read/write | 0x2 | reserved. |
Reserved | 1 | rwNormal read/write | 0x0 | reserved. |
attr_enable_rx_td_ecrc_trim | 0 | rwNormal read/write | 0x0 | If enabled, received TLPs have their td bit set to 0 and the ECRC is removed |