Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > ACBDLR4 (DDR_PHY) Register
Register Name | ACBDLR4 |
---|---|
Relative Address | 0x0000000550 |
Absolute Address | 0x00FD080550 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | AC Bit Delay Line Register 4 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:30 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
Reserved | 29:24 | roRead-only | 0x0 | reserved. |
Reserved | 23:22 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
Reserved | 21:16 | roRead-only | 0x0 | reserved. |
Reserved | 15:14 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
ODT1BD | 13:8 | rwNormal read/write | 0x0 | Delay select for the BDL on ODT[1]. |
Reserved | 7:6 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
ODT0BD | 5:0 | rwNormal read/write | 0x0 | Delay select for the BDL on ODT[0]. |