Zynq UltraScale+ Devices Register Reference > Module Summary > PL390 Module > enable_sgi_pending_clr_if_n (PL390) Register
Register Name | enable_sgi_pending_clr_if_n |
---|---|
Relative Address | 0x0000000280 |
Absolute Address | 0x00F9000280 (RCPU_GIC) |
Width | 16 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Pending Clear Register (ICDICPR) |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
_ | 15:0 | roRead-only | 0x0 | Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions. |