Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > GP_CONTR_REG_PLB_ALLOC_END_ADDR (GPU) Register

GP_CONTR_REG_PLB_ALLOC_END_ADDR (GPU) Register

GP_CONTR_REG_PLB_ALLOC_END_ADDR (GPU) Register Description

Register NameGP_CONTR_REG_PLB_ALLOC_END_ADDR
Relative Address0x0000000014
Absolute Address 0x00FD4B0014 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionGP Control Register PLB Allocate End Address

GP_CONTR_REG_PLB_ALLOC_END_ADDR (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GP_CONTR_REG_PLB_ALLOC_END_ADDR31:7rwNormal read/write0x0End address for the polygon list allocation
Reserved 6:0rwNormal read/write0x0Reserved, write as zero, read undefined