Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > COMMAND (QSPI) Register
Register Name | COMMAND |
---|---|
Relative Address | 0x00000000C0 |
Absolute Address | 0x00FF0F00C0 (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Command control |
This register needs to be programmed for every request.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:21 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
RXFIFO_DRAIN | 20 | woWrite-only | 0x0 | When this bit is set to 1b1, data in the RXFIFO is drained by the HW as soon as the data available in RXIFO. This bit can be set for any write transfer to the Flash so that the HW will discard the data captured while transmitting the write data. 0: Do not discard the data in RXFIFO. 1: Discard the data in RXFIFO. |
RXFIFO_DRAIN_STATUS | 19 | roRead-only | 0x0 | This bit provides the status of RXFIFO_DRAIN. 0: RXFIFO_DRAIN is reset. 1: RXFIFO_DRAIN is set. |
PARTIAL_BYTE_LEN | 18:16 | rwNormal read/write | 0x0 | Value in this field along with TXD1, TXD2, TXD3 represents the number of bits to be transmitted. (TXDx length - PARTIAL_BYTE_LEN) is the number of bits to be transmitted For example, if only 4 bits to be transmitted, program PARTIAL_BYTE_LEN with a value of 4 and then configure TXD1 register. Similar way to transmit 12 bits, program PARTIAL_BYTE_LEN a value of 4 and then configure TXD2 register. Value in this files is cleared by HW soon after completing transmission of partial byte. SW need to write into this register again if need to transfer partial byte. |
Reserved | 15 | rwNormal read/write | 0x0 | reserved. |
RX_DISCARD_REG | 14:8 | rwNormal read/write | 0x0 | Value in this field reflects the number of QSPI clocks for which the data need to be discarded before writing into RXFIFO. In general value in this field should be equal to QSPI clocks required to transmit Command+Address+Dummy cycles. |
DUMMY_CYCLES | 7:2 | rwNormal read/write | 0x0 | Number of dummy cycles to be inserted after the address phase to the flash. |
DMA_EN | 1 | rwNormal read/write | 0x0 | This bit along with LQSPI_CFG[31] forms the mode selection. And the encoding is as mentioned below {DMA_EN, LQSPI_CFG[31]}: 01: Linear Mode. 10: DMA Mode. Others: reserved. Never set both the [DMA_EN] and LQSPI_SFG [31] bits to 1 as it is not a valid condition. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved. |