Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > TX_thres (SPI) Register
Register Name | TX_thres |
---|---|
Relative Address | 0x0000000028 |
Absolute Address |
0x00FF040028 (SPI0) 0x00FF050028 (SPI1) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000001 |
Description | TX FIFO Threshold |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Threshold_of_TX_FIFO | 31:0 | rwNormal read/write | 0x1 | Defines the level at which the TX FIFO not full interrupt is generated Change only when controller is not actively transmitting or receiving data. |