Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > GQSPI_IMR (QSPI) Register
Register Name | GQSPI_IMR |
---|---|
Relative Address | 0x0000000110 |
Absolute Address | 0x00FF0F0110 (QSPI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000FBE |
Description | GQSPI Interrupt Mask |
Status of the interrupt mask (read-only) 0: unmased (enabled). 1: masked. Writes to this register are ignored.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:12 | razRead as zero | 0x0 | reserved |
RX_FIFO_EMPTY | 11 | roRead-only | 0x1 | RX FIFO Empty enable |
Gen_FIFO_full | 10 | roRead-only | 0x1 | Generic FIFO full interrupt |
Gen_FIFO_not_full | 9 | roRead-only | 0x1 | Generic FIFO not full interrupt |
TX_FIFO_EMPTY | 8 | roRead-only | 0x1 | TX FIFO Empty |
Gen_FIFO_Empty | 7 | roRead-only | 0x1 | Generic FIFO Empty interrupt |
Reserved | 6 | razRead as zero | 0x0 | reserved |
RX_FIFO_full | 5 | roRead-only | 0x1 | RX FIFO full |
RX_FIFO_not_empty | 4 | roRead-only | 0x1 | RX FIFO not empty |
TX_FIFO_full | 3 | roRead-only | 0x1 | TX FIFO full |
TX_FIFO_not_full | 2 | roRead-only | 0x1 | TX FIFO not full |
Poll_Time_Expire | 1 | roRead-only | 0x1 | Poll Time out counter expire interrupt enable |
Reserved | 0 | razRead as zero | 0x0 | reserved |