Zynq UltraScale+ Devices Register Reference > Module Summary > TTC Module > Match_1_Counter_2 (TTC) Register

Match_1_Counter_2 (TTC) Register

Match_1_Counter_2 (TTC) Register Description

Register NameMatch_1_Counter_2
Relative Address0x0000000034
Absolute Address 0x00FF110034 (TTC0)
0x00FF120034 (TTC1)
0x00FF130034 (TTC2)
0x00FF140034 (TTC3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMatch value

Match_1_Counter_2 (TTC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Match31:0rwNormal read/write0x0When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.