Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L1_TX_ANA_TM_13 (SERDES) Register
Register Name | L1_TX_ANA_TM_13 |
---|---|
Relative Address | 0x0000004034 |
Absolute Address | 0x00FD404034 (SERDES) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000002 |
Description | Register value is generated by Vivado PCW. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | roRead-only | 0x0 | reserved. |
Reserved | 7:4 | roRead-only | 0x0 | reserved. |
TX_swap_polarity | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
force_TX_swap_polarity | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
Reserved | 1 | rwNormal read/write | 0x1 | reserved. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved. |