Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_2 (PCIE_ATTRIB) Register
Register Name | ATTR_2 |
---|---|
Relative Address | 0x0000000008 |
Absolute Address | 0x00FD480008 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000002 |
Description | ATTR_2 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_aer_cap_version | 4:1 | rwNormal read/write | 0x1 | The version of AER Capability followed. The value is transferred to the VC Capabilities Register[19:16]. |
attr_aer_cap_permit_rooterr_update | 0 | rwNormal read/write | 0x0 | If TRUE, permits the AER Root Status and Error Source ID reg to be updated. If FALSE, these registers are forced to 0. |