Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_HTOTAL (DISPLAY_PORT) Register

DP_MAIN_STREAM_HTOTAL (DISPLAY_PORT) Register

DP_MAIN_STREAM_HTOTAL (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_HTOTAL
Relative Address0x0000000180
Absolute Address 0x00FD4A0180 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSpecifies the total number of clocks in the horizontal framing period for the main stream video signal.

DP_MAIN_STREAM_HTOTAL (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0
HTOTAL15:0rwNormal read/write0x0Horizontal line length total in clocks.