Zynq UltraScale+ Devices Register Reference > Module Summary > A53_DBG_2 Module > EDECCR (A53_DBG_2) Register

EDECCR (A53_DBG_2) Register

EDECCR (A53_DBG_2) Register Description

Register NameEDECCR
Relative Address0x0000000098
Absolute Address 0x00FEE10098 (CORESIGHT_A53_DBG_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExternal Debug Exception Catch Control Register

EDECCR (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NSE 7:4rwNormal read/write0x0Coarse-grained Non-secure exception catch. Possible values of this field are:All other values are reserved. Bits [7,4] are reserved, RES0.
SE 3:0rwNormal read/write0x0Coarse-grained Secure exception catch. Possible values of this field are:All other values are reserved. Bits [2,0] are reserved. RES0. Ignored if ExternalSecureInvasiveDebugEnabled() == FALSE.