Zynq UltraScale+ Devices Register Reference > Module Summary > RSA Module > rsa_cfg (RSA) Register

rsa_cfg (RSA) Register

rsa_cfg (RSA) Register Description

Register Namersa_cfg
Relative Address0x0000000038
Absolute Address 0x00FFCE0064 (RSA)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRSA Control

rsa_cfg (RSA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
rd_endianness 2rwNormal read/write0x0When cleared (0), the RD_DATA registers will not change the incoming APB byte ordering. When set (1), the incomming APB byte locations will be flipped before saving to the RAM. The byte flip is as follows:
- Byte[3] -> Byte[0]
- Byte[2] -> Byte[1]
- Byte[1] -> Byte[2]
- Byte[0] -> Byte[3]
This is a static signal and should not be changed while data is being written or read to the RSA data registers.
wr_endianness 1rwNormal read/write0x0When cleared (0), the WR_DATA registers will not change the incoming APB byte ordering. When set (1), the incomming APB byte locations will be flipped before saving to the RAM. The byte flip is as follows:
- Byte[3] -> Byte[0]
- Byte[2] -> Byte[1]
- Byte[1] -> Byte[2]
- Byte[0] -> Byte[3]
This is a static signal and should not be changed while data is being written or read to the RSA data registers.
slverr_en 0rwNormal read/write0x0By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur.
Enable/Disable SLVERR during address decode failure.
0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0.
1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0.