Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DPLL_FRAC_CFG (CRF_APB) Register
Register Name | DPLL_FRAC_CFG |
---|---|
Relative Address | 0x0000000034 |
Absolute Address | 0x00FD1A0034 (CRF_APB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Fractional control for the PLL |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ENABLED | 31 | rwNormal read/write | 0x0 | Fractional SDM bypass control. 0: PLL is in integer mode and it ignores all fractional data. 1: PLL is in fractional mode and uses [DATA] bitfield for the fractional portion of the feedback divider. |
Reserved | 30:25 | rwNormal read/write | 0x0 | reserved. |
Reserved | 24:22 | rwNormal read/write | 0x0 | reserved. |
Reserved | 21:20 | rwNormal read/write | 0x0 | reserved. |
Reserved | 19 | rwNormal read/write | 0x0 | reserved. |
Reserved | 18 | rwNormal read/write | 0x0 | reserved. |
Reserved | 17:16 | rwNormal read/write | 0x0 | reserved. |
DATA | 15:0 | rwNormal read/write | 0x0 | Fractional value for the Feedback value. |