Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DRAMTMG10 (DDRC) Register
Register Name | DRAMTMG10 |
---|---|
Relative Address | 0x0000000128 |
Absolute Address | 0x00FD070128 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x001C180A |
Description | SDRAM Timing Register 10 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 20:16 | rwNormal read/write | 0x1C | reserved. |
Reserved | 12:8 | rwNormal read/write | 0x18 | reserved. |
Reserved | 3:2 | rwNormal read/write | 0x2 | reserved. |
Reserved | 1:0 | rwNormal read/write | 0x2 | reserved. |