Zynq UltraScale+ Devices Register Reference > Module Summary > AXIPCIE_MAIN Module > E_BREG_BASE_HI (AXIPCIE_MAIN) Register

E_BREG_BASE_HI (AXIPCIE_MAIN) Register

E_BREG_BASE_HI (AXIPCIE_MAIN) Register Description

Register NameE_BREG_BASE_HI
Relative Address0x0000000214
Absolute Address 0x00FD0E0214 (AXIPCIE_MAIN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEgress Bridge Register Translation - Source Address High

E_BREG_BASE_HI (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
breg_base_hi31:0rwNormal read/write0x0This field must be set to 0x0