Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > SPMSCR (STM) Register
Register Name | SPMSCR |
---|---|
Relative Address | 0x0000000E64 |
Absolute Address | 0x00FE9C0E64 (CORESIGHT_SOC_STM) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Enable a debugger to program which masters the STMSPSCR applies to. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
MASTSEL | 22:15 | rwNormal read/write | 0 | This field defines which master the STMSPSCR applies to |
MASTCTL | 0 | rwNormal read/write | 0x0 | This defines how the master is applied: 0: Not used. 1: STMSPSCR. |