Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_QOS_CTRL Module > ZQCS_CTRL1 (DDR_QOS_CTRL) Register

ZQCS_CTRL1 (DDR_QOS_CTRL) Register

ZQCS_CTRL1 (DDR_QOS_CTRL) Register Description

Register NameZQCS_CTRL1
Relative Address0x0000000018
Absolute Address 0x00FD090018 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionZQCS Control Register 2

ZQCS_CTRL1 (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4razRead as zero0x0Reserved for future use
VSYNC_CNT 3:0rwNormal read/write0x0Software Programmable register to issue ZQCS to DDRC after programmable VSYNC pulse count