Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank0_ctrl3 (IOU_SLCR) Register

bank0_ctrl3 (IOU_SLCR) Register

bank0_ctrl3 (IOU_SLCR) Register Description

Register Namebank0_ctrl3
Relative Address0x0000000140
Absolute Address 0x00FF180140 (IOU_SLCR)
Width26
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Bank 0, CMOS input type control.

bank0_ctrl3 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
schmitt_cmos_n25:0rwNormal read/write0x0Select between Schmitt Trigger or CMOS input for MIO pins [0:25].
0 = CMOS.
1 = Schmitt (hysteresis).
Bit [0] controls MIO pin 0.
..
Bit [25] controls MIO pin 25.
Bits [26] to [31] are reserved.