Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > DMACTLR (STM) Register

DMACTLR (STM) Register

DMACTLR (STM) Register Description

Register NameDMACTLR
Relative Address0x0000000C10
Absolute Address 0x00FE9C0C10 (CORESIGHT_SOC_STM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionControls the DMA transfer request mechanism.

DMACTLR (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SENS 3:2rwNormal read/write0x0Determines the sensitivity of the DMA request to the current buffer level in the STM:
0: Empty
1: 25%
2: 50%
3: 75%