Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module > IMR (QSPI) Register
Register Name | IMR |
---|---|
Relative Address | 0x0000000010 |
Absolute Address | 0x00FF0F0010 (QSPI) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Interrupt Un-Mask (enabled) |
0: masked (disabled). 1: unmasked (enabled).
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:9 | roRead-only | 0x0 | reserved |
TXFIFO_EMPTY | 8 | roRead-only | 0x0 | TX FIFO Empty enable |
Reserved | 7 | roRead-only | 0x0 | reserved |
TX_FIFO_underflow | 6 | roRead-only | 0x0 | TX FIFO underflow enable |
RX_FIFO_full | 5 | roRead-only | 0x0 | RX FIFO full enable |
RX_FIFO_not_empty | 4 | roRead-only | 0x0 | RX FIFO not empty enable |
TX_FIFO_full | 3 | roRead-only | 0x0 | TX FIFO full enable |
TX_FIFO_not_full | 2 | roRead-only | 0x0 | TX FIFO not full enable |
Reserved | 1 | roRead-only | 0x0 | reserved |
RX_OVERFLOW | 0 | roRead-only | 0x0 | Receive Overflow interrupt enable |