Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU Module > ISR (XPPU) Register

ISR (XPPU) Register

ISR (XPPU) Register Description

Register NameISR
Relative Address0x0000000010
Absolute Address 0x00FF980010 (LPD_XPPU)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Status and Clear.

AXI and APB Access Violations. If a Status bit is 1 and its Mask is 0, then the IRQ interrupt signal is activated to the interrupt controller. The first AXI violation is recorded. Once an ISR[7:1] status bit is set, subsequent AXI violations are not recorded, but their transactions are poisoned. The status bits are cleared by a system reset and can be cleared by software.

ISR (XPPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0reserved
APER_PARITY 7wtcReadable, write a 1 to clear0x0Aperture Parity Error detected for an aperture entry fetched from local RAM.
0: no error.
1: error detected.
This parity checking is enable by setting CTRL [APER_PARITY_EN] = 1.
APER_TZ 6wtcReadable, write a 1 to clear0x0TrustZone Violation; a non-secure master attempted to access an aperture to a secure memory location.
0: no violation.
1: violation detected.
APER_PERM 5wtcReadable, write a 1 to clear0x0Master ID Access Violation. The transaction does not match any of the 20 Master ID aperture profile configurations.
0: no violation.
1: violation detected.
Reserved 4roRead-only0x0reserved
MID_PARITY 3wtcReadable, write a 1 to clear0x0Master ID Parity Error. One of the 20 Master ID entries fetched from the local registers contained a parity error.
0: no error.
1: error detected.
This parity checking is enable by setting CTRL [MID_PARITY_EN] = 1.
MID_RO 2wtcReadable, write a 1 to clear0x0Read permission Violation. The master attempted a write, but Master ID entry matching the request specifies read-only permission; MASTER_IDxx [MIDR] =1.
0: no violation.
1: violation detected.
This violation checking is enable by setting CTRL [ENABLE] = 1.
MID_MISS 1wtcReadable, write a 1 to clear0x0Master ID Not Found. The transaction's Master ID, after masking is applied, doesn't match a Master ID in the entry list.
0: no miss.
1: miss detected.
INV_APB 0wtcReadable, write a 1 to clear0x0Register Access Error on APB. A register access was requested to an unimplemented register location.
The PSLVERR error signal is also asserted back to the APB interconnect.