Zynq UltraScale+ Devices Register Reference > Module Summary > IPI Module > RPU_0_TRIG (IPI) Register

RPU_0_TRIG (IPI) Register

RPU_0_TRIG (IPI) Register Description

Register NameRPU_0_TRIG
Relative Address0x0000010000
Absolute Address 0x00FF310000 (IPI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionCh 1 Interrupt Trigger (sender). Default RPU0.

Send an interrrupt to another processor by writing a 1 to its associated bit. This asserts a signal that sets a bit in the receivers ISR register. Write-Only: 0: no effect. 1: set interrupt bit in target ISR register.

RPU_0_TRIG (IPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28roRead-only0x0reserved
PL_327woWrite-only0x0Ch 10. Default to PL IPI3.
PL_226woWrite-only0x0Ch 9. Default to PL IPI2.
PL_125woWrite-only0x0Ch 8. Default to PL IPI1.
PL_024woWrite-only0x0Ch 7. Default to PL IPI0.
Reserved23:20roRead-only0x0reserved
PMU_319woWrite-only0x0Ch 6: PMU IPI3.
PMU_218woWrite-only0x0Ch 5: PMU IPI2.
PMU_117woWrite-only0x0Ch 4: PMU IPI1.
PMU_016woWrite-only0x0Ch 3: PMU IPI0.
Reserved15:10roRead-only0x0reserved
RPU_1 9woWrite-only0x0Ch 2. Default to RPU1.
RPU_0 8woWrite-only0x0Ch 1. Default to RPU0.
Reserved 7:1roRead-only0x0reserved
APU 0woWrite-only0x0Ch 0. Default to APU MPCore.