Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PCFGQOS1_3 (DDRC) Register
Register Name | PCFGQOS1_3 |
---|---|
Relative Address | 0x00000006A8 |
Absolute Address | 0x00FD0706A8 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Port 3 Read QoS Configuration Register 1 |
This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
rqos_map_timeoutr | 26:16 | rwNormal read/write | 0x0 | Specifies the timeout value for transactions mapped to the red address queue. |
rqos_map_timeoutb | 10:0 | rwNormal read/write | 0x0 | Specifies the timeout value for transactions mapped to the blue address queue. |