Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TXPMD_TM_48 (SERDES) Register

L3_TXPMD_TM_48 (SERDES) Register

L3_TXPMD_TM_48 (SERDES) Register Description

Register NameL3_TXPMD_TM_48
Relative Address0x000000CCC0
Absolute Address 0x00FD40CCC0 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TXPMD_TM_48 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TXPMD_TM_48_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
ana_misc2_7_6_rsvd 7:6roRead-only0x0Value generated by PCW.
TM_force_resultant_margining_factor 5rwNormal read/write0x0Value generated by PCW.
TM_resultant_margining_factor 4:0rwNormal read/write0x0Value generated by PCW.