Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank0_ctrl1 (IOU_SLCR) Register

bank0_ctrl1 (IOU_SLCR) Register

bank0_ctrl1 (IOU_SLCR) Register Description

Register Namebank0_ctrl1
Relative Address0x000000013C
Absolute Address 0x00FF18013C (IOU_SLCR)
Width26
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Bank 0, Drive 1 control.

bank0_ctrl1 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
drive125:0rwNormal read/write0x0Together with the bank0_ctrl0 [drive0] bit field, controls the output drive strength of MIO pins [0:25].
Drive0 corresponds to MSB and drive1 corresponds to LSB
Drive table for [drive0], [drive1]:
00 = 2 mA
01 = 4 mA
10 = 8 mA
11 = 12 mA
Bit [0] controls MIO pin 0.
..
Bit [25] controls MIO pin 25.
Bits [26] to [31] are reserved.
Eg: setting bank0_ctrl0 [drive0][bit4] = 0 and bank0_ctrl1 [drive1] [bit4]=1 makes MIO[4] drive strength to 4mA