Zynq UltraScale+ Devices Register Reference > Module Summary > GPIO Module > INT_MASK_5 (GPIO) Register

INT_MASK_5 (GPIO) Register

INT_MASK_5 (GPIO) Register Description

Register NameINT_MASK_5
Relative Address0x000000034C
Absolute Address 0x00FF0A034C (GPIO)
Width32
TyperoRead-only
Reset Value0xFFFFFFFF
DescriptionInterrupt Mask Status (GPIO Bank5, EMIO Bank2)

This register operates in exactly the same manner as INT_MASK_0, except that it reflects bank5, which corresponds to EMIO[95:64].

INT_MASK_5 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
INT_MASK_531:0roRead-only0xFFFFFFFFInterrupt mask
0: interrupt source enabled
1: interrupt source masked
Each bit reports the status for the corresponding pin within the 32-bit bank