Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DITHER_CONFIG_SEED1 (DISPLAY_PORT) Register
Register Name | DITHER_CONFIG_SEED1 |
---|---|
Relative Address | 0x000000B084 |
Absolute Address | 0x00FD4AB084 (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00008080 |
Description | Description same as DITHER_CONFIG_SEED0 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:16 | razRead as zero | 0x0 | |
COLR1 | 15:0 | rwNormal read/write | 0x8080 | - |