Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank1_ctrl0 (IOU_SLCR) Register

bank1_ctrl0 (IOU_SLCR) Register

bank1_ctrl0 (IOU_SLCR) Register Description

Register Namebank1_ctrl0
Relative Address0x0000000154
Absolute Address 0x00FF180154 (IOU_SLCR)
Width26
TyperwNormal read/write
Reset Value0x03FFFFFF
DescriptionMIO Bank 1, Drive 0 control.

bank1_ctrl0 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
drive025:0rwNormal read/write0x3FFFFFFTogether with the bank1_ctrl1 [drive1] bit field, controls the output drive strength of MIO pins [26:51].
Truthtable for [drive0], [drive1]:
00 = 2 mA
01 = 4 mA
10 = 8 mA
11 = 12 mA
Bit [0] controls MIO pin 26.
..
Bit [25] controls MIO pin 51.
Bits [26] to [31] are reserved.