Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CIDR0 (SMMU500) Register

SMMU_CIDR0 (SMMU500) Register

SMMU_CIDR0 (SMMU500) Register Description

Register NameSMMU_CIDR0
Relative Address0x0000000FF0
Absolute Address 0x00FD800FF0 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x0000000D
DescriptionComponent Identification register 0

SMMU_CIDR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PREAMBLE 7:0roRead-only0xDRefer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details