Zynq UltraScale+ Devices Register Reference > Module Summary > XPPU Module > MASTER_ID00 (XPPU) Register
Register Name | MASTER_ID00 |
---|---|
Relative Address | 0x0000000100 |
Absolute Address | 0x00FF980100 (LPD_XPPU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x83FF0040 |
Description | Master Profile 0. Predefined for PMU. |
Each Master profile includes a read/write attribute, a Master ID mask, a Master ID matching value, and parity bits for the profile.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
MIDP | 31 | rwNormal read/write | 0x1 | Parity protection for [MIDR], [MIDM] and [MID]. |
MIDR | 30 | rwNormal read/write | 0x0 | Allow only read transactions. 0: read or write okay. 1: read transactions only. |
Reserved | 29:26 | roRead-only | 0x0 | reserved |
MIDM | 25:16 | rwNormal read/write | 0x3FF | Master ID mask. Applied to transaction Master ID and [MID] bit field. |
Reserved | 15:10 | roRead-only | 0x0 | reserved |
MID | 9:0 | rwNormal read/write | 0x40 | Master ID; subject to [MIDM] mask. Predefined value may be changed to profile another master or set of masters. |