Zynq UltraScale+ Devices Register Reference > Module Summary > LPD_GPV Module > rpuM1_intlpd_ar_r (LPD_GPV) Register

rpuM1_intlpd_ar_r (LPD_GPV) Register

rpuM1_intlpd_ar_r (LPD_GPV) Register Description

Register NamerpuM1_intlpd_ar_r
Relative Address0x000004312C
Absolute Address 0x00FE14312C (LPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAR channel average rate

rpuM1_intlpd_ar_r (LPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_r31:20rwNormal read/write0x0channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.