Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > ADPEVT (USB3_XHCI) Register
Register Name | ADPEVT |
---|---|
Relative Address | 0x000000CC28 |
Absolute Address |
0x00FE20CC28 (USB3_0_XHCI) 0x00FE30CC28 (USB3_1_XHCI) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | ADP Event Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:29 | roRead-only | 0x0 | Reserved |
AdpPrbEvnt | 28 | wtcReadable, write a 1 to clear | 0x0 | ADP Probe Event When this event is set, it means that the Vbus voltage is greater than VadpPrb or VadpPrb is reached. |
AdpSnsEvnt | 27 | wtcReadable, write a 1 to clear | 0x0 | ADP Sense Event When this event is set, it means that the Vbus voltage is greater than VadpSns or VadpSns is reached. |
AdpTmoutEvnt | 26 | wtcReadable, write a 1 to clear | 0x0 | ADP Timeout Event This event is relevant when ADP probe command is executed. When this event is set, it means that the ramp time is completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. |
ADPRstCmpltEvnt | 25 | wtcReadable, write a 1 to clear | 0x0 | This event, when set, indicates that the ADP Reset command is successful. |
Reserved | 24:16 | roRead-only | 0x0 | Reserved |
RTIM | 15:0 | roRead-only | 0 | RAMP TIME: These bits capture the latest time it took for Vbus to ramp from VADP_SINK to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: - 0x000: 1 cycles - 0x001: 2 cycles - 0x002: 3 cycles and so on till, - 0xFFFF: 65536 cycles The maximum time of 65536 cycles corresponds to a time of 2.04 seconds. Note: For scaledown ramp_timeout: - PrbDelta = 2b11 => 781.25 us - PrbDelta = 2b10 => 1562.5 us - PrbDelta = 2b01 => 3125 us - PrbDelta = 2b00 => 6250 us |