Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > EP_CTRL (PCIE_ATTRIB) Register

EP_CTRL (PCIE_ATTRIB) Register

EP_CTRL (PCIE_ATTRIB) Register Description

Register NameEP_CTRL
Relative Address0x0000000230
Absolute Address 0x00FD480230 (PCIE_ATTRIB)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPL End Point Mode Control Register

EP_CTRL (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pl_upstream_deemph_source 1rwNormal read/write0x0Enables the Endpoint to control de-emphasis used on the link at 5.0 Gb/s speeds.
0b - -6 dB de-emphasis recommended for short, reflection dominated channels.
1b - -3.5 dB de-emphasis recommended for long, loss dominated channels.
pl_received_hot_rst 0roRead-only0x0Indicates In-Band Hot Reset has been received