Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > PM_CTRL (PCIE_ATTRIB) Register

PM_CTRL (PCIE_ATTRIB) Register

PM_CTRL (PCIE_ATTRIB) Register Description

Register NamePM_CTRL
Relative Address0x0000000218
Absolute Address 0x00FD480218 (PCIE_ATTRIB)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000007
DescriptionCFG PM Control Register

PM_CTRL (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
cfg_trn_pending 3roRead-only0x0If asserted, sets the Transactions Pending bit in the Device Status Register (Device_Status[5]). Note: The user is required to assert this input if the User Application has not received a completion to a request.
cfg_pm_send_pme_to 2rwNormal read/write0x1Active-low signal causes core to to send Turn Off Message. When the link responds with a Turn Off Ack, this will be reported on cfg_msg_received_pme_to_ack, and the final transition to L3 Ready will be reported on cfg_pcie_link_state.
cfg_pm_turnoff_ok 1rwNormal read/write0x1Active low power turn-off ready signal to notify the endpoint that it is safe for power to be turned off. This input will be sampled during or after the cycle in which cfg_msg_received_pme_to pulses.
cfg_pm_wake 0rwNormal read/write0x1One-clock cycle active low pulse to generate and send a Power Management Wake Event (PM_PME) Message TLP to the upstream link partner.