Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > DP_MAIN_STREAM_VRES (DISPLAY_PORT) Register

DP_MAIN_STREAM_VRES (DISPLAY_PORT) Register

DP_MAIN_STREAM_VRES (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_VRES
Relative Address0x0000000198
Absolute Address 0x00FD4A0198 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionVertical resolution of the main stream video source

DP_MAIN_STREAM_VRES (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0
VRES15:0rwNormal read/write0x0Number of active lines per frame of the main stream video.