Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > V_BLEND_IN1CSC_COEFF4 (DISPLAY_PORT) Register

V_BLEND_IN1CSC_COEFF4 (DISPLAY_PORT) Register

V_BLEND_IN1CSC_COEFF4 (DISPLAY_PORT) Register Description

Register NameV_BLEND_IN1CSC_COEFF4
Relative Address0x000000A054
Absolute Address 0x00FD4AA054 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00001000
DescriptionV_BLEND_IN1CSC_COEFF4:Description same as V_BLEND_IN1CSC_COEFF0

V_BLEND_IN1CSC_COEFF4 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:15razRead as zero0x0
Y2R_C414:0rwNormal read/write0x1000Signed representation of value.