Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB5_PMCNTENSET (SMMU500) Register

SMMU_CB5_PMCNTENSET (SMMU500) Register

SMMU_CB5_PMCNTENSET (SMMU500) Register Description

Register NameSMMU_CB5_PMCNTENSET
Relative Address0x0000015F48
Absolute Address 0x00FD815F48 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionProvides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter

SMMU_CB5_PMCNTENSET (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P3 3woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2 2woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1 1woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P0 0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details