Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > IOPLL_FRAC_CFG (CRL_APB) Register

IOPLL_FRAC_CFG (CRL_APB) Register

IOPLL_FRAC_CFG (CRL_APB) Register Description

Register NameIOPLL_FRAC_CFG
Relative Address0x0000000028
Absolute Address 0x00FF5E0028 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionFractional control for the PLL

IOPLL_FRAC_CFG (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ENABLED31rwNormal read/write0x0Fractional SDM bypass control.
0: PLL is in integer mode and it ignores all fractional data.
1: PLL is in fractional mode and uses [DATA] bitfield for the fractional portion of the feedback divider.
Reserved30:25rwNormal read/write0x0reserved.
Reserved24:22rwNormal read/write0x0reserved.
Reserved21:20rwNormal read/write0x0reserved.
Reserved19rwNormal read/write0x0reserved.
Reserved18rwNormal read/write0x0reserved.
Reserved17:16rwNormal read/write0x0reserved.
DATA15:0rwNormal read/write0x0Fractional value for the Feedback value.