Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > FEAT1R (STM) Register

FEAT1R (STM) Register

FEAT1R (STM) Register Description

Register NameFEAT1R
Relative Address0x0000000EA0
Absolute Address 0x00FE9C0EA0 (CORESIGHT_SOC_STM)
Width32
TyperoRead-only
Reset Value0x006587D1
DescriptionRead the features of the STM.

FEAT1R (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SWOEN23:22roRead-only0x1STMTCSR.SWOEN support:
1: not implemented.
SYNCEN21:20roRead-only0x2STMTCSR.SYNCEN support:
2: RAO.
HWTEN19:18roRead-only0x1STMTCSR.HWTEN support:
1: not implemented.
TSPRESCALE17:16roRead-only0x1Timestamp prescale support:
1: not implemented.
TRIGCTL15:14roRead-only0x2Trigger control support.
TRACEBUS13:10roRead-only0x1Trace bus support:
1: ATB with trigger.
SYNC 9:8roRead-only0x3STMSYNCR support:
3: mode.
FORCETS 7roRead-only0x1STMTSSTIMR support:
1: implemented.
TSFREQ 6roRead-only0x1Timestamp frequency indication configuration:
1: RW.
TS 5:4roRead-only0x1Timestamp support:
1: absolute.
PROT 3:0roRead-only0x1Protocol:
1: STPv2.