Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB10_IPAFAR_high (SMMU500) Register

SMMU_CB10_IPAFAR_high (SMMU500) Register

SMMU_CB10_IPAFAR_high (SMMU500) Register Description

Register NameSMMU_CB10_IPAFAR_high
Relative Address0x000001A074
Absolute Address 0x00FD81A074 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe stage 1 IPA Fault Address Upper bits [63:32] Register

SMMU_CB10_IPAFAR_high (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits15:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details