Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_LOCAL Module > DOMAIN_ISO_CNTRL (PMU_LOCAL) Register

DOMAIN_ISO_CNTRL (PMU_LOCAL) Register

DOMAIN_ISO_CNTRL (PMU_LOCAL) Register Description

Register NameDOMAIN_ISO_CNTRL
Relative Address0x00000000F0
Absolute Address 0x00FFD600F0 (PMU_LOCAL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000028
DescriptionIsolation Wall Enable Control. Reset only by POR.

Controls the Isolation walls for various power domains and subsystems. 0: not isolated. 1: isolated. The register maintains its contents during a System Reset.

DOMAIN_ISO_CNTRL (PMU_LOCAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LP_FP_Locked31rwsoRead/write, set only0x0Isolates the FPD-PL domains by clamping all inputs to each domain. Once this bit is set, the FPD-PL remain isolated until POR is asserted.
Reserved30:6roRead-only0x0reserved
FP_PL 5rwNormal read/write0x1Isolates the FPD-PL domains by clamping all inputs to each domain to their disabled values (1=Isolated)
LP_PL_PCAP 4rwNormal read/write0x0Isolates the LPD-PL domains of the PCAP interface signals by clamping all inputs to each domain to their disabled values. This is used mainly during power-down of the PL.
LP_PL_Non_PCAP 3rwNormal read/write0x1Isolates the LPD-PL domains by disabling interface signals except the ones associated with the PCAP subystem by clamping all inputs to each domain to their disabled values. This is used during Partial Reconfiguration of the PL.
LP_FP_2 2rwNormal read/write0x0Isolates the LPD-FPD domains by disabling interface signals that includes Clock, Resets and Controls that may have to be unisolated while the rest of the interface stays in isolation.
LP_FP_1 1rwNormal read/write0x0Isolates the LPD-FPD domains by disabling interface signals except the ones that are controlled by the [LP_FP_2] bit.
PMU 0rwNormal read/write0x0Isolates the PMU from the rest of the LPD. Clamps all inputs to the PMU to their disabled values.