Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > CAPLENGTH (USB3_XHCI) Register
Register Name | CAPLENGTH |
---|---|
Relative Address | 0x0000000000 |
Absolute Address |
0x00FE200000 (USB3_0_XHCI) 0x00FE300000 (USB3_1_XHCI) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Capability Registers Length Host Controller Operational Registers = Base address + CAPLENGTH where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
HCIVERSION | 31:16 | roRead-only | 0 | HC Interface Version Number (HCIVERSION) |
Reserved | 15:8 | roRead-only | 0x0 | Reserved |
CAPLENGTH | 7:0 | roRead-only | 0 | Capability Registers Length (CAPLENGTH) |