Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU_REG Module > IER_0 (SMMU_REG) Register

IER_0 (SMMU_REG) Register

IER_0 (SMMU_REG) Register Description

Register NameIER_0
Relative Address0x0000000018
Absolute Address 0x00FD5F0018 (SMMU_REG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of 1 to this location will unmask the interrupt

IER_0 (SMMU_REG) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err31wtcReadable, write a 1 to clear0x0Address Decode Error
Reserved30:5roRead-only0x0Reserved
gbl_flt_irpt_ns 4woWrite-only0x0Interrupt Enable for gbl_flt_irpt_ns interrupt.
gbl_flt_irpt_s 3woWrite-only0x0Interrupt Enable for gbl_flt_irpt_s interrupt.
comb_perf_irpt_TBU 2woWrite-only0x0Interrupt Enable for comb_perf_irpt_TBU interrupt.
comb_irpt_s 1woWrite-only0x0Interrupt Enable for comb_irpt_s interrupt.
comb_irpt_ns 0woWrite-only0x0Interrupt Enable for comb_irpt_ns interrupt.