Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_PIDR1 (SMMU500) Register
Register Name | SMMU_PIDR1 |
---|---|
Relative Address | 0x0000000FE4 |
Absolute Address | 0x00FD800FE4 (SMMU_GPV) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x000000B4 |
Description | Peripheral Identificaation register 1 |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
JEP106_identity_code | 7:4 | roRead-only | 0xB | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
PartNumber1 | 3:0 | roRead-only | 0x4 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |