Zynq UltraScale+ Devices Register Reference > Module Summary > SPI Module > RX_thres (SPI) Register

RX_thres (SPI) Register

RX_thres (SPI) Register Description

Register NameRX_thres
Relative Address0x000000002C
Absolute Address 0x00FF04002C (SPI0)
0x00FF05002C (SPI1)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionRX FIFO Threshold

RX_thres (SPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Threshold_of_RX_FIFO31:0rwNormal read/write0x1Defines the level at which the RX FIFO not empty interrupt is generated
Change only when controller is not actively transmitting or receiving data.