Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_REGS Module > bus_filter (USB3_REGS) Register
Register Name | bus_filter |
---|---|
Relative Address | 0x0000000030 |
Absolute Address |
0x00FF9D0030 (USB3_0) 0x00FF9E0030 (USB3_1) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Disables internal bus filters that are enabled by DWC_USB3_EN_BUS_FILTERS |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:4 | razRead as zero | 0x0 | reserved for future |
bypass | 3:0 | rwNormal read/write | 0x0 | This signal must be set or reset at power-on reset and is not changed during normal operation of core. 1b1 means Bus filters disabled. 1b0 means otherwise |