Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module

USB3_XHCI Module

USB3_XHCI Module Description

Module NameUSB3_XHCI Module
Modules of this TypeUSB3_0_XHCI, USB3_1_XHCI
Base Address0x00FE200000 (USB3_0_XHCI)
0x00FE300000 (USB3_1_XHCI)
DescriptionUSB Extensible Host Controller Interface, USB Port 0 XHCI

USB3_XHCI Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
CAPLENGTH0x000000000032roRead-only0x00000000Capability Registers Length
Host Controller Operational Registers = Base address + CAPLENGTH
where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h.
HCSPARAMS10x000000000432roRead-only0x00000000Structural Parameters 1 Register
For register definitions, refer to the xHCI specification.
HCSPARAMS20x000000000832roRead-only0x00000000Structural Parameters 2 Register
For register definitions, refer to the xHCI specification.
HCSPARAMS30x000000000C32roRead-only0x00000000Structural Parameters 3 Register
For register definitions, refer to the xHCI specification.
HCCPARAMS10x000000001032roRead-only0x0238F66DCapability Parameters 1 Register
For register definitions, refer to the xHCI specification.
DBOFF0x000000001432roRead-only0x00000000Doorbell Offset Register
For register definitions, refer to the xHCI specification.
RTSOFF0x000000001832roRead-only0x00000000Runtime Register Space Offset Register
HCCPARAMS20x000000001C32roRead-only0x0000000BHost Controller Capability Parameters 2
For register definitions, refer to the xHCI specification.
USBCMD0x000000002032mixedMixed types. See bit-field details.0x00000000USB Command Register
For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
USBSTS0x000000002432mixedMixed types. See bit-field details.0x00000000USB Status Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
PAGESIZE0x000000002832roRead-only0x00000000Page Size Register Bit Definitions
Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received.
A Notification Enable (Nx, where x = 0 to 15) flag is defined for each of the 16 possible device notification types. If a flag is set for a specific notification type, a Device Notification Event is generated when the respective notification packet is received. After reset, all notifications are disabled.
This register is written as a Dword. Byte writes produce undefined results.
DNCTRL0x000000003432mixedMixed types. See bit-field details.0x00000000Device Notification Register Bit Definitions
For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
CRCR_LO0x000000003832mixedMixed types. See bit-field details.0x00000000CRCR_LO
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
CRCR_HI0x000000003C32rwNormal read/write0x00000000CRCR_HI
DCBAAP_LO0x000000005032mixedMixed types. See bit-field details.0x00000000DCBAAP_LO
DCBAAP_HI0x000000005432rwNormal read/write0x00000000DCBAAP_HI
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
CONFIG0x000000005832mixedMixed types. See bit-field details.0x00000000Configure Register Bit Definitions
This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST).
PORTSC_200x000000042032mixedMixed types. See bit-field details.0x000002A0Port Status and Control Register Bit Definitions
The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted.
- PR
- ORC
PORTPMSC_200x000000042432mixedMixed types. See bit-field details.0x00000000USB3 Port Power Management Status and Control Register Bit Definitions
This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST).
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
PORTLI_200x000000042832roRead-only0x00000000Port Link Info Register
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
PORTHLPMC_200x000000042C32mixedMixed types. See bit-field details.0x00000000USB2 Port Hardware LPM Control Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
PORTSC_300x000000043032mixedMixed types. See bit-field details.0x000002A0Port Status and Control Register Bit Definitions
The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted.
- PR
- ORC
- WPR
PORTPMSC_300x000000043432mixedMixed types. See bit-field details.0x00000000USB3 Port Power Management Status and Control Register Bit Definitions
This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST).
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
PORTLI_300x000000043832roRead-only0x00000000Port Link Info Register
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
PORTHLPMC_300x000000043C32roRead-only0x00000000USB2 Port Hardware LPM Control Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
MFINDEX0x000000044032roRead-only0x00000000Microframe Index Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
RsvdZ0x000000044432roRead-only0x00000000RsvdZ
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
IMAN_00x000000046032mixedMixed types. See bit-field details.0x00000000Interrupter Management Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 0 of an array of 4.
IMOD_00x000000046432rwNormal read/write0x00000FA0Interrupter Moderation Register
The software may use this register to pace (or even out) the delivery of interrupts to the host CPU.
This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions.
To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric.
Instance 0 of an array of 4.
ERSTSZ_00x000000046832mixedMixed types. See bit-field details.0x00000000Event Ring Segment Table Size Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 0 of an array of 4.
RsvdP_00x000000046C32roRead-only0x00000000RsvdP Instance 0 of an array of 4.
ERSTBA_LO_00x000000047032mixedMixed types. See bit-field details.0x00000000ERSTBA_LO Instance 0 of an array of 4.
ERSTBA_HI_00x000000047432rwNormal read/write0x00000000ERSTBA_HI Instance 0 of an array of 4.
ERDP_LO_00x000000047832mixedMixed types. See bit-field details.0x00000000ERDP_LO
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 0 of an array of 4.
ERDP_HI_00x000000047C32rwNormal read/write0x00000000ERDP_HI Instance 0 of an array of 4.
IMAN_10x000000048032mixedMixed types. See bit-field details.0x00000000Interrupter Management Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 1 of an array of 4.
IMOD_10x000000048432rwNormal read/write0x00000FA0Interrupter Moderation Register
The software may use this register to pace (or even out) the delivery of interrupts to the host CPU.
This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions.
To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric.
Instance 1 of an array of 4.
ERSTSZ_10x000000048832mixedMixed types. See bit-field details.0x00000000Event Ring Segment Table Size Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 1 of an array of 4.
RsvdP_10x000000048C32roRead-only0x00000000RsvdP Instance 1 of an array of 4.
ERSTBA_LO_10x000000049032mixedMixed types. See bit-field details.0x00000000ERSTBA_LO Instance 1 of an array of 4.
ERSTBA_HI_10x000000049432rwNormal read/write0x00000000ERSTBA_HI Instance 1 of an array of 4.
ERDP_LO_10x000000049832mixedMixed types. See bit-field details.0x00000000ERDP_LO
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 1 of an array of 4.
ERDP_HI_10x000000049C32rwNormal read/write0x00000000ERDP_HI Instance 1 of an array of 4.
IMAN_20x00000004A032mixedMixed types. See bit-field details.0x00000000Interrupter Management Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 2 of an array of 4.
IMOD_20x00000004A432rwNormal read/write0x00000FA0Interrupter Moderation Register
The software may use this register to pace (or even out) the delivery of interrupts to the host CPU.
This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions.
To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric.
Instance 2 of an array of 4.
ERSTSZ_20x00000004A832mixedMixed types. See bit-field details.0x00000000Event Ring Segment Table Size Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 2 of an array of 4.
RsvdP_20x00000004AC32roRead-only0x00000000RsvdP Instance 2 of an array of 4.
ERSTBA_LO_20x00000004B032mixedMixed types. See bit-field details.0x00000000ERSTBA_LO Instance 2 of an array of 4.
ERSTBA_HI_20x00000004B432rwNormal read/write0x00000000ERSTBA_HI Instance 2 of an array of 4.
ERDP_LO_20x00000004B832mixedMixed types. See bit-field details.0x00000000ERDP_LO
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 2 of an array of 4.
ERDP_HI_20x00000004BC32rwNormal read/write0x00000000ERDP_HI Instance 2 of an array of 4.
IMAN_30x00000004C032mixedMixed types. See bit-field details.0x00000000Interrupter Management Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 3 of an array of 4.
IMOD_30x00000004C432rwNormal read/write0x00000FA0Interrupter Moderation Register
The software may use this register to pace (or even out) the delivery of interrupts to the host CPU.
This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions.
To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common interrupts/sec performance metric.
Instance 3 of an array of 4.
ERSTSZ_30x00000004C832mixedMixed types. See bit-field details.0x00000000Event Ring Segment Table Size Register Bit Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 3 of an array of 4.
RsvdP_30x00000004CC32roRead-only0x00000000RsvdP Instance 3 of an array of 4.
ERSTBA_LO_30x00000004D032mixedMixed types. See bit-field details.0x00000000ERSTBA_LO Instance 3 of an array of 4.
ERSTBA_HI_30x00000004D432rwNormal read/write0x00000000ERSTBA_HI Instance 3 of an array of 4.
ERDP_LO_30x00000004D832mixedMixed types. See bit-field details.0x00000000ERDP_LO
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Instance 3 of an array of 4.
ERDP_HI_30x00000004DC32rwNormal read/write0x00000000ERDP_HI Instance 3 of an array of 4.
DB00x00000004E032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB10x00000004E432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB20x00000004E832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB30x00000004EC32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB40x00000004F032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB50x00000004F432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB60x00000004F832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB70x00000004FC32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB80x000000050032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB90x000000050432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB100x000000050832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB110x000000050C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB120x000000051032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB130x000000051432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB140x000000051832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB150x000000051C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB160x000000052032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB170x000000052432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB180x000000052832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB190x000000052C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB200x000000053032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB210x000000053432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB220x000000053832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB230x000000053C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB240x000000054032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB250x000000054432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB260x000000054832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB270x000000054C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB280x000000055032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB290x000000055432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB300x000000055832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB310x000000055C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB320x000000056032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB330x000000056432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB340x000000056832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB350x000000056C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB360x000000057032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB370x000000057432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB380x000000057832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB390x000000057C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB400x000000058032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB410x000000058432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB420x000000058832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB430x000000058C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB440x000000059032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB450x000000059432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB460x000000059832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB470x000000059C32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB480x00000005A032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB490x00000005A432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB500x00000005A832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB510x00000005AC32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB520x00000005B032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB530x00000005B432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB540x00000005B832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB550x00000005BC32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB560x00000005C032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB570x00000005C432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB580x00000005C832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB590x00000005CC32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB600x00000005D032mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB610x00000005D432mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB620x00000005D832mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
DB630x00000005DC32mixedMixed types. See bit-field details.0x00000000Doorbell Register Bit Field Definitions
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted. Bit Bash register testing is not recommended.
USBLEGSUP0x00000008E032mixedMixed types. See bit-field details.0x00000000USBLEGSUP
USBLEGCTLSTS0x00000008E432mixedMixed types. See bit-field details.0x00000000USBLEGCTLSTS
SUPTPRT2_DW00x00000008F032roRead-only0x02000402SUPTPRT2_DW0
SUPTPRT2_DW10x00000008F432roRead-only0x20425355Register SUPTPRT2_DW1
SUPTPRT2_DW20x00000008F832roRead-only0x00080201xHCI Supported Protocol Capability_ Data Word 2
For a description of other register fields, see section 7.2 of the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
SUPTPRT2_DW30x00000008FC32roRead-only0x00000000Register SUPTPRT2_DW3
SUPTPRT3_DW00x000000090032roRead-only0x03000002Register SUPTPRT3_DW0
SUPTPRT3_DW10x000000090432roRead-only0x20425355Register SUPTPRT3_DW1
SUPTPRT3_DW20x000000090832roRead-only0x00000002SUPTPRT3_DW2
For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
SUPTPRT3_DW30x000000090C32roRead-only0x00000000SUPTPRT3_DW3
DCID0x000000091032roRead-only0x00000000DCID
DCDB0x000000091432mixedMixed types. See bit-field details.0x00000000Register DCDB
DCERSTSZ0x000000091832mixedMixed types. See bit-field details.0x00000000DCERSTSZ
DCERSTBA_LO0x000000092032mixedMixed types. See bit-field details.0x00000000DCERSTBA_LO
DCERSTBA_HI0x000000092432rwNormal read/write0x00000000Register DCERSTBA_HI
DCERDP_LO0x000000092832mixedMixed types. See bit-field details.0x00000000DCERDP_LO
DCERDP_HI0x000000092C32rwNormal read/write0x00000000DCERDP_HI
DCCTRL0x000000093032mixedMixed types. See bit-field details.0x00000000DCCTRL
DCST0x000000093432roRead-only0x00000000DCST
DCPORTSC0x000000093832mixedMixed types. See bit-field details.0x00000000Register DCPORTSC
DCCP_LO0x000000094032mixedMixed types. See bit-field details.0x00000000DCCP_LO
DCCP_HI0x000000094432rwNormal read/write0x00000000Register DCCP_HI
DCDDI10x000000094832rwNormal read/write0x00000000Register DCDDI1
DCDDI20x000000094C32rwNormal read/write0x00000000Register DCDDI2
GSBUSCFG00x000000C10032mixedMixed types. See bit-field details.0x00000000Global SoC Bus Configuration Register 0
This register configures system bus DMA options for the master bus, which may be configured as AHB, AXI, or Native. Options include burst length and cache type (bufferable/posted, cacheable/snoop, and so on). The application can program this register upon power-on, or a change in mode of operation after the DMA engine is halted.
xHCI Register Power-On Value:
The standard xHCI driver does not access this register.
GSBUSCFG10x000000C10432mixedMixed types. See bit-field details.0x00000000Global SoC Bus Configuration Register 1
xHCI Register Power-On Value:
The standard xHCI driver does not access this register.
GTXTHRCFG0x000000C10832mixedMixed types. See bit-field details.0x00000000Global Tx Threshold Control Register
For more information on
- Using this register, refer to Architecture Details chapter.
- Selecting values for the fields of this register.
Note:
- All the fields in GTXTHRCFG register are valid only in Host mode.
- GTXTHRCFG register is not applicable for Debug Target.
- GTXTHRCFG register is not applicable in USB 2.0-only mode.
GRXTHRCFG0x000000C10C32mixedMixed types. See bit-field details.0x00000000Global Rx Threshold Control Register
In a normal case, a Tx burst starts as soon as one packet is prefetched; an Rx burst starts as soon as 1-packet space is available. This works well as long as the system bus is faster than the USB 3.0 bus (a 1024-bytes packet takes ~2.2 microseconds on the USB bus in SS mode).
If the system bus latency is larger than 2.2 microseconds to access a 1024-byte packet, then starting a burst on 1-packet condition leads to an early abort of the burst causing unnecessary performance reduction.
To avoid underrun and overrun during the burst, in a high-latency bus system (like USB), threshold and burst size control is provided through GTXTHRCFG and GRXTHRCFG registers. Bit [29] of the GTXTHRCFG and GRXTHRCFG registers enables this feature.
For more information on
- Using this register, refer to Architecture Details chapter.
- Selecting values for the fields of this register.
Note:
- GRXTHRCFG register is not applicable for Debug Target.
- GRXTHRCFG register is not applicable in USB 2.0-only mode.
GCTL0x000000C11032rwNormal read/write0x00693004Global Core Control Register
Note:
When Hibernation is not enabled, you can write any value to GblHibernationEn. It always returns 0 when read.
GPMSTS0x000000C11432mixedMixed types. See bit-field details.0x00000000Global Power Management Status Register
This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information, and is for
use only for debugging purposes.
This register is not applicable in USB 2.0-only mode.
GSTS0x000000C11832mixedMixed types. See bit-field details.0x00000000Global Status Register
GUCTL10x000000C11C32mixedMixed types. See bit-field details.0x00000000Global User Control Register 1
GSNPSID0x000000C12032roRead-only0x5533290AGlobal
ID Register
This is a read-only register that contains the release number of the core.
GGPIO0x000000C12432mixedMixed types. See bit-field details.0x00000000Global General Purpose Input/Output Register
The application can use this register for general purpose input and output ports or for debugging.
GUID0x000000C12832rwNormal read/write0x12345678Global User ID Register This is a read/write register containing the User ID. This register can be used in the following ways:
- To store the version or revision of your system;
- To store hardware configurations that are outside the core;
- As a scratch register.
GUCTL0x000000C12C32mixedMixed types. See bit-field details.0x00000000Global User Control Register:
This register provides a few options for the software to control the core behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices.
GBUSERRADDRLO0x000000C13032roRead-only0x00000000Gobal SoC Bus Error Address Register - Low
This is an alternate register for the GBUSERRADDR register.
GBUSERRADDRHI0x000000C13432roRead-only0x00000000Gobal SoC Bus Error Address Register - High
This is an alternate register for the GBUSERRADDR register.
GPRTBIMAPLO0x000000C13832mixedMixed types. See bit-field details.0x00000000Global SS Port to Bus Instance Mapping Register - Low
This is an alternate register for the GPRTBIMAP register.
Note: For reset values, refer to the corresponding values in the GPRTBIMAP register.
GPRTBIMAPHI0x000000C13C32roRead-only0x00000000Global SS Port to Bus Instance Mapping Register - High
This is an alternate register for the GPRTBIMAP register.
Note: For reset values, refer to the corresponding values in the GPRTBIMAP register.
GHWPARAMS00x000000C14032roRead-only0x4020404AGlobal Hardware Parameter Register 0
GHWPARAMS10x000000C14432roRead-only0x8262493BGlobal Hardware Parameter Register 1
GHWPARAMS20x000000C14832roRead-only0x12345678Global Hardware Parameter Register 2
GHWPARAMS30x000000C14C32roRead-only0x0618C089Global Hardware Parameter Register 3
GHWPARAMS40x000000C15032roRead-only0x47822004Global Hardware Parameter Register 4
GHWPARAMS50x000000C15432roRead-only0x04204108Global Hardware Parameter Register 5
GHWPARAMS60x000000C15832roRead-only0x07BAAC20Global Hardware Parameter Register 6
GHWPARAMS70x000000C15C32roRead-only0x030807D6Global Hardware Parameter Register 7
GDBGFIFOSPACE0x000000C16032mixedMixed types. See bit-field details.0x00420000Global Debug Queue/FIFO Space Available Register
Bit Bash test should not be done on this debug register.
GDBGLTSSM0x000000C16432roRead-only0x01000442Global Debug LTSSM Register
In multi-port host configuration, the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register.
Note:
- GDBGLTSSM register is not applicable for USB 2.0-only mode.
- Bit Bash test should not be done on this debug register.
GDBGLNMCC0x000000C16832roRead-only0x00000000Global Debug LNMCC Register
Bit Bash test should not be done on this debug register.
GDBGBMU0x000000C16C32roRead-only0x00000000Global Debug BMU Register
Bit Bash test should not be done on this debug register.
GDBGLSPMUX_HST0x000000C17032mixedMixed types. See bit-field details.0x003F0000Global Debug LSP MUX Register - Host
This register is for internal use only.
If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined).
Bit Bash test should not be done on this debug register.
GDBGLSP0x000000C17432roRead-only0x00000000Global Debug LSP Register
This register is for internal debug purposes only.
This register is for internal use only.
If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined).
Bit Bash test should not be done on this debug register.
GDBGEPINFO00x000000C17832roRead-only0x00000000Global Debug Endpoint Information Register 0
This register is for internal use only.
If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined).
Bit Bash test should not be done on this debug register.
GDBGEPINFO10x000000C17C32roRead-only0x00800000Global Debug Endpoint Information Register 1
This register is for internal use only.
If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during core configuration, then the default values readout is X (Undefined).
Bit Bash test should not be done on this debug register.
GPRTBIMAP_HSLO0x000000C18032mixedMixed types. See bit-field details.0x00000000Global High-Speed Port to Bus Instance Mapping Register - Low
This is an alternate register for the GPRTBIMAP_HS register.
Note: For reset values, refer to the corresponding values in the GPRTBIMAP_HS register.
GPRTBIMAP_HSHI0x000000C18432roRead-only0x00000000Global High-Speed Port to Bus Instance Mapping Register - High
This is an alternate register for the GPRTBIMAP_HS register.
Note: For reset values, refer to the corresponding values in the GPRTBIMAP register.
GPRTBIMAP_FSLO0x000000C18832mixedMixed types. See bit-field details.0x00000000Global Full-Speed Port to Bus Instance Mapping Register - Low
This is an alternate register for the GPRTBIMAP_FS register.
Note: For reset values, refer to the corresponding values in the GPRTBIMAP_FS register.
GPRTBIMAP_FSHI0x000000C18C32roRead-only0x00000000Global Full-Speed Port to Bus Instance Mapping Register - High
This is an alternate register for the GPRTBIMAP_FS register.
Note: For reset values, refer to the corresponding values in the GPRTBIMAP_FS register.
Reserved_940x000000C19432roRead-only0x00000000Future Register
Reserved_980x000000C19832roRead-only0x00000000Future Register
GUSB2PHYCFG0x000000C20032mixedMixed types. See bit-field details.0x00000000Global USB2 PHY Configuration Register
The application must program this register before starting any transactions on either the SoC bus or the USB.
In Device-only configurations, only one register is needed.
In Host mode, per-port registers are implemented.
GUSB2I2CCTL0x000000C24032roRead-only0x00000000Reserved Register
GUSB2PHYACC_ULPI0x000000C28032mixedMixed types. See bit-field details.0x00000000Global USB 2.0 UTMI PHY Vendor Control Register
The application used this register to access PHY registers. For an ULPI PHY, the core uses the ULPI interface for PHY register access.
The application sets the Vendor Control register for PHY register access and times the PHY register access. The application polls the VStatus Done bit in this register for the completion of the PHY register access.
In Device-only configurations, only one register is needed. In Host mode, per-port registers are implemented
GUSB3PIPECTL0x000000C2C032mixedMixed types. See bit-field details.0x010C0002Global USB 3.0 PIPE Control Register
The application uses this register to configure the USB3 PHY and PIPE interface.
Device-only configuration requires only one register. In Host mode, registers are implemented for each port.
Note:
- GUSB3PIPECTLn registers are not applicable for USB 2.0-only mode.
GTXFIFOSIZ00x000000C30032rwNormal read/write0x00000042Global Transmit FIFO Size Register
This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device IN Endpoints, number of Host Bus Instances, and presence of Debug Capability.
The register default values for each mode are assigned based on the maximum packet size, number of packets to be buffered, speed of host bus instance, bus latency, and mode of operation (host, device, or, DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values.
For the debug capability mode, the currently mapped EP0 IN and EP1 IN TxFIFO numbers can be read from the GFIFOPRIDBC register.
For OTG mode of operation, when the core is transitioning to host mode, program GTXFIFOSIZ register to the correct value only after OCTL.PeriMode is programmed to 1b0.
GTXFIFOSIZ10x000000C30432rwNormal read/write0x00420184Register GTXFIFOSIZ 1
GTXFIFOSIZ20x000000C30832rwNormal read/write0x01C60184Transmit FIFOn RAM Start Address
This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.
GTXFIFOSIZ30x000000C30C32rwNormal read/write0x034A0184Register GTXFIFOSIZ 3
GTXFIFOSIZ40x000000C31032rwNormal read/write0x04CE0184Register GTXFIFOSIZ 4
GTXFIFOSIZ50x000000C31432rwNormal read/write0x06520184Register GTXFIFOSIZ 5
GRXFIFOSIZ00x000000C38032rwNormal read/write0x00000185Global Receive FIFO Size Register
This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus Instances and presence of Debug Capability; device mode requires only one RxFIFO.
The register default values for each mode are assigned based on the maximum packet size, number of packets to be buffered, speed of the host bus instance, bus latency, and mode of operation (host, device, or DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values.
For the debug capability mode, the currently mapped RxFIFO number can be read from the GFIFOPRIDBC register.
GRXFIFOSIZ10x000000C38432rwNormal read/write0x01850000Register
GRXFIFOSIZ20x000000C38832rwNormal read/write0x01850000Register
GEVNTADRLO_00x000000C40032rwNormal read/write0x00000000Global Event Buffer Address (Low) Register
This is an alternate register for the GEVNTADRn register. Instance 0 of an array of 4.
GEVNTADRHI_00x000000C40432rwNormal read/write0x00000000Global Event Buffer Address (High) Register
This is an alternate register for the GEVNTADRn register. Instance 0 of an array of 4.
GEVNTSIZ_00x000000C40832mixedMixed types. See bit-field details.0x00000000Global Event Buffer Size Register
This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 0 of an array of 4.
GEVNTCOUNT_00x000000C40C32mixedMixed types. See bit-field details.0x00000000Global Event Buffer Count Register
This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed.
Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 0 of an array of 4.
GEVNTADRLO_10x000000C41032rwNormal read/write0x00000000Global Event Buffer Address (Low) Register
This is an alternate register for the GEVNTADRn register. Instance 1 of an array of 4.
GEVNTADRHI_10x000000C41432rwNormal read/write0x00000000Global Event Buffer Address (High) Register
This is an alternate register for the GEVNTADRn register. Instance 1 of an array of 4.
GEVNTSIZ_10x000000C41832mixedMixed types. See bit-field details.0x00000000Global Event Buffer Size Register
This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 1 of an array of 4.
GEVNTCOUNT_10x000000C41C32mixedMixed types. See bit-field details.0x00000000Global Event Buffer Count Register
This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed.
Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 1 of an array of 4.
GEVNTADRLO_20x000000C42032rwNormal read/write0x00000000Global Event Buffer Address (Low) Register
This is an alternate register for the GEVNTADRn register. Instance 2 of an array of 4.
GEVNTADRHI_20x000000C42432rwNormal read/write0x00000000Global Event Buffer Address (High) Register
This is an alternate register for the GEVNTADRn register. Instance 2 of an array of 4.
GEVNTSIZ_20x000000C42832mixedMixed types. See bit-field details.0x00000000Global Event Buffer Size Register
This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 2 of an array of 4.
GEVNTCOUNT_20x000000C42C32mixedMixed types. See bit-field details.0x00000000Global Event Buffer Count Register
This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed.
Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 2 of an array of 4.
GEVNTADRLO_30x000000C43032rwNormal read/write0x00000000Global Event Buffer Address (Low) Register
This is an alternate register for the GEVNTADRn register. Instance 3 of an array of 4.
GEVNTADRHI_30x000000C43432rwNormal read/write0x00000000Global Event Buffer Address (High) Register
This is an alternate register for the GEVNTADRn register. Instance 3 of an array of 4.
GEVNTSIZ_30x000000C43832mixedMixed types. See bit-field details.0x00000000Global Event Buffer Size Register
This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization, software must initialize the size with the number of bytes allocated for the Event Buffer. The Event Interrupt Mask will mask the interrupt, but events are still queued. After configuration, software must preserve the Event Buffer Size value when changing the Event Interrupt Mask. Instance 3 of an array of 4.
GEVNTCOUNT_30x000000C43C32mixedMixed types. See bit-field details.0x00000000Global Event Buffer Count Register
This register holds the number of valid bytes in the Event Buffer. During initialization, software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to the Event Buffer, it increments this count. Most events are four bytes, but some events may span over multiple four byte entries. Whenever the count is greater than zero, the hardware raises the corresponding interrupt line (depending on the EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software processes one or more events out of the Event Buffer. Afterwards, software must write the Event Count field with the number of bytes it processed.
Clock crossing delays may result in the interrupts continual assertion after software acknowledges the last event. Therefore, when the interrupt line is asserted, software must read the GEVNTCOUNT register and only process events if the GEVNTCOUNT is greater than 0. Instance 3 of an array of 4.
GHWPARAMS80x000000C60032roRead-only0x000007BAGlobal Hardware Parameters
This register contains the hardware configuration options selected during implementation.
GTXFIFOPRIDEV0x000000C61032mixedMixed types. See bit-field details.0x00000000Global Device TX FIFO DMA Priority Register
This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high, 0: low) of each TXFIFO[n]. When multiple TXFIFOs compete for DMA service at a given time (that is, multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner:
- 1. High-priority TXFIFOs are granted access using round-robin arbitration
- 2. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full).
For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
When configuring periodic IN endpoints, software must set register bit[n]=1, where n is the TXFIFO assignment. This ensures that the DMA for isochronous or interrupt IN endpoints are prioritized over bulk or control IN endpoints.
This register is present only when the core is configured to operate in the device mode (includes DRD and OTG modes). The register size corresponds to the number of Device IN endpoints.
Note
- Since the device mode uses only one RXFIFO, there is no Device RXFIFO DMA Priority Register.
GTXFIFOPRIHST0x000000C61832mixedMixed types. See bit-field details.0x00000000Global Host TX FIFO DMA Priority Register
This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of TXFIFO[n] within a speed group. When multiple TXFIFOs compete for DMA service at a given time (i.e., multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner:
- 1. Among the FIFOs in the same speed group (SS or HS/FSLS):
a. High-priority TXFIFOs are granted access using round-robin arbitration
b. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full).
- 2. The TX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register.
For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
This register is present only when the core is configured to operate in the host mode (includes DRD and OTG modes). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS).
GRXFIFOPRIHST0x000000C61C32mixedMixed types. See bit-field details.0x00000000Global Host RX FIFO DMA Priority Register
This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of RXFIFO[n] within a speed group. When multiple RXFIFOs compete for DMA service at a given time (i.e., multiple RXQs contain RX DMA requests and their corresponding RXFIFOs have data available), the RX DMA arbiter grants access on a packet-basis in the following manner:
- 1. Among the FIFOs in the same speed group (SS or HS/FSLS):
a. High-priority RXFIFOs are granted access using round-robin arbitration
b. Low-priority RXFIFOs are granted access using round-robin arbitration only after high-priority RXFIFOs have no further processing to do (that is, either the RXQs are empty or the corresponding RXFIFOs do not have the required data).
- 2. The RX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register.
For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
This register is present only when the core is configured to operate in the host mode (includes DRD and OTG modes). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS).
GFIFOPRIDBC0x000000C62032mixedMixed types. See bit-field details.0x00000000Global Host Debug Capability DMA Priority Register
This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and TXFIFO DMA priority registers, when the DbC mode is enabled.
Priority settings are specified in relation to the low-priority SS speed group:
- 1. Normal priority indicates that the DbC FIFOs are considered identical to the Host SS low-priority FIFOs.
- 2. Low priority indicates that the DbC FIFOs are considered to have lower priority than all Host SS FIFOs.
- 3. High priority indicates that the DbC FIFOs are considered higher priority than the Host SS low-priority FIFOs but lower priority than the Host SS high-priority FIFOs.
This register is present only when the core is configured to operate in Host Debug Capability (DbC) mode.
GDMAHLRATIO0x000000C62432mixedMixed types. See bit-field details.0x00000000Global Host FIFO DMA High-Low Priority Ratio Register
This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low Priority Ratio grants as indicated in the register separately for TX and RX.
To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is 4. SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, and so on.
If FIFOs from both speed groups are not requesting access simultaneously then,
- if SS got grants 4 out of the last 4 times, then HS/FSLS get the priority on any future request.
- if HS/FSLS got the grant last time, SS gets the priority on the next request.
- if there is a valid request on either SS or HS/FSLS, a grant is always awarded; there is no idle.
This register is present if the core is configured to operate in host mode (includes DRD and OTG).
GFLADJ0x000000C63032mixedMixed types. See bit-field details.0x00000000Global Frame Length Adjustment Register
This register provides options for the software to control the core behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an option to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely from the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
DCFG0x000000C70032mixedMixed types. See bit-field details.0x00000800Device Configuration Register.
This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
DCTL0x000000C70432mixedMixed types. See bit-field details.0x00000000Device Control Register
Note:
When Hibernation is not enabled using GCTL.GblHibernationEn field,
- you can write any value to CSS, CRS, L1HibernationEn, and KeepConnect fields
- L1HibernationEn, and KeepConnect fields always return 0 when read in this hibernation-disabled state
DEVTEN0x000000C70832mixedMixed types. See bit-field details.0x00000000Device Event Enable Register
This register controls the generation of device-specific events. If an enable bit is set to 0, the event will not be generated.
DSTS0x000000C70C32mixedMixed types. See bit-field details.0x00000000Device Status Register
This register indicates the status of the device controller with respect to USB-related events.
Note:
When Hibernation is not enabled, RSS and SSS fields always return 0 when read.
DGCMDPAR0x000000C71032rwNormal read/write0x00000000Device Generic Command Parameter Register
This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register.
DGCMD0x000000C71432mixedMixed types. See bit-field details.0x00000000Device Generic Command Register
This register enables software to program the core using a single generic command interface to send link management packets and notifications. This register contains command, control, and status fields relevant to the current generic command, while the DGCMDPAR register provides the command parameter.
DALEPENA0x000000C72032rwNormal read/write0x00000000Device Active USB Endpoint Enable Register.
This register indicates whether a USB endpoint is active in a given configuration or interface.
Rsvd00x000000C72432roRead-only0x00000000Reserved
Rsvd10x000000C72832roRead-only0x00000000Reserved
Rsvd20x000000C72C32roRead-only0x00000000Reserved
Rsvd30x000000C73032roRead-only0x00000000Reserved
Rsvd40x000000C73432roRead-only0x00000000Reserved
Rsvd50x000000C73832roRead-only0x00000000Reserved
Rsvd60x000000C73C32roRead-only0x00000000Reserved
Rsvd70x000000C74032roRead-only0x00000000Reserved
Rsvd80x000000C74432roRead-only0x00000000Reserved
Rsvd90x000000C74832roRead-only0x00000000Reserved
Rsvd100x000000C74C32roRead-only0x00000000Reserved
Rsvd110x000000C75032roRead-only0x00000000Reserved
Rsvd120x000000C75432roRead-only0x00000000Reserved
Rsvd130x000000C75832roRead-only0x00000000Reserved
Rsvd140x000000C75C32roRead-only0x00000000Reserved
Rsvd150x000000C76032roRead-only0x00000000Reserved
Rsvd160x000000C76432roRead-only0x00000000Reserved
Rsvd170x000000C76832roRead-only0x00000000Reserved
Rsvd180x000000C76C32roRead-only0x00000000Reserved
Rsvd190x000000C77032roRead-only0x00000000Reserved
Rsvd200x000000C77432roRead-only0x00000000Reserved
Rsvd210x000000C77832roRead-only0x00000000Reserved
Rsvd220x000000C77C32roRead-only0x00000000Reserved
Rsvd230x000000C78032roRead-only0x00000000Reserved
Rsvd240x000000C78432roRead-only0x00000000Reserved
Rsvd250x000000C78832roRead-only0x00000000Reserved
Rsvd260x000000C78C32roRead-only0x00000000Reserved
Rsvd270x000000C79032roRead-only0x00000000Reserved
Rsvd280x000000C79432roRead-only0x00000000Reserved
Rsvd290x000000C79832roRead-only0x00000000Reserved
Rsvd300x000000C79C32roRead-only0x00000000Reserved
Rsvd310x000000C7A032roRead-only0x00000000Reserved
DEPCMDPAR2_00x000000C80032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 0 of an array of 12.
DEPCMDPAR1_00x000000C80432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 0 of an array of 12.
DEPCMDPAR0_00x000000C80832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 0 of an array of 12.
DEPCMD_00x000000C80C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 0 of an array of 12.
DEPCMDPAR2_10x000000C81032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 1 of an array of 12.
DEPCMDPAR1_10x000000C81432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 1 of an array of 12.
DEPCMDPAR0_10x000000C81832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 1 of an array of 12.
DEPCMD_10x000000C81C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 1 of an array of 12.
DEPCMDPAR2_20x000000C82032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 2 of an array of 12.
DEPCMDPAR1_20x000000C82432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 2 of an array of 12.
DEPCMDPAR0_20x000000C82832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 2 of an array of 12.
DEPCMD_20x000000C82C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 2 of an array of 12.
DEPCMDPAR2_30x000000C83032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 3 of an array of 12.
DEPCMDPAR1_30x000000C83432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 3 of an array of 12.
DEPCMDPAR0_30x000000C83832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 3 of an array of 12.
DEPCMD_30x000000C83C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 3 of an array of 12.
DEPCMDPAR2_40x000000C84032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 4 of an array of 12.
DEPCMDPAR1_40x000000C84432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 4 of an array of 12.
DEPCMDPAR0_40x000000C84832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 4 of an array of 12.
DEPCMD_40x000000C84C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 4 of an array of 12.
DEPCMDPAR2_50x000000C85032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 5 of an array of 12.
DEPCMDPAR1_50x000000C85432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 5 of an array of 12.
DEPCMDPAR0_50x000000C85832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 5 of an array of 12.
DEPCMD_50x000000C85C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 5 of an array of 12.
DEPCMDPAR2_60x000000C86032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 6 of an array of 12.
DEPCMDPAR1_60x000000C86432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 6 of an array of 12.
DEPCMDPAR0_60x000000C86832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 6 of an array of 12.
DEPCMD_60x000000C86C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 6 of an array of 12.
DEPCMDPAR2_70x000000C87032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 7 of an array of 12.
DEPCMDPAR1_70x000000C87432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 7 of an array of 12.
DEPCMDPAR0_70x000000C87832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 7 of an array of 12.
DEPCMD_70x000000C87C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 7 of an array of 12.
DEPCMDPAR2_80x000000C88032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 8 of an array of 12.
DEPCMDPAR1_80x000000C88432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 8 of an array of 12.
DEPCMDPAR0_80x000000C88832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 8 of an array of 12.
DEPCMD_80x000000C88C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 8 of an array of 12.
DEPCMDPAR2_90x000000C89032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 9 of an array of 12.
DEPCMDPAR1_90x000000C89432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 9 of an array of 12.
DEPCMDPAR0_90x000000C89832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 9 of an array of 12.
DEPCMD_90x000000C89C32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 9 of an array of 12.
DEPCMDPAR2_100x000000C8A032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 10 of an array of 12.
DEPCMDPAR1_100x000000C8A432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 10 of an array of 12.
DEPCMDPAR0_100x000000C8A832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 10 of an array of 12.
DEPCMD_100x000000C8AC32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 10 of an array of 12.
DEPCMDPAR2_110x000000C8B032rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)
This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command.
Instance 11 of an array of 12.
DEPCMDPAR1_110x000000C8B432rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n) Instance 11 of an array of 12.
DEPCMDPAR0_110x000000C8B832rwNormal read/write0x00000000Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n) Instance 11 of an array of 12.
DEPCMD_110x000000C8BC32mixedMixed types. See bit-field details.0x00000000Device Physical Endpoint-n Command Register
This register enables software to issue physical endpoint-specific commands. This register contains command, control, and status fields relevant to the current generic command, while the DEPCMDPAR[2:0]n registers provide command parameters and return status information.
Several fields (including Command Type) are write-only, so their read values are undefined. After power-on, prior to issuing the first endpoint command, the read value of this register is undefined. In particular, the CmdAct bit may be set after power-on. In this case, it is safe to issue an endpoint command. Instance 11 of an array of 12.
OCFG0x000000CC0032mixedMixed types. See bit-field details.0x00000000OTG Configuration Register
This register specifies the HNP and SRP capability of the controller
OCTL0x000000CC0432mixedMixed types. See bit-field details.0x00000000OTG Control Register
The OTG Control register controls the behavior of the OTG function of the core.
OEVT0x000000CC0832mixedMixed types. See bit-field details.0x00000000OTG Events Register
Any event set in this register will cause otg_interrupt signal to go high. Writing 1b1 to the event information bit in this register clears the register bit and the associated interrupt. The otg_interrupt signal goes low when there are no more pending OTG events.
OEVTEN0x000000CC0C32mixedMixed types. See bit-field details.0x00000000OTG Events Enable Register
Setting a bit in this register enables the generation of corresponding events in OEVT and assertion of otg_interrupt due to this event. When the enable bit is 1b0, the event is
not be set in OEVT and otg_interrupt is not asserted due to this event.
OSTS0x000000CC1032roRead-only0x00000000OTG Status Register
The OTG Status Register reflects the status of the OTG function of the core.
ADPEVT0x000000CC2832mixedMixed types. See bit-field details.0x00000000ADP Event Register