Zynq UltraScale+ Devices Register Reference > Module Summary > GIC400 Module > GICH_LR3_Alias5 (GIC400) Register

GICH_LR3_Alias5 (GIC400) Register

GICH_LR3_Alias5 (GIC400) Register Description

Register NameGICH_LR3_Alias5
Relative Address0x0000050B0C
Absolute Address 0x00F9050B0C (ACPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionList Register 3

GICH_LR3_Alias5 (GIC400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.