Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_DBGRPTRTCU (SMMU500) Register
Register Name | SMMU_DBGRPTRTCU |
---|---|
Relative Address | 0x0000000088 |
Absolute Address | 0x00FD800088 (SMMU_GPV) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Address of an entry from a specific cache in TCU. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DATASRC | 27:26 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
WAY_RAM | 25:24 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TLB_Pointer | 12:4 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
TLB_Entry_Pointer | 3:0 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |