Zynq UltraScale+ Devices Register Reference > Module Summary > RPU Module > RPU_GLBL_CNTL (RPU) Register
Register Name | RPU_GLBL_CNTL |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FF9A0000 (RPU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000050 |
Description | Global Control Regiter for RPU |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:11 | razRead as zero | 0x0 | Reserved for future use |
GIC_AXPROT | 10 | rwNormal read/write | 0x0 | GIC access security setting. This bit is equivalent to AxPROT[1] on AXI bus. 0: All RPU transactions to GIC are secure (reset default). 1: All RPU transactions to GIC are non-secure. Note: The RPU does not toggle the TZ bit. |
Reserved | 9 | razRead as zero | 0x0 | Reserved for future use |
TCM_CLK_CNTL | 8 | rwNormal read/write | 0x0 | TCM clock disable (all TCMs, both RPU processors): 0: TCMs are clocked (reset default). 1: TCM clocks are stopped (gated off) |
TCM_WAIT | 7 | rwNormal read/write | 0x0 | Insert Wait states in TCM access: 0: Disable (no wait state inserted, reset default) 1: Enable (insert single cycle wait on every TCM access: ATCM , B0TCM, and B1TCM) |
TCM_COMB | 6 | rwNormal read/write | 0x1 | Combine TCMs of RPU0 and RPU1: 0: Disable (128KB TCMs are visible to each RPU) 1: Enable (256KB TCM is visible to RPU0, reset default) |
TEINIT | 5 | rwNormal read/write | 0x0 | Select exception handling state: 0: Arm (reset default) 1: Thumb |
SLCLAMP | 4 | rwNormal read/write | 0x1 | Output clamps for redundant processor: 0: Disable 1: Enable (required for lock-step mode, reset default) |
SLSPLIT | 3 | rwNormal read/write | 0x0 | Processor Mode: 0: Lock-step mode (Safety mode, reset default). 1: Dual, split mode (Performance Mode). |
DBGNOCLKSTOP | 2 | rwNormal read/write | 0x0 | Clock control when entering standby: 0: clocks are stopped in standby mode (reset default). 1: clocks continue in standby mode (does not assert nCLKSTOPPEDm). |
CFGIE | 1 | rwNormal read/write | 0x0 | Instruction fetch endianess: 0: Little-endian (reset default) 1: Big-endian |
CFGEE | 0 | rwNormal read/write | 0x0 | Data endianness during exception handling: 0: Little-endian (reset default). 1: Big-endian. |