Zynq UltraScale+ Devices Register Reference > Module Summary > VCU_SLCR Module > VCU_AXI_CTRL (VCU_SLCR) Register

VCU_AXI_CTRL (VCU_SLCR) Register

VCU_AXI_CTRL (VCU_SLCR) Register Description

Register NameVCU_AXI_CTRL
Relative Address0x0000000040
Absolute Address 0x00A0040040 (VCU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000F000
DescriptionThis register controls this reference clock

VCU_AXI_CTRL (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved18razRead as zero0x0reserved
MCU_CLK_SEL17rwNormal read/write0x00: Encoder MCU clock selected on output port for monitoring purpose.
1: Decoder MCU clock selected on output port for monitoring purpose.
CORE_CLK_SEL16rwNormal read/write0x00: Encoder core clock selected on output port for monitoring purpose.
1: Decoder core clock selected on output port for monitoring purpose.
MCU_CLKACT15rwNormal read/write0x1Clock active signal. Switch to 0 to disable the clock
DEC_CLKACT14rwNormal read/write0x1Clock active signal. Switch to 0 to disable the clock
ENC_CACHE_CLKACT13rwNormal read/write0x1Clock active signal. Switch to 0 to disable the clock
ENC_CLKACT12rwNormal read/write0x1Clock active signal. Switch to 0 to disable the clock
Reserved11:0razRead as zero0x0reserved