Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_HBA Module > CAP2 (SATA_AHCI_HBA) Register
Register Name | CAP2 |
---|---|
Relative Address | 0x0000000024 |
Absolute Address | 0x00FD0C0024 (SATA_AHCI_HBA) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x0000000C |
Description | HBA Capabilities Extended |
Indicates capabilities of the HBA to driver software.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:6 | roRead-only | 0x0 | Reserved |
DESO | 5 | roRead-only | 0x0 | DevSleep Entrance from Slumber Only (DESO): This field specifies that the HBA shall only assert the DEVSLP signal if the interface is in Slumber. When this bit is set to 1, the HBA shall ignore software directed entrance to DevSleep via PxCMD.ICC unless PxSSTS.IPM = 6h. When this bit is cleared to 0, the HBA may enter DevSleep from any link state (active, Partial, or Slumber). |
SADM | 4 | roRead-only | 0x0 | Supports Aggressive Device Sleep Management (SADM): When set to 1, the HBA supports hardware assertion of the DEVSLP signal after the idle timeout expires. When cleared to 0, this function is not supported and software shall treat the PxDEVSLP.ADSE field as reserved. |
SDS | 3 | roRead-only | 0x1 | Supports Device Sleep (SDS): When set to 1, the HBA supports the Device Sleep feature. When cleared to 0, DEVSLP is not supported and software shall not set PxCMD.ICC to 8h. |
APST | 2 | roRead-only | 0x1 | Automatic Partial to Slumber Transitions (APST): When set to 1, the HBA supports Automatic Partial to Slumber Transitions. When cleared to 0, Automatic Partial to Slumber Transitions are not supported. Please refer to section 10.16 for more information regarding Automatic Partial to Slumber transitions. |
NVMP | 1 | roRead-only | 0x0 | NVMHCI Present (NVMP): When set to 1, the HBA includes support for NVMHCI and the registers at offset 60h-9Fh are valid. When cleared to 0, the HBA does not support NVMHCI. |
BOH | 0 | roRead-only | 0x0 | BIOS/OS Handoff (BOH): When set to 1, the HBA supports the BIOS/OS handoff mechanism defined in section 10.6. When cleared to 0, the HBA does not support the BIOS/OS handoff mechanism. When BIOS/OS handoff is supported, the HBA has implemented the BOHC global HBA register. When cleared to 0, it indicates that the HBA does not support BIOS/OS handoff and the BOHC global HBA register is not implemented. |