Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank1_ctrl6 (IOU_SLCR) Register
Register Name | bank1_ctrl6 |
---|---|
Relative Address | 0x0000000168 |
Absolute Address | 0x00FF180168 (IOU_SLCR) |
Width | 26 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | MIO Bank 1, Output slew rate select. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
slow_fast_slew_n | 25:0 | rwNormal read/write | 0x0 | Select between fast and slow output slew rates for MIO pins [26:51]. 0 = fast slew rate. 1 = slow slew rate. Bit [0] controls MIO pin 26. .. Bit [25] controls MIO pin 51. Bits [26] to [31] are reserved. |