Zynq UltraScale+ Devices Register Reference > Module Summary > SIOU Module > reg_ctrl (SIOU) Register
Register Name | reg_ctrl |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FD3D0000 (SIOU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Miscellaneous control functions for SIOU |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | roRead-only | 0x0 | Reserved |
slverr_enable | 0 | rwNormal read/write | 0x0 | By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur. Enable/Disable SLVERR during address decode failure. 0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0. 1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0. |