Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TM_DIG_21 (SERDES) Register

L3_TM_DIG_21 (SERDES) Register

L3_TM_DIG_21 (SERDES) Register Description

Register NameL3_TM_DIG_21
Relative Address0x000000D0A8
Absolute Address 0x00FD40D0A8 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_DIG_21 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_DIG_21_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
Reserved 7:5roRead-only0x0Value generated by PCW.
comma_location_rst 4rwNormal read/write0x0Value generated by PCW.
ssc_wait_cnt 3:2rwNormal read/write0x0Value generated by PCW.
comma_pre_lock_thresh 1:0rwNormal read/write0x0Value generated by PCW.