Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module > PP1_WB2_TARGET_FLAGS (GPU) Register

PP1_WB2_TARGET_FLAGS (GPU) Register

PP1_WB2_TARGET_FLAGS (GPU) Register Description

Register NamePP1_WB2_TARGET_FLAGS
Relative Address0x000000A318
Absolute Address 0x00FD4BA318 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionWB2 Target Flags Register

PP1_WB2_TARGET_FLAGS (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:6rwNormal read/write0x0Reserved, write as zero, read undefined.
WB2_BIG_ENDIAN 5rwNormal read/write0x0When enabled, pixels are written in big-endian byte order.
When disabled, pixels are written in little-endian byte order.
WB2_DITHER_ENABLE 4rwNormal read/write0x0When enabled, dithering of the write-back data is performed
using Bayer ordered dithering. Dithering is only possible
when FP_TILEBUF_ENABLE is off.
Note:
Dithering only is supported when the tilebuffer is not
downsampled more than a factor of four in either dimension,
that is, the tilebuffer size is not less than 4x4 pixels.
WB2_INV_COMPONENT_ORDER_ENABLE 3rwNormal read/write0x0When enabled, color formats get the order of their
components inverted, for example:
RGBA -> ARGB.
This, together with WB2_SWAP_RED_BLUE_ENABLE
makes it possible to support different component
permutations of WB2_TARGET_PIXEL_FORMAT.
WB2_SWAP_RED_BLUE_ENABLE 2rwNormal read/write0x0When enabled, color formats get their red and blue
components swapped, for example:
RGBA->BGRA.
This, together with
WB2_INV_COMPONENT_ORDER_ENABLE makes it
possible to support different component permutations of
WB2_TARGET_PIXEL_FORMAT.
WB2_BOUNDING_BOX_ENABLE 1rwNormal read/write0x0When enabled, write-back is limited to inside the
rectangular box defined by the
BOUNDING_BOX_LEFT_RIGHT and
BOUNDING_BOX_BOTTOM registers.
WB2_DIRTY_BIT_ENABLE 0rwNormal read/write0x0When enabled, only pixels written to in the tile buffer are
written back to the framebuffer.