Zynq UltraScale+ Devices Register Reference > Module Summary > A53_PMU_2 Module > INTENCLR_EL1 (A53_PMU_2) Register
Register Name | INTENCLR_EL1 |
---|---|
Relative Address | 0x0000000C60 |
Absolute Address | 0x00FEE30C60 (CORESIGHT_A53_PMU_2) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Performance Monitors Interrupt Enable Clear Register |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
C | 31 | rwNormal read/write | 0x0 | PMCCNTR_EL0 overflow interrupt request disable bit. |
P | 30:0 | rwNormal read/write | 0x0 | Event counter overflow interrupt request disable bit for EVCNTR<x>_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: |