Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_5 (PCIE_ATTRIB) Register

ATTR_5 (PCIE_ATTRIB) Register

ATTR_5 (PCIE_ATTRIB) Register Description

Register NameATTR_5
Relative Address0x0000000014
Absolute Address 0x00FD480014 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x0000FF07
DescriptionATTR_5

This register should only be written to during reset of the PCIe block

ATTR_5 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_aer_cap_optional_err_support15:0rwNormal read/write0xFF07Indicates which optional error conditions in the Uncorrectable and Correctable Error Mask/Severity registers are supported. If an error is unsupported, then the corresponding bit in the Mask/Severity register is hardwired to 0. Encoding ("1" indicates support):
[0]
: Corrected Internal Error
[1]
: Header Log Overflow
[2]
: Receiver Error
[3:7]
: undefined
[8]
: Surprise Down
[9]
: Flow Control Protocol Error
[10]
: Completion Timeout
[11]
: Completer Abort
[12]
: Receiver Overflow
[13]
: ECRC Error
[14]
: ACS Violation
[15]
: Uncorrectable Internal Error