Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_PORTCNTRL Module > PxSIG (SATA_AHCI_PORTCNTRL) Register

PxSIG (SATA_AHCI_PORTCNTRL) Register

PxSIG (SATA_AHCI_PORTCNTRL) Register Description

Register NamePxSIG
Relative Address0x0000000024
Absolute Address 0x00FD0C0124 (SATA_AHCI_PORT0_CNTRL)
0x00FD0C01A4 (SATA_AHCI_PORT1_CNTRL)
Width32
TyperoRead-only
Reset Value0xFFFFFFFF
DescriptionPort x Signature (PxSIG).

This is a 32-bit register which contains the initial signature of an attached device when the first D2H Register FIS is received from that device. It is updated once after a reset sequence.

PxSIG (SATA_AHCI_PORTCNTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SIG31:0roRead-only0xFFFFFFFFSignature (SIG): Contains the signature received from a device on the first D2H Register FIS.
The bit order is as follows:
Bit Field
31:24 LBA High Register
23:16 LBA Mid Register
15:08 LBA Low Register
07:00 Sector Count Register