Zynq UltraScale+ Devices Register Reference > Module Summary > SIOU Module > IR_ENABLE (SIOU) Register
Register Name | IR_ENABLE |
---|---|
Relative Address | 0x000000000C |
Absolute Address | 0x00FD3D000C (SIOU) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:1 | roRead-only | 0x0 | Reserved |
addr_decode_err | 0 | woWrite-only | 0x0 | Enable for an address decode error interrupt. |