Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > RP_CTRL (PCIE_ATTRIB) Register

RP_CTRL (PCIE_ATTRIB) Register

RP_CTRL (PCIE_ATTRIB) Register Description

Register NameRP_CTRL
Relative Address0x0000000234
Absolute Address 0x00FD480234 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPL Root Port Mode Control Register

RP_CTRL (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
pl_downstream_deemph_source 1rwNormal read/write0x0Enables the Root Port to control de-emphasis used on the link at 5.0 Gb/s speeds.
0b - Use Upstream link partner preferred de-emphasis.
1b - Use Selectable de-emphasis value from Link Control 2 register.
pl_transmit_hot_rst 0rwNormal read/write0x0Active-High signal to direct the PCI ExpressRoot Port to transmit an In-Band Hot Reset