Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX8RSR2 (DDR_PHY) Register

DX8RSR2 (DDR_PHY) Register

DX8RSR2 (DDR_PHY) Register Description

Register NameDX8RSR2
Relative Address0x0000000FD8
Absolute Address 0x00FD080FD8 (DDR_PHY)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDATX8 n Rank Status Register 2

DX8RSR2 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved. Return zeroes on reads.
WLAWN15:0roRead-only0x0Write Latency Adjustment 'DQS off on some DQ lines' warning.
One bit per rank indicates that, for that rank, the WLA algorithm
found some DQ lines where the read data sequence did not match
the expected comparison signatures. This is for the byte in x8
mode