Zynq UltraScale+ Devices Register Reference > Module Summary > SMMU500 Module > SMMU_CB2_PMEVCNTR2 (SMMU500) Register
Register Name | SMMU_CB2_PMEVCNTR2 |
---|---|
Relative Address | 0x0000012E08 |
Absolute Address | 0x00FD812E08 (SMMU_GPV) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter. |
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
bits | 31:0 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |