Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > PLL_REF_SEL0 (SERDES) Register

PLL_REF_SEL0 (SERDES) Register

PLL_REF_SEL0 (SERDES) Register Description

Register NamePLL_REF_SEL0
Relative Address0x0000010000
Absolute Address 0x00FD410000 (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000000D
DescriptionRegister value is generated by Vivado PCW.

PLL_REF_SEL0 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PLL_REF_SEL0_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
PLL_REF_SEL0_7_rsvd 7roRead-only0x0Value generated by PCW.
PLL_REF_SEL0_6_rsvd 6roRead-only0x0Value generated by PCW.
PLL_REF_SEL0_5_rsvd 5roRead-only0x0Value generated by PCW.
pllrefsel0 4:0rwNormal read/write0xDValue generated by PCW.