Zynq UltraScale+ Devices Register Reference > Module Summary > DDR_PHY Module > DX8SL0PLLCR1 (DDR_PHY) Register

DX8SL0PLLCR1 (DDR_PHY) Register

DX8SL0PLLCR1 (DDR_PHY) Register Description

Register NameDX8SL0PLLCR1
Relative Address0x0000001408
Absolute Address 0x00FD081408 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDAXT8 0-1 PLL Control Register 1 (Type B PLL Only)

DX8SL0PLLCR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:22roRead-only0x0Reserved. Return zeroes on reads
PLLPROG21:6rwNormal read/write0x0Connects to the PLL PLL_PROG bus. Reserved. Set to 0x0000.
BYPVREGCP 5rwNormal read/write0x0Bypass PLL vreg_cp
BYPVREGDIG 4rwNormal read/write0x0Bypass PLL vreg_dig.
Reserved 3rwNormal read/write0x0reserved.
LOCKPS 2rwNormal read/write0x0Lock Detector Phase Select. Connects to pin LOCK_PHASE_SEL
on the PLL.
LOCKCS 1rwNormal read/write0x0Lock Detector Counter Select. Connects to pin
LOCK_COUNT_SEL on the PLL.
LOCKDS 0rwNormal read/write0x0Lock Detector Select. Connects to pin LOCK_DET_SEL on the
PLL on the PLL.