Zynq UltraScale+ Devices Register Reference > Module Summary > CRL_APB Module > IR_MASK (CRL_APB) Register
Register Name | IR_MASK |
---|---|
Relative Address | 0x0000000008 |
Absolute Address | 0x00FF5E0008 (CRL_APB) |
Width | 1 |
Type | roRead-only |
Reset Value | 0x00000001 |
Description | Interrupt Mask. |
Read-only. 0: enabled. 1: masked (disabled IRQ). If an IR_STATUS bit = 1 (asserted interrupt) and the IR_MASK bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Modify the mask bits using the enable and disable registers.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
addr_decode_err | 0 | roRead-only | 0x1 | Register Access Error on APB. |