Zynq UltraScale+ Devices Register Reference > Module Summary > IOU_SLCR Module > bank1_ctrl1 (IOU_SLCR) Register

bank1_ctrl1 (IOU_SLCR) Register

bank1_ctrl1 (IOU_SLCR) Register Description

Register Namebank1_ctrl1
Relative Address0x0000000158
Absolute Address 0x00FF180158 (IOU_SLCR)
Width26
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Bank 1, Drive 1 control.

bank1_ctrl1 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
drive125:0rwNormal read/write0x0Together with the bank1_ctrl0 [drive0] bit field, controls the output drive strength of MIO pins [26:51].
Refer to the bank1_ctrl0 register for a drive table.
Bit [0] controls MIO pin 26.
..
Bit [25] controls MIO pin 51.
Bits [26] to [31] are reserved.