Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_26 (PCIE_ATTRIB) Register
Register Name | ATTR_26 |
---|---|
Relative Address | 0x0000000068 |
Absolute Address | 0x00FD480068 (PCIE_ATTRIB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00003000 |
Description | ATTR_26 |
This register should only be written to during reset of the PCIe block
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr_dev_cap_enable_slot_pwr_limit_value | 13 | rwNormal read/write | 0x1 | Permits captured Slot Power Limit Scale Messages to program corresponding Device Capabilities Value field (Upstream Ports only). If set to 0, this field will be hardwired to 0. |
attr_dev_cap_enable_slot_pwr_limit_scale | 12 | rwNormal read/write | 0x1 | Permits captured Slot Power Limit Scale Messages to program corresponding Device Capabilities Scale field (Upstream Ports only). If set to 0, this field will be hardwired to 0. |
Reserved | 11 | rwNormal read/write | 0x0 | reserved. |
Reserved | 10:9 | rwNormal read/write | 0x0 | reserved. |
Reserved | 8 | rwNormal read/write | 0x0 | reserved. |
Reserved | 7 | rwNormal read/write | 0x0 | reserved. |
Reserved | 6:5 | rwNormal read/write | 0x0 | reserved. |
Reserved | 4 | rwNormal read/write | 0x0 | reserved. |
Reserved | 3 | rwNormal read/write | 0x0 | reserved. |
Reserved | 2 | rwNormal read/write | 0x0 | reserved. |
Reserved | 1 | rwNormal read/write | 0x0 | reserved. |
Reserved | 0 | rwNormal read/write | 0x0 | reserved. |