Zynq UltraScale+ Devices Register Reference > Module Summary > SATA_AHCI_HBA Module > CAP (SATA_AHCI_HBA) Register
Register Name | CAP |
---|---|
Relative Address | 0x0000000000 |
Absolute Address | 0x00FD0C0000 (SATA_AHCI_HBA) |
Width | 32 |
Type | roRead-only |
Reset Value | 0xE537FF80 |
Description | HBA Capabilities |
Indicates basic capabilities of the HBA to driver software.
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
S64A | 31 | roRead-only | 0x1 | Supports 64-bit Addressing (S64A): Indicates whether the HBA can access 64-bit data structures. When set to 1, the HBA shall make the 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry read/write. When cleared to 0, these are read-only and treated as 0 by the HBA. |
SNCQ | 30 | roRead-only | 0x1 | Supports Native Command Queuing (SNCQ): Indicates whether the HBA supports Serial ATA native command queuing. If set to 1, an HBA shall handle DMA Setup FISes natively, and shall handle the auto-activate optimization through that FIS. If cleared to 0, native command queuing is not supported and software should not issue any native command queuing commands. |
SSNTF | 29 | roRead-only | 0x1 | Supports SNotification Register (SSNTF): When set to 1, the HBA supports the PxSNTF (SNotification) register and its associated functionality. When cleared to 0, the HBA does not support the PxSNTF (SNotification) register and its associated functionality. Refer to section 10.11.1. Asynchronous notification with a directly attached device is always supported. |
SMPS | 28 | roRead-only | 0x0 | Supports Mechanical Presence Switch (SMPS): When set to 1, the HBA supports mechanical presence switches on its ports for use in hot plug operations. When cleared to 0, this function is not supported. This value is loaded by the BIOS prior to OS initialization. |
SSS | 27 | roRead-only | 0x0 | Supports Staggered Spin-up (SSS): When set to 1, the HBA supports staggered spin-up on its ports, for use in balancing power spikes. When cleared to 0, this function is not supported. This value is loaded by the BIOS prior to OS initiallization. |
SALP | 26 | roRead-only | 0x1 | Supports Aggressive Link Power Management (SALP): When set to 1, the HBA can support auto-generating link requests to the Partial or Slumber states when there are no commands to process. When cleared to 0, this function is not supported and software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved. Refer to section 8.3.1.3. |
SAL | 25 | roRead-only | 0x0 | Supports Activity LED (SAL): When set to 1, the HBA supports a single activity indication output pin. This pin can be connected to an LED on the platform to indicate device activity on any drive. When cleared to 0, this function is not supported. See section 10.11 for more information. |
SCLO | 24 | roRead-only | 0x1 | Supports Command List Override (SCLO): When set to 1, the HBA supports the PxCMD.CLO bit and its associated function. When cleared to 0, the HBA is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation. |
ISS | 23:20 | roRead-only | 0x3 | Interface Speed Support (ISS): Indicates the maximum speed the HBA can support on its ports. These encodings match the system software programmable PxSCTL.DET.SPD field. Values are: Bits Definition 0000 Reserved 0001 Gen 1 (1.5 Gbps) 0010 Gen 2 (3 Gbps) 0011 Gen 3 (6 Gbps) 0100 - 1111 Reserved |
Reserved | 19 | roRead-only | 0x0 | Reserved |
SAM | 18 | roRead-only | 0x1 | Supports AHCI mode only (SAM): The SATA controller may optionally support AHCI access mechanisms only. A value of 0 indicates that in addition to the native AHCI mechanism (via ABAR), the SATA controller implements a legacy, task-file based register interface such as SFF-8038i. A value of 1 indicates that the SATA controller does not implement a legacy, task-file based register interface. |
SPM | 17 | roRead-only | 0x1 | Supports Port Multiplier (SPM): Indicates whether the HBA can support a Port Multiplier. When set, a Port Multiplier using command-based switching is supported and FIS-based switching may be supported. When cleared to 0, a Port Multiplier is not supported, and a Port Multiplier may not be attached to this HBA. |
FBSS | 16 | roRead-only | 0x1 | FIS-based Switching Supported (FBSS): When set to 1, indicates that the HBA supports Port Multiplier FIS-based switching. When cleared to 0, indicates that the HBA does not support FIS-based switching. This bit shall only be set to 1 if the SPM bit is set to 1. |
PMD | 15 | roRead-only | 0x1 | PIO Multiple DRQ Block (PMD): If set to 1, the HBA supports multiple DRQ block data transfers for the PIO command protocol. If cleared to 0 the HBA only supports single DRQ block data transfers for the PIO command protocol. AHCI 1.2 HBAs shall have this bit set to 1. |
SSC | 14 | roRead-only | 0x1 | Slumber State Capable (SSC): Indicates whether the HBA can support transitions to the Slumber state. When cleared to 0, software must not allow the HBA to initiate transitions to the Slumber state via agressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Slumber requests. When set to 1, HBA and device initiated Slumber requests can be supported. |
PSC | 13 | roRead-only | 0x1 | Partial State Capable (PSC): Indicates whether the HBA can support transitions to the Partial state. When cleared to 0, software must not allow the HBA to initiate transitions to the Partial state via agressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Partial requests. When set to 1, HBA and device initiated Partial requests can be supported. |
NCS | 12:8 | roRead-only | 0x1F | Number of Command Slots (NCS): 0s based value indicating the number of command slots per port supported by this HBA. A minimum of 1 and maximum of 32 slots per port can be supported. The same number of command slots is available on each implemented port. |
CCCS | 7 | roRead-only | 0x1 | Command Completion Coalescing Supported (CCCS): When set to 1, indicates that the HBA supports command completion coalescing as defined in section 11. When command completion coalescing is supported, the HBA has implemented the CCC_CTL and the CCC_PORTS global HBA registers. When cleared to 0, indicates that the HBA does not support command completion coalescing and the CCC_CTL and CCC_PORTS global HBA registers are not implemented. |
EMS | 6 | roRead-only | 0x0 | Enclosure Management Supported (EMS): When set to 1, indicates that the HBA supports enclosure management as defined in section 12. When enclosure management is supported, the HBA has implemented the EM_LOC and EM_CTL global HBA registers. When cleared to 0, indicates that the HBA does not support enclosure management and the EM_LOC and EM_CTL global HBA registers are not implemented. |
SXS | 5 | roRead-only | 0x0 | Supports External SATA (SXS): When set this bit is set to 1, indicates that the HBA has one or more Serial ATA ports that has a signal only connector that is externally accessible (e.g. eSATA connector). If this bit is set to 1, software may refer to the PxCMD.ESP bit to determine whether a specific port has its signal connector externally accessible as a signal only connector (i.e. power is not part of that connector). When the bit is cleared to 0, indicates that the HBA has no Serial ATA ports that have a signal only connector externally accessible. |
NP | 4:0 | roRead-only | 0x0 | Number of Ports (NP): 0s based value indicating the maximum number of ports supported by the HBA silicon. A maximum of 32 ports can be supported. A value of 0h, indicating one port, is the minimum requirement. Note that the number of ports indicated in this field may be more than the number of ports indicated in the PI register. |