Zynq UltraScale+ Devices Register Reference > Module Summary > CSU Module > aes_key_clear (CSU) Register

aes_key_clear (CSU) Register

aes_key_clear (CSU) Register Description

Register Nameaes_key_clear
Relative Address0x0000001014
Absolute Address 0x00FFCA1014 (CSU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAES Key Clear

aes_key_clear (CSU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved 3rwNormal read/write0x0reserved.
Reserved 2rwNormal read/write0x0reserved.
aes_kup_zero 1rwNormal read/write0x0Setting this bit zeroes the KUP register. The zeroization is confirmed by the AES_KUP_ZEROED bit in the AES_STATUS register.
aes_key_zero 0rwNormal read/write0x0Setting this bit zeroes the expanded key from the AES. The zeroization is confirmed by AES_KEY_ZEROED in the AES_STATUS register.