Zynq UltraScale+ Devices Register Reference > Module Summary > SDIO Module > reg_normalintrsts (SDIO) Register

reg_normalintrsts (SDIO) Register

reg_normalintrsts (SDIO) Register Description

Register Namereg_normalintrsts
Relative Address0x0000000030
Absolute Address 0x00FF160030 (SD0)
0x00FF170030 (SD1)
Width16
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionStatus of all
Interrupts

reg_normalintrsts (SDIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
reg_errorintrsts15roRead-only0x0Or of all bits in the Error Interrupt Status Register.
0 No error
1 Error
normalintrsts_bootcomplete14wtcReadable, write a 1 to clear0x0This status is set if the boot operation gets terminated.
0 Boot operation is not terminated
1 Boot operation is terminated
normalintrsts_rcvbootack13wtcReadable, write a 1 to clear0x0This status is set if the boot acknowledge is received from device.
0 Boot ack not recieved
1 Boot ack is recieved
normalintrsts_retuningevent12roRead-only0x0This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning.
0 Re-tuning not required
1 Re-tuning should be performed
normalintrsts_intc11roRead-only0x0This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor.
normalintrsts_intb10roRead-only0x0This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor.
normalintrsts_inta 9roRead-only0x0This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor.
NOTE: INT_A, INT_B, and INT_C are to be implemented based on the Application Requirements. By default these are not implemented as there is no specific requirement from Customers.
normalintrsts_cardintsts 8roRead-only0x0Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to theHost system.
when this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again.
Interrupt detected by DAT[1] is supported
when there is a card per slot. In case of shared bus, interrupt pins are used to detect interrupts. If 000b is set to Interrupt Pin Select in the Shared Bus Control register, this status is effective. Non-zero value is set to Interrupt Pin Select, INT_A, INT_B or INT_C is then used to device interrupts.
Card Interrupt:
0: inactive.
1: active.
normalintrsts_cardremsts 7wtcReadable, write a 1 to clear0x0This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
0 Card State Stable or Debouncing
1 Card Removed
normalintrsts_cardinssts 6wtcReadable, write a 1 to clear0x0This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
0 Card State Stable or Debouncing
1 Card Inserted
normalintrsts_bufrdready 5wtcReadable, write a 1 to clear0x0This status is set if the Buffer Read Enable changes from 0 to 1. 0 Not ready to read buffer,1
Ready to read buffer
normalintrsts_bufwrready 4wtcReadable, write a 1 to clear0x0This status is set if the Buffer Write Enable changes from 0 to 1. 0 Not ready to write to buffer, 1 Ready to write to buffer
normalintrsts_dmainterrupt 3wtcReadable, write a 1 to clear0x0This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser.
0 No DMA Interrupt
1 DMA Interrupt is generated
normalintrsts_blkgapevent 2wtcReadable, write a 1 to clear0x0If the Stop At Block Gap Request in the BlockGap Control Register is set, this bit is set.
Read Transaction:
This bit is set at the falling edge of the DAT Line Active Status (When the transaction is stopped at SD Bus timing. The Read Wait must be supported inorder to use this function).
Write Transaction:
This bit is set at the falling edge of Write Transfer Active Status (After getting CRC status at SD Bus timing).
0 No Block Gap Event
1 Transaction stopped at Block Gap
normalintrsts_xfercomplete 1wtcReadable, write a 1 to clear0x0This bit is set when a read / write transaction is completed.
Read Transaction:
This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (After the last data has been read to the Host Sys- tem). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register (After valid data has been read to the Host System).
Write Transaction:
This bit is set at the falling edge of the DAT Line Active Status. There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. (After valid data is written to the SD card and the busy signal is released).
Note: Transfer Complete has higher priority than Data Time-out Error. If both bits are set to 1, the data transfer can be considered complete.
Note: While performing tuning procedure (Execute Tuning is set to 1), Transfer Complete is not set to 1
0 No Data Transfer Complete,
1 Data Transfer Complete
normalintrsts_cmdcomplete 0wtcReadable, write a 1 to clear0x0This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23)
Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly.
0 No Command Complete,
1 Command Complete