Zynq UltraScale+ Devices Register Reference > Module Summary > STM Module > HEFEAT1R (STM) Register

HEFEAT1R (STM) Register

HEFEAT1R (STM) Register Description

Register NameHEFEAT1R
Relative Address0x0000000DF8
Absolute Address 0x00FE9C0DF8 (CORESIGHT_SOC_STM)
Width32
TyperoRead-only
Reset Value0x00200035
DescriptionRead the features of the STM.

HEFEAT1R (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
HEEXTMUXSIZE30:28roRead-only0Size of Hardware Event external multiplex signals:
3h.
NUMHE23:15roRead-only0x40The number of hardware events supported by the STM:
40h.
HECOMP 5:4roRead-only0x3Data compression on hardware event tracing support.
3h.
HEMASTR 3roRead-only0x0STMHEMASTR support:
0:
HEERR 2roRead-only0x1Hardware event error detection support:
1: implemented
HETER 0roRead-only0x1STMHETER support:
1: implemented