Zynq UltraScale+ Devices Register Reference > Module Summary > SERDES Module > L3_TM_ILL11 (SERDES) Register

L3_TM_ILL11 (SERDES) Register

L3_TM_ILL11 (SERDES) Register Description

Register NameL3_TM_ILL11
Relative Address0x000000D98C
Absolute Address 0x00FD40D98C (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_ILL11 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_ILL11_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
g2a_pcieg1_pll_ctr_11_8_byp_val 7:4rwNormal read/write0x0Value generated by PCW.
g2b_pll_ctr_11_8_byp_val 3:0rwNormal read/write0x0Value generated by PCW.