Zynq UltraScale+ Devices Register Reference > Module Summary > CRF_APB Module > DPLL_TO_LPD_CTRL (CRF_APB) Register

DPLL_TO_LPD_CTRL (CRF_APB) Register

DPLL_TO_LPD_CTRL (CRF_APB) Register Description

Register NameDPLL_TO_LPD_CTRL
Relative Address0x000000004C
Absolute Address 0x00FD1A004C (CRF_APB)
Width16
TyperwNormal read/write
Reset Value0x00000400
DescriptionDPLL to LPD Clock Divisor.

Program divisor for DPLL clock source (in FPD) driven to LPD clock generators. Refer to data sheet for frequency limits.

DPLL_TO_LPD_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15:14rwNormal read/write0x0reserved.
DIVISOR013:8rwNormal read/write0x46-bit divider.
Reserved 7:0rwNormal read/write0x0reserved.