Zynq UltraScale+ Devices Register Reference > Module Summary > USB3_XHCI Module > GEVNTADRLO_0 (USB3_XHCI) Register

GEVNTADRLO_0 (USB3_XHCI) Register

GEVNTADRLO_0 (USB3_XHCI) Register Description

Register NameGEVNTADRLO_0
Relative Address0x000000C400
Absolute Address 0x00FE20C400 (USB3_0_XHCI)
0x00FE30C400 (USB3_1_XHCI)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionGlobal Event Buffer Address (Low) Register
This is an alternate register for the GEVNTADRn register. Instance 0 of an array of 4.

GEVNTADRLO_0 (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EVNTADRLO31:0rwNormal read/write0x0Event Buffer Address (EvntAdrLo)
Holds the lower 32 bits of start address of the external memory for the Event Buffer. During operation, hardware does not update this address.