Zynq UltraScale+ Devices Register Reference > Module Summary > DISPLAY_PORT Module > AV_BUF_HCOUNT_VCOUNT_INT1 (DISPLAY_PORT) Register

AV_BUF_HCOUNT_VCOUNT_INT1 (DISPLAY_PORT) Register

AV_BUF_HCOUNT_VCOUNT_INT1 (DISPLAY_PORT) Register Description

Register NameAV_BUF_HCOUNT_VCOUNT_INT1
Relative Address0x000000B078
Absolute Address 0x00FD4AB078 (DISPLAY_PORT)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAV_BUF_HCOUNT_VCOUNT_INT1: When the early VTC timing values(VCOUNT and HCOUNT) match the values programmed in this register and corresponding interrupt mask is enabled, an interrupt is generated

AV_BUF_HCOUNT_VCOUNT_INT1 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
HCOUNT29:16rwNormal read/write0x0HCOUNT value to match
VCOUNT13:0rwNormal read/write0x0VCOUNT value to match