Zynq UltraScale+ Devices Register Reference > Module Summary > UART Module > Baud_rate_divider (UART) Register

Baud_rate_divider (UART) Register

Baud_rate_divider (UART) Register Description

Register NameBaud_rate_divider
Relative Address0x0000000034
Absolute Address 0x00FF000034 (UART0)
0x00FF010034 (UART1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000000F
DescriptionBaud Rate Divider Register

The baud rate divider register controls how much baud_sample is divided by to generate the baud rate clock enables, baud_rx_rate and baud_tx_rate.

Baud_rate_divider (UART) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved, read as zero, ignored on write.
BDIV 7:0rwNormal read/write0xFBaud rate divider value:
0 - 3: ignored
4 - 255: Baud rate