Zynq UltraScale+ Devices Register Reference > Module Summary > PMU_GLOBAL Module > REQ_SWRST_INT_MASK (PMU_GLOBAL) Register

REQ_SWRST_INT_MASK (PMU_GLOBAL) Register

REQ_SWRST_INT_MASK (PMU_GLOBAL) Register Description

Register NameREQ_SWRST_INT_MASK
Relative Address0x0000000414
Absolute Address 0x00FFD80414 (PMU_GLOBAL)
Width32
TyperoRead-only
Reset Value0xFBF717DF
DescriptionReset Request; Interrupt Mask.
Check the REQ_SWRST_STATUS register bits for more information.

0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only.

REQ_SWRST_INT_MASK (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PL31roRead-only0x1Programmable Logic, PL reset request.
FP30roRead-only0x1Full Power Domain, FPD reset request.
LP29roRead-only0x1Low Power Domain, LPD reset request.
PS_ONLY28roRead-only0x1PS-only reset request.
IOU27roRead-only0x1IOP reset request.
Reserved26roRead-only0x0reserved
USB125roRead-only0x1USB controller 1 reset request.
USB024roRead-only0x1USB controller 0 reset request.
GEM323roRead-only0x1GEM3 reset request.
GEM222roRead-only0x1GEM2 reset request.
GEM121roRead-only0x1GEM1 reset request.
GEM020roRead-only0x1GEM0 reset request.
Reserved19roRead-only0x0reserved
LS_R518roRead-only0x1RPU Lockstep reset request.
R5_117roRead-only0x1RPU core 1 reset request.
R5_016roRead-only0x1RPU core 0 reset request.
Reserved15:13roRead-only0x0reserved
Display_Port12roRead-only0x1Display Port.
Reserved11roRead-only0x0reserved
SATA10roRead-only0x1SATA reset request.
PCIe 9roRead-only0x1PCIe reset request.
GPU 8roRead-only0x1Both GPU Pixel Processors reset request.
PP1 7roRead-only0x1GPU Pixel Processor 1 reset request.
PP0 6roRead-only0x1GPU Pixel Processor 0 reset request.
Reserved 5roRead-only0x0reserved
APU 4roRead-only0x1APU MPCore reset request
ACPU3 3roRead-only0x1APU3 processor reset request.
ACPU2 2roRead-only0x1APU2 processor reset request.
ACPU1 1roRead-only0x1APU1 processor reset request.
ACPU0 0roRead-only0x1APU0 processor reset request.