Zynq UltraScale+ Devices Register Reference > Module Summary > GPU Module

GPU Module

GPU Module Description

Module NameGPU Module
Modules of this TypeGPU
Base Address0x00FD4B0000 (GPU)
DescriptionGraphics Processing Unit, Graphics Processing Unit

GPU Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
GP_CONTR_REG_VSCL_START_ADDR0x000000000032rwNormal read/write0x00000000GP ControlRegister VSCL Start Address
GP_CONTR_REG_VSCL_END_ADDR0x000000000432rwNormal read/write0x00000000GP Control Register VSCL End Address
GP_CONTR_REG_PLBCL_START_ADDR0x000000000832rwNormal read/write0x00000000GP Control Register PLBCL Start Address
GP_CONTR_REG_PLBCL_END_ADDR0x000000000C32rwNormal read/write0x00000000GP Control Register PLBCL End Address
GP_CONTR_REG_PLB_ALLOC_START_ADDR0x000000001032rwNormal read/write0x00000000GP Control Register PLB Allocate Start Address
GP_CONTR_REG_PLB_ALLOC_END_ADDR0x000000001432rwNormal read/write0x00000000GP Control Register PLB Allocate End Address
GP_CONTR_REG_CMD0x000000002032woWrite-only0x00000000GP Control Register Command
GP_CONTR_REG_INT_RAWSTAT0x000000002432rwNormal read/write0x00080000GP Control Register Interrupt Rawstat
GP_CONTR_REG_INT_CLEAR0x000000002832woWrite-only0x00707BFFGP Control Register Interrupt Clear
GP_CONTR_REG_INT_MASK0x000000002C32woWrite-only0x00000000GP Control Register Interrupt Mask
GP_CONTR_REG_INT_STAT0x000000003032roRead-only0x00080000GP Control Register Interrupt Status
GP_CONTR_REG_WRITE_BOUND_LOW0x000000003432rwNormal read/write0x00000000GP Control Register Write Boundary Low
GP_CONTR_REG_WRITE_BOUND_HIGH0x000000003832rwNormal read/write0xFFFFFF00GP Control Register Write Boundary High
GP_CONTR_REG_PERF_CNT_0_ENABLE0x000000003C32rwNormal read/write0x00000000GP Control Register Performance Counter 0 Enable
GP_CONTR_REG_PERF_CNT_1_ENABLE0x000000004032rwNormal read/write0x00000000GP Control Register Performance Counter 1 Enable
GP_CONTR_REG_PERF_CNT_0_SRC0x000000004432rwNormal read/write0x00000000GP Control Register Performance Counter 0 Source
GP_CONTR_REG_PERF_CNT_1_SRC0x000000004832rwNormal read/write0x00000000GP Control Register Performance Counter 1 Source
GP_CONTR_REG_PERF_CNT_0_VAL0x000000004C32roRead-only0x00000000GP Control Register Performance Counter 0 Value
GP_CONTR_REG_PERF_CNT_1_VAL0x000000005032roRead-only0x00000000GP Control Register Performance Counter 1 Value
GP_CONTR_REG_PERF_CNT_0_LIMIT0x000000005432rwNormal read/write0x00000000GP Control Register Performance Counter 0 Limit
GP_CONTR_REG_PERF_CNT_1_LIMIT0x000000005832rwNormal read/write0x00000000GP Control Register Performance Control 1 Limit
GP_CONTR_REG_STATUS0x000000006832roRead-only0x00000000GP Control Register Status
GP_CONTR_REG_VERSION0x000000006C32roRead-only0x00000B07GP Control Register VERSION
GP_CONTR_REG_VSCL_INITIAL_ADDR0x000000008032roRead-only0x00000000GP Control Register VSCL Initial Address
GP_CONTR_REG_PLBCL_INITIAL_ADDR0x000000008432roRead-only0x00000000GP Control Register PLBCL Initial Address
GP_CONTR_REG_WRITE_BOUNDARY_ERROR_ADDR0x000000008832roRead-only0x00000000GP Control Register Write Error Address
GP_CONTR_REG_AXI_BUS_ERROR_STAT0x000000009432roRead-only0x00000000GP Control AXI Bus Error Status
GP_CONTR_REG_WATCHDOG_DISABLE0x00000000A032rwNormal read/write0x00000000GP Control Register Watchdog Disable
GP_CONTR_REG_WATCHDOG_TIMEOUT0x00000000A432rwNormal read/write0x000F4240GP Control Register Watchdog Timeout
VERSION0x000000100032roRead-only0xCAC20000VERSION Register
SIZE0x000000100432roRead-only0x00000000SIZE Register
STATUS0x000000100832roRead-only0x00000000Status Register
COMMAND0x000000101032woWrite-only0x00000000Command Register
CLEAR_PAGE0x000000101432woWrite-only0x00000000Clear Page Register
MAX_READS0x000000101832rwNormal read/write0x0000001CMaximum Reads Register
ENABLE0x000000101C32rwNormal read/write0x00000000Enable Register
PERFCNT_SRC00x000000102032rwNormal read/write0x00000000Performance Counter 0 Source Register
PERFCNT_VAL00x000000102432rwNormal read/write0x00000000Performance Counter 0 Value Register
PERFCNT_SRC10x000000102832rwNormal read/write0x00000000Performance Counter 1 Source Register
PERFCNT_VAL10x000000102C32rwNormal read/write0x00000000Performance Counter 1 Value Register
GP_MMU_DTE_ADDR0x000000300032rwNormal read/write0x00000000MMU Current Page Table Address Register
GP_MMU_STATUS0x000000300432roRead-only0x00000018MMU Status Register
GP_MMU_COMMAND0x000000300832woWrite-only0x00000000MMU Command Register
GP_MMU_PAGE_FAULT_ADDR0x000000300C32roRead-only0x00000000MMU Logical Address
GP_MMU_ZAP_ONE_LINE0x000000301032woWrite-only0x00000000MMU Zap Cache Line Register
GP_MMU_INT_RAWSTAT0x000000301432rwNormal read/write0x00000000MMU Raw Interrupt Status Register
GP_MMU_INT_CLEAR0x000000301832woWrite-only0x00000000MMU Interrupt Clear Register
GP_MMU_INT_MASK0x000000301C32rwNormal read/write0x00000000MMU Interrupt Mask Register
GP_MMU_INT_STATUS0x000000302032roRead-only0x00000000MMU Interrupt Status Register
PP0_MMU_DTE_ADDR0x000000400032rwNormal read/write0x00000000MMU Current Page Table Address Register
PP0_MMU_STATUS0x000000400432roRead-only0x00000018MMU Status Register
PP0_MMU_COMMAND0x000000400832woWrite-only0x00000000MMU Command Register
PP0_MMU_PAGE_FAULT_ADDR0x000000400C32roRead-only0x00000000MMU Logical Address
PP0_MMU_ZAP_ONE_LINE0x000000401032woWrite-only0x00000000MMU Zap Cache Line Register
PP0_MMU_INT_RAWSTAT0x000000401432rwNormal read/write0x00000000MMU Raw Interrupt Status Register
PP0_MMU_INT_CLEAR0x000000401832woWrite-only0x00000000MMU Interrupt Clear Register
PP0_MMU_INT_MASK0x000000401C32rwNormal read/write0x00000000MMU Interrupt Mask Register
PP0_MMU_INT_STATUS0x000000402032roRead-only0x00000000MMU Interrupt Status Register
PP1_MMU_DTE_ADDR0x000000500032rwNormal read/write0x00000000MMU Current Page Table Address Register
PP1_MMU_STATUS0x000000500432roRead-only0x00000018MMU Status Register
PP1_MMU_COMMAND0x000000500832woWrite-only0x00000000MMU Command Register
PP1_MMU_PAGE_FAULT_ADDR0x000000500C32roRead-only0x00000000MMU Logical Address
PP1_MMU_ZAP_ONE_LINE0x000000501032woWrite-only0x00000000MMU Zap Cache Line Register
PP1_MMU_INT_RAWSTAT0x000000501432rwNormal read/write0x00000000MMU Raw Interrupt Status Register
PP1_MMU_INT_CLEAR0x000000501832woWrite-only0x00000000MMU Interrupt Clear Register
PP1_MMU_INT_MASK0x000000501C32rwNormal read/write0x00000000MMU Interrupt Mask Register
PP1_MMU_INT_STATUS0x000000502032roRead-only0x00000000MMU Interrupt Status Register
PP0_REND_LIST_ADDR0x000000800032rwNormal read/write0x00000000Renderer List Address Register
PP0_REND_RSW_BASE0x000000800432rwNormal read/write0x00000000Renderer State Word Base Address Register
PP0_REND_VERTEX_BASE0x000000800832rwNormal read/write0x00000000Renderer Vertex Base Register
PP0_FEATURE_ENABLE0x000000800C32rwNormal read/write0x00000002Feature Enable Register
PP0_Z_CLEAR_VALUE0x000000801032rwNormal read/write0x00000000Z Clear Value Register
PP0_STENCIL_CLEAR_VALUE0x000000801432rwNormal read/write0x00000000Stencil Clear Value Register
PP0_ABGR_CLEAR_VALUE_00x000000801832rwNormal read/write0x00000000ABGR Clear Value 0 Register
PP0_ABGR_CLEAR_VALUE_10x000000801C32rwNormal read/write0x00000000ABGR Clear Value 1 Register
PP0_ABGR_CLEAR_VALUE_20x000000802032rwNormal read/write0x00000000ABGR Clear Value 2 Register
PP0_ABGR_CLEAR_VALUE_30x000000802432rwNormal read/write0x00000000ABGR Clear Value 3 Register
PP0_BOUNDING_BOX_LEFT_RIGHT0x000000802832rwNormal read/write0x00000000Bounding Box Left Right Register
PP0_BOUNDING_BOX_BOTTOM0x000000802C32rwNormal read/write0x00000000Bounding Box Bottom Register
PP0_FS_STACK_ADDR0x000000803032rwNormal read/write0x00000000FS Stack Address Register
PP0_FS_STACK_SIZE_AND_INIT_VAL0x000000803432rwNormal read/write0x00000000FS Stack Size and Initial Value Register
PP0_ORIGIN_OFFSET_X0x000000804032rwNormal read/write0x00000000Origin Offset X Register
PP0_ORIGIN_OFFSET_Y0x000000804432rwNormal read/write0x00000000Origin Offset Y Register
PP0_SUBPIXEL_SPECIFIER0x000000804832rwNormal read/write0x00000075Subpixel Specifier Register
PP0_TIEBREAK_MODE0x000000804C32rwNormal read/write0x00000000Tiebreak mode Register
PP0_PLIST_CONFIG0x000000805032rwNormal read/write0x00000000Polygon List Format Register
PP0_SCALING_CONFIG0x000000805432rwNormal read/write0x00000000Scaling Register
PP0_TILEBUFFER_BITS0x000000805832rwNormal read/write0x00000000Tilebuffer configuration Register
PP0_WB0_SOURCE_SELECT0x000000810032rwNormal read/write0x00000000WB0 Source Select Register
PP0_WB0_TARGET_ADDR0x000000810432rwNormal read/write0x00000000WB0 Target Address Register
PP0_WB0_TARGET_PIXEL_FORMAT0x000000810832rwNormal read/write0x00000000WB0 Target Pixel Format Register
PP0_WB0_TARGET_AA_FORMAT0x000000810C32rwNormal read/write0x00000000WB0 Target AA Format Register
PP0_WB0_TARGET_LAYOUT0x000000811032rwNormal read/write0x00000000WB0 Target Layout
PP0_WB0_TARGET_SCANLINE_LENGTH0x000000811432rwNormal read/write0x00000000WB0 Target Scanline Length
PP0_WB0_TARGET_FLAGS0x000000811832rwNormal read/write0x00000000WB0 Target Flags Register
PP0_WB0_MRT_ENABLE0x000000811C32rwNormal read/write0x00000000WB0 MRT Enable Register
PP0_WB0_MRT_OFFSET0x000000812032rwNormal read/write0x00000000WB0 MRT Offset Register
PP0_WB0_GLOBAL_TEST_ENABLE0x000000812432rwNormal read/write0x00000000WB0 Global Test Enable Register
PP0_WB0_GLOBAL_TEST_REF_VALUE0x000000812832rwNormal read/write0x00000000WB0 Global Test Reference Value Register
PP0_WB0_GLOBAL_TEST_CMP_FUNC0x000000812C32rwNormal read/write0x00000000WB0 Global Test Compare Function Register
PP0_WB1_SOURCE_SELECT0x000000820032rwNormal read/write0x00000000WB1 Source Select Register
PP0_WB1_TARGET_ADDR0x000000820432rwNormal read/write0x00000000WB1 Target Address Register
PP0_WB1_TARGET_PIXEL_FORMAT0x000000820832rwNormal read/write0x00000000WB1 Target Pixel Format Register
PP0_WB1_TARGET_AA_FORMAT0x000000820C32rwNormal read/write0x00000000WB1 Target AA Format Register
PP0_WB1_TARGET_LAYOUT0x000000821032rwNormal read/write0x00000000WB1 Target Layout
PP0_WB1_TARGET_SCANLINE_LENGTH0x000000821432rwNormal read/write0x00000000WB1 Target Scanline Length
PP0_WB1_TARGET_FLAGS0x000000821832rwNormal read/write0x00000000WB1 Target Flags Register
PP0_WB1_MRT_ENABLE0x000000821C32rwNormal read/write0x00000000WB1 MRT Enable Register
PP0_WB1_MRT_OFFSET0x000000822032rwNormal read/write0x00000000WB1 MRT Offset Register
PP0_WB1_GLOBAL_TEST_ENABLE0x000000822432rwNormal read/write0x00000000WB1 Global Test Enable Register
PP0_WB1_GLOBAL_TEST_REF_VALUE0x000000822832rwNormal read/write0x00000000WB1 Global Test Reference Value Register
PP0_WB1_GLOBAL_TEST_CMP_FUNC0x000000822C32rwNormal read/write0x00000000WB1 Global Test Compare Function Register
PP0_WB2_SOURCE_SELECT0x000000830032rwNormal read/write0x00000000WB2 Source Select Register
PP0_WB2_TARGET_ADDR0x000000830432rwNormal read/write0x00000000WB2 Target Address Register
PP0_WB2_TARGET_PIXEL_FORMAT0x000000830832rwNormal read/write0x00000000WB2 Target Pixel Format Register
PP0_WB2_TARGET_AA_FORMAT0x000000830C32rwNormal read/write0x00000000WB2 Target AA Format Register
PP0_WB2_TARGET_LAYOUT0x000000831032rwNormal read/write0x00000000WB2 Target Layout
PP0_WB2_TARGET_SCANLINE_LENGTH0x000000831432rwNormal read/write0x00000000WB2 Target Scanline Length
PP0_WB2_TARGET_FLAGS0x000000831832rwNormal read/write0x00000000WB2 Target Flags Register
PP0_WB2_MRT_ENABLE0x000000831C32rwNormal read/write0x00000000WB2 MRT Enable Register
PP0_WB2_MRT_OFFSET0x000000832032rwNormal read/write0x00000000WB2 MRT Offset Register
PP0_WB2_GLOBAL_TEST_ENABLE0x000000832432rwNormal read/write0x00000000WB2 Global Test Enable Register
PP0_WB2_GLOBAL_TEST_REF_VALUE0x000000832832rwNormal read/write0x00000000WB2 Global Test Reference Value Register
PP0_WB2_GLOBAL_TEST_CMP_FUNC0x000000832C32rwNormal read/write0x00000000WB2 Global Test Compare Function Register
PP0_VERSION0x000000900032roRead-only0x00CD0007Version Register
PP0_CURRENT_REND_LIST_ADDR0x000000900432rwNormal read/write0x00000000Current Renderer List Address Register
PP0_STATUS0x000000900832rwNormal read/write0x00000000Pixel Processor Status Register
PP0_CTRL_MGMT0x000000900C32woWrite-only0x00000000Control Management Register
PP0_LAST_TILE_POS_START0x000000901032roRead-only0x00000000Last Tile Where Processing Started Register
PP0_LAST_TILE_POS_END0x000000901432roRead-only0x00000000Last Tile Where Processing Completed Register
PP0_INT_RAWSTAT0x000000902032rwNormal read/write0x00001000Interrupt Rawstat Register
PP0_INT_CLEAR0x000000902432woWrite-only0x00000000Interrupt Clear Register
PP0_INT_MASK0x000000902832rwNormal read/write0x00000FFFInterrupt Mask Register
PP0_INT_STATUS0x000000902C32rwNormal read/write0x00001000Interrupt Status Register
PP0_WRITE_BOUNDARY_ENABLE0x000000904032rwNormal read/write0x00000000Write Boundary Enable Register
PP0_WRITE_BOUNDARY_LOW0x000000904432rwNormal read/write0x00000000Write Boundary Low Register
PP0_WRITE_BOUNDARY_HIGH0x000000904832rwNormal read/write0x00000000Write Boundary High Register
PP0_WRITE_BOUNDARY_ADDRESS0x000000904C32rwNormal read/write0x00000000Write Boundary Address Register
PP0_BUS_ERROR_STATUS0x000000905032rwNormal read/write0x00000000Bus Error Status Register
PP0_WATCHDOG_DISABLE0x000000906032rwNormal read/write0x00000000Watchdog Disable Register
PP0_WATCHDOG_TIMEOUT0x000000906432rwNormal read/write0x00000000Watchdog Timeout Register
PP0_PERF_CNT_0_ENABLE0x000000908032rwNormal read/write0x00000000Performance Counter 0 Enable Register
PP0_PERF_CNT_0_SRC0x000000908432rwNormal read/write0x00000000Performance Counter 0 SRC Register
PP0_PERF_CNT_0_LIMIT0x000000908832rwNormal read/write0x00000000Performance Counter 0 Limit Register
PP0_PERF_CNT_0_VALUE0x000000908C32rwNormal read/write0x00000000Performance Counter 0 Value Register
PP0_PERF_CNT_1_ENABLE0x00000090A032rwNormal read/write0x00000000Performance Counter 0 Enable Register
PP0_PERF_CNT_1_SRC0x00000090A432rwNormal read/write0x00000000Performance Counter 1 SRC Register
PP0_PERF_CNT_1_LIMIT0x00000090A832rwNormal read/write0x00000000Performance Counter 1 Limit Register
PP0_PERF_CNT_1_VALUE0x00000090AC32rwNormal read/write0x00000000Performance Counter 1 Value Register
PP0_PERFMON_CONTR0x00000090B032rwNormal read/write0x00000000Performance Monitor Control Register
PP0_PERFMON_BASE0x00000090B432rwNormal read/write0x00000000Performance Monitor Base Address Register
PP1_REND_LIST_ADDR0x000000A00032rwNormal read/write0x00000000Renderer List Address Register
PP1_REND_RSW_BASE0x000000A00432rwNormal read/write0x00000000Renderer State Word Base Address Register
PP1_REND_VERTEX_BASE0x000000A00832rwNormal read/write0x00000000Renderer Vertex Base Register
PP1_FEATURE_ENABLE0x000000A00C32rwNormal read/write0x00000000Feature Enable Register
PP1_Z_CLEAR_VALUE0x000000A01032rwNormal read/write0x00000000Z Clear Value Register
PP1_STENCIL_CLEAR_VALUE0x000000A01432rwNormal read/write0x00000000Stencil Clear Value Register
PP1_ABGR_CLEAR_VALUE_00x000000A01832rwNormal read/write0x00000000ABGR Clear Value 0 Register
PP1_ABGR_CLEAR_VALUE_10x000000A01C32rwNormal read/write0x00000000ABGR Clear Value 1 Register
PP1_ABGR_CLEAR_VALUE_20x000000A02032rwNormal read/write0x00000000ABGR Clear Value 2 Register
PP1_ABGR_CLEAR_VALUE_30x000000A02432rwNormal read/write0x00000000ABGR Clear Value 3 Register
PP1_BOUNDING_BOX_LEFT_RIGHT0x000000A02832rwNormal read/write0x00000000Bounding Box Left Right Register
PP1_BOUNDING_BOX_BOTTOM0x000000A02C32rwNormal read/write0x00000000Bounding Box Bottom Register
PP1_FS_STACK_ADDR0x000000A03032rwNormal read/write0x00000000FS Stack Address Register
PP1_FS_STACK_SIZE_AND_INIT_VAL0x000000A03432rwNormal read/write0x00000000FS Stack Size and Initial Value Register
PP1_ORIGIN_OFFSET_X0x000000A04032rwNormal read/write0x00000000Origin Offset X Register
PP1_ORIGIN_OFFSET_Y0x000000A04432rwNormal read/write0x00000000Origin Offset Y Register
PP1_SUBPIXEL_SPECIFIER0x000000A04832rwNormal read/write0x00000000Subpixel Specifier Register
PP1_TIEBREAK_MODE0x000000A04C32rwNormal read/write0x00000000Tiebreak mode Register
PP1_PLIST_CONFIG0x000000A05032rwNormal read/write0x00000000Polygon List Format Register
PP1_SCALING_CONFIG0x000000A05432rwNormal read/write0x00000000Scaling Register
PP1_TILEBUFFER_BITS0x000000A05832rwNormal read/write0x00000000Tilebuffer configuration Register
PP1_WB0_SOURCE_SELECT0x000000A10032rwNormal read/write0x00000000WB0 Source Select Register
PP1_WB0_TARGET_ADDR0x000000A10432rwNormal read/write0x00000000WB0 Target Address Register
PP1_WB0_TARGET_PIXEL_FORMAT0x000000A10832rwNormal read/write0x00000000WB0 Target Pixel Format Register
PP1_WB0_TARGET_AA_FORMAT0x000000A10C32rwNormal read/write0x00000000WB0 Target AA Format Register
PP1_WB0_TARGET_LAYOUT0x000000A11032rwNormal read/write0x00000000WB0 Target Layout
PP1_WB0_TARGET_SCANLINE_LENGTH0x000000A11432rwNormal read/write0x00000000WB0 Target Scanline Length
PP1_WB0_TARGET_FLAGS0x000000A11832rwNormal read/write0x00000000WB0 Target Flags Register
PP1_WB0_MRT_ENABLE0x000000A11C32rwNormal read/write0x00000000WB0 MRT Enable Register
PP1_WB0_MRT_OFFSET0x000000A12032rwNormal read/write0x00000000WB0 MRT Offset Register
PP1_WB0_GLOBAL_TEST_ENABLE0x000000A12432rwNormal read/write0x00000000WB0 Global Test Enable Register
PP1_WB0_GLOBAL_TEST_REF_VALUE0x000000A12832rwNormal read/write0x00000000WB0 Global Test Reference Value Register
PP1_WB0_GLOBAL_TEST_CMP_FUNC0x000000A12C32rwNormal read/write0x00000000WB0 Global Test Compare Function Register
PP1_WB1_SOURCE_SELECT0x000000A20032rwNormal read/write0x00000000WB1 Source Select Register
PP1_WB1_TARGET_ADDR0x000000A20432rwNormal read/write0x00000000WB1 Target Address Register
PP1_WB1_TARGET_PIXEL_FORMAT0x000000A20832rwNormal read/write0x00000000WB1 Target Pixel Format Register
PP1_WB1_TARGET_AA_FORMAT0x000000A20C32rwNormal read/write0x00000000WB1 Target AA Format Register
PP1_WB1_TARGET_LAYOUT0x000000A21032rwNormal read/write0x00000000WB1 Target Layout
PP1_WB1_TARGET_SCANLINE_LENGTH0x000000A21432rwNormal read/write0x00000000WB1 Target Scanline Length
PP1_WB1_TARGET_FLAGS0x000000A21832rwNormal read/write0x00000000WB1 Target Flags Register
PP1_WB1_MRT_ENABLE0x000000A21C32rwNormal read/write0x00000000WB1 MRT Enable Register
PP1_WB1_MRT_OFFSET0x000000A22032rwNormal read/write0x00000000WB1 MRT Offset Register
PP1_WB1_GLOBAL_TEST_ENABLE0x000000A22432rwNormal read/write0x00000000WB1 Global Test Enable Register
PP1_WB1_GLOBAL_TEST_REF_VALUE0x000000A22832rwNormal read/write0x00000000WB1 Global Test Reference Value Register
PP1_WB1_GLOBAL_TEST_CMP_FUNC0x000000A22C32rwNormal read/write0x00000000WB1 Global Test Compare Function Register
PP1_WB2_SOURCE_SELECT0x000000A30032rwNormal read/write0x00000000WB2 Source Select Register
PP1_WB2_TARGET_ADDR0x000000A30432rwNormal read/write0x00000000WB2 Target Address Register
PP1_WB2_TARGET_PIXEL_FORMAT0x000000A30832rwNormal read/write0x00000000WB2 Target Pixel Format Register
PP1_WB2_TARGET_AA_FORMAT0x000000A30C32rwNormal read/write0x00000000WB2 Target AA Format Register
PP1_WB2_TARGET_LAYOUT0x000000A31032rwNormal read/write0x00000000WB2 Target Layout
PP1_WB2_TARGET_SCANLINE_LENGTH0x000000A31432rwNormal read/write0x00000000WB2 Target Scanline Length
PP1_WB2_TARGET_FLAGS0x000000A31832rwNormal read/write0x00000000WB2 Target Flags Register
PP1_WB2_MRT_ENABLE0x000000A31C32rwNormal read/write0x00000000WB2 MRT Enable Register
PP1_WB2_MRT_OFFSET0x000000A32032rwNormal read/write0x00000000WB2 MRT Offset Register
PP1_WB2_GLOBAL_TEST_ENABLE0x000000A32432rwNormal read/write0x00000000WB2 Global Test Enable Register
PP1_WB2_GLOBAL_TEST_REF_VALUE0x000000A32832rwNormal read/write0x00000000WB2 Global Test Reference Value Register
PP1_WB2_GLOBAL_TEST_CMP_FUNC0x000000A32C32rwNormal read/write0x00000000WB2 Global Test Compare Function Register
PP1_VERSION0x000000B00032rwNormal read/write0x00CD0007Version Register
PP1_CURRENT_REND_LIST_ADDR0x000000B00432rwNormal read/write0x00000000Current Renderer List Address Register
PP1_STATUS0x000000B00832rwNormal read/write0x00000000Pixel Processor Status Register
PP1_CTRL_MGMT0x000000B00C32rwNormal read/write0x00000000Control Management Register
PP1_LAST_TILE_POS_START0x000000B01032rwNormal read/write0x00000000Last Tile Where Processing Started Register
PP1_LAST_TILE_POS_END0x000000B01432rwNormal read/write0x00000000Last Tile Where Processing Completed Register
PP1_INT_RAWSTAT0x000000B02032rwNormal read/write0x00000000Interrupt Rawstat Register
PP1_INT_CLEAR0x000000B02432rwNormal read/write0x00000000Interrupt Clear Register
PP1_INT_MASK0x000000B02832rwNormal read/write0x00000FFFInterrupt Mask Register
PP1_INT_STATUS0x000000B02C32rwNormal read/write0x00000000Interrupt Status Register
PP1_WRITE_BOUNDARY_ENABLE0x000000B04032rwNormal read/write0x00000000Write Boundary Enable Register
PP1_WRITE_BOUNDARY_LOW0x000000B04432rwNormal read/write0x00000000Write Boundary Low Register
PP1_WRITE_BOUNDARY_HIGH0x000000B04832rwNormal read/write0x00000000Write Boundary High Register
PP1_WRITE_BOUNDARY_ADDRESS0x000000B04C32rwNormal read/write0x00000000Write Boundary Address Register
PP1_BUS_ERROR_STATUS0x000000B05032rwNormal read/write0x00000000Bus Error Status Register
PP1_WATCHDOG_DISABLE0x000000B06032rwNormal read/write0x00000000Watchdog Disable Register
PP1_WATCHDOG_TIMEOUT0x000000B06432rwNormal read/write0x00000000Watchdog Timeout Register
PP1_PERF_CNT_0_ENABLE0x000000B08032rwNormal read/write0x00000000WB2 Global Test Compare Function Register
PP1_PERF_CNT_0_SRC0x000000B08432rwNormal read/write0x00000000Performance Counter 0 SRC Register
PP1_PERF_CNT_0_LIMIT0x000000B08832rwNormal read/write0x00000000Performance Counter 0 Limit Register
PP1_PERF_CNT_0_VALUE0x000000B08C32rwNormal read/write0x00000000Performance Counter 0 Value Register
PP1_PERF_CNT_1_ENABLE0x000000B0A032rwNormal read/write0x00000000Performance Counter 1 Enable Register
PP1_PERF_CNT_1_SRC0x000000B0A432rwNormal read/write0x00000000Performance Counter 1 SRC Register
PP1_PERF_CNT_1_LIMIT0x000000B0A832rwNormal read/write0x00000000Performance Counter 1 Limit Register
PP1_PERF_CNT_1_VALUE0x000000B0AC32rwNormal read/write0x00000000Performance Counter 1 Value Register
PP1_PERFMON_CONTR0x000000B0B032rwNormal read/write0x00000000Performance Monitor Control Register
PP1_PERFMON_BASE0x000000B0B432rwNormal read/write0x00000000Performance Monitor Base Address Register