Zynq UltraScale+ Devices Register Reference > Module Summary > PCIE_ATTRIB Module > ATTR_38 (PCIE_ATTRIB) Register

ATTR_38 (PCIE_ATTRIB) Register

ATTR_38 (PCIE_ATTRIB) Register Description

Register NameATTR_38
Relative Address0x0000000098
Absolute Address 0x00FD480098 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000120
DescriptionATTR_38

This register should only be written to during reset of the PCIe block

ATTR_38 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_mps_force 9rwNormal read/write0x0If set, causes the core to use the MPS value on cfg_force_mps for checking the payload size of received TLPs and for replay/acknak timeouts, instead of using Device Ctrl[7:5]. It does not change Device Ctrl[7:5].
attr_link_status_slot_clock_config 8rwNormal read/write0x1Slot Clock Configuration.
Indicates where the component uses the same physical reference clock that the platform provides on the connector.
For a port that connects to the slot, indicates that it uses a clock with a common source to that used by the slot. For an adaptor inserted in the slot, indicates that it uses the same clock source as the slot, not a locally-derived clock source.
Transferred to the Link Status register.
attr_link_ctrl2_target_link_speed 7:4rwNormal read/write0x2Set an upper limit on the speed advertised by the Upstream component (Root). The value is transferred to the Link Control2[3:0] Register.
attr_link_ctrl2_hw_autonomous_speed_disable 3rwNormal read/write0x0When TRUE disables hardware from changing the link speed for reasons other than reliability. The value is transferred to the Link Control2 Register[5].
attr_link_ctrl2_deemphasis 2rwNormal read/write0x0Sets the de-emphasis level used by upstream component in 5.0 GT/s mode. The value is transferred to the Link Control2 Register[12].
0b = -6db
1b = -3.5db.
attr_link_control_rcb 1rwNormal read/write0x01 implies read completion boundary is 128 bits; 0 implies 64 bits.
Transferred to the Link Control register.
Only non-zero for a downstream-facing port.
attr_link_cap_surprise_down_error_capable 0rwNormal read/write0x0Set on a downstream port if the detection and reporting of a surprise down event is supported