Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedMon Oct 20 20:24:47 2014 product_versionVivado v2013.2 (64-bit)
build_version272601 os_platformWIN64
registration_id1_2_4_3 tool_flowVivado
betaFALSE route_designTRUE
target_familykintex7 target_devicexc7k70t
target_packagefbg484 target_speed-2
random_id24b89f3744455746b2a958f17ff67446 project_id2f3d7a5a3aae456a9552c8400643c81a
project_iteration25

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-3720QM CPU @ 2.60GHz cpu_speed2591 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=24 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1
other_data
batchmode=1 guimode=30

unisim_transformation
pre_unisim_transformation
bufg=3 bufhce=1 carry4=27 fdpe=7
fdre=428 fdse=22 fifo18e1=1 gnd=21
ibuf=3 ibufds=1 lut1=71 lut2=85
lut3=157 lut4=91 lut5=94 lut6=337
mmcme2_adv=1 muxf7=1 obuf=13 oddr=1
ramb18e1=1 vcc=29
post_unisim_transformation
bufg=3 bufhce=1 carry4=27 fdpe=7
fdre=428 fdse=22 fifo18e1=1 gnd=21
ibuf=3 ibufds=1 lut1=71 lut2=85
lut3=157 lut4=91 lut5=94 lut6=337
mmcme2_adv=1 muxf7=1 obuf=13 oddr=1
ramb18e1=1 vcc=29

power_opt_design
usage
flow_state=post_synth
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
clk_wiz_v5_0/1
iptotal=1 component_name=clk_core use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
feedback_source=FDBK_AUTO primitive=MMCME2 num_out_clk=2 clkin1_period=5.0
clkin2_period=10.0 use_power_down=false use_reset=true use_locked=true
use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA manual_override=false
fifo_generator_v10_0/1
iptotal=1 x_ipproduct=Vivado 2013.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=fifo_generator x_ipversion=10.0 x_ipcorerevision=1 x_iplanguage=VERILOG
c_common_clock=0 c_count_type=0 c_data_count_width=11 c_default_value=BlankString
c_din_width=8 c_dout_rst_val=0 c_dout_width=8 c_enable_rlocs=0
c_family=kintex7 c_full_flags_rst_val=0 c_has_almost_empty=0 c_has_almost_full=0
c_has_backup=0 c_has_data_count=0 c_has_int_clk=0 c_has_meminit_file=0
c_has_overflow=0 c_has_rd_data_count=0 c_has_rd_rst=0 c_has_rst=1
c_has_srst=0 c_has_underflow=0 c_has_valid=0 c_has_wr_ack=0
c_has_wr_data_count=0 c_has_wr_rst=0 c_implementation_type=6 c_init_wr_pntr_val=0
c_memory_type=4 c_mif_file_name=BlankString c_optimization_mode=0 c_overflow_low=0
c_preload_latency=0 c_preload_regs=1 c_prim_fifo_type=2kx9 c_prog_empty_thresh_assert_val=6
c_prog_empty_thresh_negate_val=7 c_prog_empty_type=0 c_prog_full_thresh_assert_val=2038 c_prog_full_thresh_negate_val=2037
c_prog_full_type=0 c_rd_data_count_width=11 c_rd_depth=2048 c_rd_freq=193
c_rd_pntr_width=11 c_underflow_low=0 c_use_dout_rst=0 c_use_ecc=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wr_ack_low=0 c_wr_data_count_width=11 c_wr_depth=2048 c_wr_freq=200
c_wr_pntr_width=11 c_wr_response_latency=1 c_msgon_val=1 c_enable_rst_sync=1
c_error_injection_type=0 c_synchronizer_stage=2 c_interface_type=0 c_axi_type=0
c_has_axi_wr_channel=0 c_has_axi_rd_channel=0 c_has_slave_ce=0 c_has_master_ce=0
c_add_ngc_constraint=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_axi_id_width=4 c_axi_addr_width=32 c_axi_data_width=64 c_has_axi_awuser=0
c_has_axi_wuser=0 c_has_axi_buser=0 c_has_axi_aruser=0 c_has_axi_ruser=0
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_wuser_width=1 c_axi_buser_width=1
c_axi_ruser_width=1 c_has_axis_tdata=0 c_has_axis_tid=0 c_has_axis_tdest=0
c_has_axis_tuser=0 c_has_axis_tready=1 c_has_axis_tlast=0 c_has_axis_tstrb=0
c_has_axis_tkeep=0 c_axis_tdata_width=64 c_axis_tid_width=8 c_axis_tdest_width=4
c_axis_tuser_width=4 c_axis_tstrb_width=8 c_axis_tkeep_width=8 c_wach_type=0
c_wdch_type=0 c_wrch_type=0 c_rach_type=0 c_rdch_type=0
c_axis_type=0 c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1
c_implementation_type_rach=1 c_implementation_type_rdch=1 c_implementation_type_axis=1 c_application_type_wach=0
c_application_type_wdch=0 c_application_type_wrch=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_axis=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_ecc_rach=0 c_use_ecc_rdch=0 c_use_ecc_axis=0 c_error_injection_type_wach=0
c_error_injection_type_wdch=0 c_error_injection_type_wrch=0 c_error_injection_type_rach=0 c_error_injection_type_rdch=0
c_error_injection_type_axis=0 c_din_width_wach=32 c_din_width_wdch=64 c_din_width_wrch=2
c_din_width_rach=32 c_din_width_rdch=64 c_din_width_axis=1 c_wr_depth_wach=16
c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_axis=1024 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10 c_wr_pntr_width_axis=10 c_has_data_counts_wach=0
c_has_data_counts_wdch=0 c_has_data_counts_wrch=0 c_has_data_counts_rach=0 c_has_data_counts_rdch=0
c_has_data_counts_axis=0 c_has_prog_flags_wach=0 c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0
c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_axis=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_axis=0 c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023
c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_axis=1023 c_prog_empty_type_wach=0
c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_axis=0 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_axis=1022 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_axis=0

report_utilization
slice_logic
slice_luts_used=702 slice_luts_loced=0 slice_luts_available=41000 slice_luts_util_percentage=1.71
lut_as_logic_used=702 lut_as_logic_loced=0 lut_as_logic_available=41000 lut_as_logic_util_percentage=1.71
lut_as_memory_used=0 lut_as_memory_loced=0 lut_as_memory_available=13400 lut_as_memory_util_percentage=0.00
slice_registers_used=445 slice_registers_loced=0 slice_registers_available=82000 slice_registers_util_percentage=0.54
register_as_flip_flop_used=445 register_as_flip_flop_loced=0 register_as_flip_flop_available=82000 register_as_flip_flop_util_percentage=0.54
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=82000 register_as_latch_util_percentage=0.00
f7_muxes_used=1 f7_muxes_loced=0 f7_muxes_available=20500 f7_muxes_util_percentage=0.01
f8_muxes_used=0 f8_muxes_loced=0 f8_muxes_available=10250 f8_muxes_util_percentage=0.00
slice_used=252 slice_loced=0 slice_available=10250 slice_util_percentage=2.45
lut_as_logic_used=702 lut_as_logic_loced=0 lut_as_logic_available=41000 lut_as_logic_util_percentage=1.71
using_o5_output_only_used=2 using_o5_output_only_loced= using_o6_output_only_used=576 using_o6_output_only_loced=
using_o5_and_o6_used=124 using_o5_and_o6_loced= lut_as_memory_used=0 lut_as_memory_loced=0
lut_as_memory_available=13400 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_loced=0
lut_as_shift_register_used=0 lut_as_shift_register_loced=0 lut_flip_flop_pairs_used=797 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=41000 lut_flip_flop_pairs_util_percentage=1.94 fully_used_lut_ff_pairs_used=276 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=97 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=424 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=37 minimum_number_of_registers_lost_to_control_set_restriction_used=123(Lost)
memory
block_ram_tile_used=1 block_ram_tile_loced=0 block_ram_tile_available=135 block_ram_tile_util_percentage=0.74
ramb36_fifo*_used=1 ramb36_fifo*_loced=0 ramb36_fifo*_available=135 ramb36_fifo*_util_percentage=0.74
fifo18e1_only_used=1 ramb18_used=1 ramb18_loced=0 ramb18_available=270
ramb18_util_percentage=0.37 ramb18e1_only_used=1
dsp
dsps_used=0 dsps_loced=0 dsps_available=240 dsps_util_percentage=0.00
io_and_gtx
bonded_iob_used=18 bonded_iob_loced=0 bonded_iob_available=285 bonded_iob_util_percentage=6.31
iob_master_pads_used=8 iob_master_pads_loced= iob_slave_pads_used=9 iob_slave_pads_loced=
iob_flip_flops_used=12 iob_flip_flops_loced=12 bonded_ipads_used=0 bonded_ipads_loced=0
bonded_ipads_available=14 bonded_ipads_util_percentage=0.00 bonded_opads_used=0 bonded_opads_loced=0
bonded_opads_available=8 bonded_opads_util_percentage=0.00 gtxe2_channel_used=0 gtxe2_channel_loced=0
gtxe2_channel_available=4 gtxe2_channel_util_percentage=0.00 gtxe2_common_used=0 gtxe2_common_loced=0
gtxe2_common_available=1 gtxe2_common_util_percentage=0.00 ibufgds_used=0 ibufgds_loced=0
ibufgds_available=275 ibufgds_util_percentage=0.00 idelayctrl_used=0 idelayctrl_loced=0
idelayctrl_available=6 idelayctrl_util_percentage=0.00 in_fifo_used=0 in_fifo_loced=0
in_fifo_available=24 in_fifo_util_percentage=0.00 out_fifo_used=0 out_fifo_loced=0
out_fifo_available=24 out_fifo_util_percentage=0.00 phaser_ref_used=0 phaser_ref_loced=0
phaser_ref_available=6 phaser_ref_util_percentage=0.00 phy_control_used=0 phy_control_loced=0
phy_control_available=6 phy_control_util_percentage=0.00 phaser_out_phaser_out_phy_used=0 phaser_out_phaser_out_phy_loced=0
phaser_out_phaser_out_phy_available=24 phaser_out_phaser_out_phy_util_percentage=0.00 phaser_in_phaser_in_phy_used=0 phaser_in_phaser_in_phy_loced=0
phaser_in_phaser_in_phy_available=24 phaser_in_phaser_in_phy_util_percentage=0.00 idelaye2_idelaye2_finedelay_used=0 idelaye2_idelaye2_finedelay_loced=0
idelaye2_idelaye2_finedelay_available=300 idelaye2_idelaye2_finedelay_util_percentage=0.00 odelaye2_odelaye2_finedelay_used=0 odelaye2_odelaye2_finedelay_loced=0
odelaye2_odelaye2_finedelay_available=100 odelaye2_odelaye2_finedelay_util_percentage=0.00 ibufds_gte2_used=0 ibufds_gte2_loced=0
ibufds_gte2_available=4 ibufds_gte2_util_percentage=0.00 ilogic_used=0 ilogic_loced=0
ilogic_available=285 ilogic_util_percentage=0.00 ologic_used=13 ologic_loced=13
ologic_available=285 ologic_util_percentage=4.56 outff_register_used=12 outff_register_loced=12
outff_oddr_register_used=1 outff_oddr_register_loced=
clocking
bufgctrl_used=3 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=9.37
bufio_used=0 bufio_loced=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=1 mmcme2_adv_loced=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=16.66
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=1 bufhce_loced=0 bufhce_available=96 bufhce_util_percentage=1.04
bufr_used=0 bufr_loced=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_loced=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=428 lut6_used=312 lut3_used=161 lut5_used=110
lut2_used=91 lut4_used=89 lut1_used=63 carry4_used=27
fdse_used=22 obuf_used=13 fdpe_used=7 ibuf_used=3
bufg_used=3 ramb18e1_used=1 oddr_used=1 muxf7_used=1
mmcme2_adv_used=1 ibufds_used=1 fifo18e1_used=1 bufhce_used=1

synthesis
command_line_options
-part=xc7k70tfbg484-2 -name=default::[not_specified] -top=wave_gen -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -flatten_hierarchy=default::rebuilt
-gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified] -bufg=default::12
-fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto
-keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::1
usage
elapsed=00:01:10s memory_peak=727.637MB memory_gain=559.547MB