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PLATFORM_VER      	:= xilinx_vck190_base_202520_1
PLATFORM_REPO_PATHS 	:= /opt/amd/2025.2/Vitis/base_platforms
PLATFORM          	:= $(PLATFORM_REPO_PATHS)/xilinx_vck190_base_202520_1/xilinx_vck190_base_202520_1.xpfm

MAP_OPT  	:= -Xmapper=BufferOptLevel0
PL_FREQ       	:= --pl-freq=500.0
SIM_OUTPUT     	:= aiesimulator_output
WORK_DIR       	:= Work
LOG_FILE      	:= log

PROJECT		:= ../src/project.cpp
AIE_OUTPUT      := libadf.a

AIE_FLAGS       := --platform=$(PLATFORM) ${PROJECT} ${MAP_OPT} ${PL_FREQ} -workdir=${WORK_DIR}

.PHONY: help clean all

help:
	echo "Makefile Usage:"
	echo "  make all"
	echo "      Command to generate everything for this design"
	echo ""
	echo "  make clean"
	echo "      Command to remove all the generated files."

x86:
	v++ -c --mode aie --target x86sim --platform=${PLATFORM} --include "$XILINX_VITIS/aietools/include" --include "./src" --include "./src/data" --include "./" --work_dir=./Work ../src/project.cpp

x86sim:
	x86simulator --pkg-dir=${WORK_DIR} --dump |& tee -a ${LOG_FILE}

aie:
	v++ -c --mode aie --target hw --platform=${PLATFORM} --include "$XILINX_VITIS/aietools/include" --include "./src" --include "./src/data" --include "./" --work_dir=./Work ../src/project.cpp

aiesim:
	aiesimulator --pkg-dir=${WORK_DIR} -o ${SIM_OUTPUT} |& tee -a ${LOG_FILE}

#profile:# In case if you want to profile
#	aiesimulator --pkg-dir=${WORK_DIR} -o ${SIM_OUTPUT} --profile --online -wdb -ctf |& tee -a ${LOG_FILE}

clean:
	rm -rf Work Work* ${WORK_DIR} libadf.a vitis_design_wrapper*
	rm -rf .Xil
	rm -rf aiesimulator_output aiesimulator.log
	rm -rf x86simulator_output
	rm -rf log log* ${LOG_FILE}
	rm -rf *.xpe *.elf *.db *.soln Map_* xnw* *.lp *.log .xil .Xil *.lp *.db *.log *.exe *.vcd *.json
	rm -rf vitis_analyzer* pl_sample_counts* function_wdb_dir
	rm -rf temp ISS_RPC_SERVER_PORT
	rm -rf system*.* .crashReporter .AIE_SIM_CMD_LINE_OPTIONS
