# *******************************************************************************
# Vendor: Xilinx 
# Associated Filename: run_hls.tcl
# Purpose: Tcl commands to setup a Vivado HLS prject 
# Device: All 
# Revision History: March 1, 2013 - initial release
#                                                 
# *******************************************************************************
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##############################################
# Project settings

# Create a project
open_component	-reset adders_prj -flow_target vivado

# The source file and test bench
add_files			adders.c
add_files -tb	adders_test.c
# Specify the top-level function for synthesis
set_top		adders

###########################
# Solution settings

# Create solution1
open_solution -reset solution1

# Specify a Xilinx device and clock period
# - Do not specify a clock uncertainty (margin)
# - Let the  margin to default to 12.5% of clock period
set_part {xczu7ev-ffvc1156-2-e}
create_clock -period 0.5

# Simulate the C code 
csim_design

csynth_design

open_solution solution2

# Apply the block-level protocols directive
set_directive_interface -mode ap_ctrl_none "adders"

# Synthesize the design 
csynth_design

exit
