xpm_cdc.sv,systemverilog,xpm,../ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_memory.sv,systemverilog,xpm,../ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_VCOMP.vhd,vhdl,xpm,../ip/xpm/xpm_VCOMP.vhd,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_14,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_14,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_14,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
char_fifo.v,verilog,xil_defaultlib,../../../../wave_gen.gen/sources_1/ip/char_fifo/sim/char_fifo.v,incdir="../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
glbl.v,Verilog,xil_defaultlib,glbl.v
