-------------------------------------
| Tool Version : Vivado v.2025.1
| Date         : Fri Jul 11 11:45:06 2025
| Host         : CustEd-VM
| Design       : design_1
| Device       : xcsu35p-sbvb625-2-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 3
	Number of BUFGCE: 2
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 1
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 3 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
Pre-CRP Checker took 0 secs

********************************
Clock Net Route Info (CRP Input)
********************************
Clock 1: clk_fab
	Clock source type: BUFG_DIV
	Clock source region: X0Y1
	Clock regions with locked loads: X0Y1 
	initial rect ((0, 0), (0, 1))

Clock 2: clk
	Clock source type: BUFGCE
	Clock source region: X0Y1
	Clock regions with locked loads: X0Y1 
	initial rect ((0, 1), (0, 1))

Clock 3: clkref
	Clock source type: BUFGCE
	Clock source region: X0Y1
	Clock regions with locked loads: X0Y1 
	initial rect ((0, 0), (0, 1))



*****************
User Constraints:
*****************
No user constraints found


