2015.3:
 * Version 3.0 (Rev. 9)
 * family name change - zynqplus and virtexplus
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Revision change in one or more subcores

2015.2.1:
 * Version 3.0 (Rev. 8)
 * No changes

2015.2:
 * Version 3.0 (Rev. 8)
 * Added Support for zynque and virtexum

2015.1:
 * Version 3.0 (Rev. 7)
 * Added synchronizer for cdc

2014.4.1:
 * Version 3.0 (Rev. 6)
 * Updated example XDC pin location constraints for new devices

2014.4:
 * Version 3.0 (Rev. 5)
 * Internal device family change, no functional changes
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time

2014.3:
 * Version 3.0 (Rev. 4)
 * activity generation bug fix

2014.2:
 * Version 3.0 (Rev. 3)
 * simplified constraint defination
 * Improved Distributed RAM usage

2014.1:
 * Version 3.0 (Rev. 2)
 * Kintex UltraScale support
 * xsdb stitching enhancements
 * Internal device family name change, no functional changes

2013.4:
 * Version 3.0 (Rev. 1)
 * Kintex UltraScale Pre-Production support

2013.3:
 * Version 3.0
 * Port Names changed to lower case

2013.2:
 * Version 2.0 (Rev. 1)
 * Improved support for multiple instances.
 * Improved Timing
 * Made the following package changes for XQ7A200, 'FB484 to RB484, FB676 to RB676, SB484 to RS484 and XQ7Z030, FB484 to RB484, Removed -2L support from the XQ7V690T and XQ7A, all to match silicon planning changes'

2013.1:
 * Version 2.0
 * Native Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

(c) Copyright 2000 - 2015 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.

DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.

CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
//<copyright-disclaimer-start>
//  **************************************************************************************************************
//  * © 2026 Advanced Micro Devices, Inc. All rights reserved.                                                   *
//  * DISCLAIMER                                                                                                 *
//  * The information contained herein is for informational purposes only, and is subject to change              *
//  * without notice. While every precaution has been taken in the preparation of this document, it              *
//  * may contain technical inaccuracies, omissions and typographical errors, and AMD is under no                *
//  * obligation to update or otherwise correct this information.  Advanced Micro Devices, Inc. makes            *
//  * no representations or warranties with respect to the accuracy or completeness of the contents of           *
//  * this document, and assumes no liability of any kind, including the implied warranties of noninfringement,  *
//  * merchantability or fitness for particular purposes, with respect to the operation or use of AMD            *
//  * hardware, software or other products described herein.  No license, including implied or                   *
//  * arising by estoppel, to any intellectual property rights is granted by this document.  Terms and           *
//  * limitations applicable to the purchase or use of AMD’s products are as set forth in a signed agreement     *
//  * between the parties or in AMD's Standard Terms and Conditions of Sale. GD-18                               *
//  *                                                                                                            *
//  **************************************************************************************************************
//<copyright-disclaimer-end>
