-------------------------------------
| Tool Version : Vivado v.2025.2
| Date         : Mon Jan 12 17:58:42 2026
| Host         : amd-VirtualBox
| Design       : design_1
| Device       : xczu7ev-ffvc1156-2-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 6
	Number of BUFGCE: 6
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 5 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
Pre-CRP Checker took 0 secs

**************************************
Clock Nets/Source Overview (CRP Input)
**************************************
Clock 1: clk_gen_i0/clk_core_i0/inst/clk_out1
	Clock source type: BUFGCE
	Clock source region: X0Y5
	initial rect ((0, 0), (3, 5))

Clock 2: clk_gen_i0/clk_core_i0/inst/clk_out2
	Clock source type: BUFGCE
	Clock source region: X0Y5
	Clock regions with locked loads: X0Y5 X2Y1 X2Y5 X3Y5 
	initial rect ((0, 0), (3, 5))

Clock 3: dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
	Clock source type: BUFGCE
	Clock source region: X2Y4
	initial rect ((2, 2), (3, 4))

Clock 4: clk_gen_i0/clk_samp
	Clock source type: BUFGCE
	Clock source region: X2Y1
	initial rect ((2, 1), (2, 4))

Clock 5: clk_gen_i0/clk_core_i0/inst/clk_in1_clk_core
	Clock source type: BUFGCE
	Clock source region: X0Y5
	Clock regions with locked loads: X0Y5 
	initial rect ((0, 5), (0, 5))

Clock 6: clk_gen_i0/clk_core_i0/inst/clkfbout_buf_clk_core
	Clock source type: BUFGCE
	Clock source region: X0Y5
	Clock regions with locked loads: X0Y5 
	initial rect ((0, 5), (0, 5))



*****************************
Clocks With User Constraints:
*****************************
No clocks with user constraints found


