-------------------------------------
| Tool Version : Vivado v.2025.2
| Date         : Wed Dec 17 16:44:43 2025
| Host         : amd-VirtualBox
| Design       : checkpoint_wave_gen
| Device       : xcku040-ffva1156-2-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 4
	Number of BUFGCE: 4
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 4 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
Pre-CRP Checker took 0 secs

**************************************
Clock Nets/Source Overview (CRP Input)
**************************************
Clock 1: clk_gen_i0/clk_core_i0/inst/clk_out1
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 1), (2, 1))

Clock 2: clk_gen_i0/clk_core_i0/inst/clk_out2
	Clock source type: BUFGCE
	Clock source region: X0Y1
	Clock regions with locked loads: X0Y1 X0Y4 X2Y0 X2Y1 
	initial rect ((0, 0), (2, 4))

Clock 3: clk_gen_i0/BUFGCE_clk_samp_i0_0
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 1), (2, 1))

Clock 4: clk_gen_i0/clk_core_i0/inst/clk_in1_clk_core
	Clock source type: BUFGCE
	Clock source region: X0Y1
	Clock regions with locked loads: X0Y1 
	initial rect ((0, 1), (0, 1))



*****************************
Clocks With User Constraints:
*****************************
The following 1 instances have the CLOCK_REGION property:
	clk_gen_i0/BUFGCE_clk_samp_i0 is at: X0Y1



