xpm_cdc.sv,systemverilog,xpm,../../../../opt/amd/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
xpm_memory.sv,systemverilog,xpm,../../../../opt/amd/2025.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
xpm_VCOMP.vhd,vhdl,xpm,../../../../opt/amd/2025.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_14,../../../../../../../../../IP_Flow/demo/KCU105/verilog/wave_gen.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_14,../../../../../../../../../IP_Flow/demo/KCU105/verilog/wave_gen.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_14,../../../../../../../../../IP_Flow/demo/KCU105/verilog/wave_gen.ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
char_fifo.v,verilog,xil_defaultlib,/home/amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/ip/char_fifo/sim/char_fifo.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
clk_core_clk_wiz.v,verilog,xil_defaultlib,/home/amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/ip/clk_core/clk_core_clk_wiz.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
clk_core.v,verilog,xil_defaultlib,/home/amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/ip/clk_core/clk_core.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
clk_div.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/clk_div.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
clk_gen.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/clk_gen.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
clkx_bus.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/clkx_bus.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
cmd_parse.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/cmd_parse.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
dac_spi.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/dac_spi.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
debouncer.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/debouncer.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
lb_ctl.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/lb_ctl.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
meta_harden.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/meta_harden.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
out_ddr_flop.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/out_ddr_flop.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
reset_bridge.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/reset_bridge.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
resp_gen.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/resp_gen.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
rst_gen.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/rst_gen.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
samp_gen.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/samp_gen.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
samp_ram.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/samp_ram.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
to_bcd.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/to_bcd.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
uart_baud_gen.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/uart_baud_gen.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
uart_rx.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/uart_rx.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
uart_rx_ctl.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/uart_rx_ctl.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
uart_tx.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/uart_tx.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
uart_tx_ctl.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/uart_tx_ctl.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
wave_gen.v,verilog,xil_defaultlib,../../../amd/training/F1 Demos/F1 Demos/IP_Flow/demo/KCU105/verilog/wave_gen.srcs/sources_1/imports/verilog/wave_gen.v,incdir="../../../../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"incdir="../../../wave_gen.srcs/sources_1/imports/verilog"incdir="../../../wave_gen.srcs/sources_1/ip/clk_core"
glbl.v,Verilog,xil_defaultlib,glbl.v
