-------------------------------------
| Tool Version : Vivado v.2024.2
| Date         : Sat Nov 23 12:22:28 2024
| Host         : amd-VirtualBox
| Design       : design_1
| Device       : xcku040-ffva1156-2-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 4
	Number of BUFGCE: 4
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 4 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
Pre-CRP Checker took 0 secs

********************************
Clock Net Route Info (CRP Input)
********************************
Clock 1: clk_gen_i0/clk_core_i0/inst/clk_out1
	Clock source type: BUFGCE
	Clock source region: X2Y2
	initial rect ((2, 0), (2, 2))

Clock 2: clk_gen_i0/clk_core_i0/inst/clk_out2
	Clock source type: BUFGCE
	Clock source region: X2Y2
	Clock regions with locked loads: X0Y4 X2Y0 
	initial rect ((0, 0), (2, 4))

Clock 3: clk_gen_i0/clk_samp
	Clock source type: BUFGCE
	Clock source region: X0Y4
	initial rect ((0, 0), (2, 4))

Clock 4: clk_gen_i0/clk_core_i0/inst/clkfbout_buf_clk_core
	Clock source type: BUFGCE
	Clock source region: X2Y2
	Clock regions with locked loads: X2Y2 
	initial rect ((2, 2), (2, 2))



*****************
User Constraints:
*****************
No user constraints found


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