-------------------------------------
| Tool Version : Vivado v.2025.2
| Date         : Tue Mar 10 14:52:32 2026
| Host         : amd-VirtualBox
| Design       : design_1
| Device       : xcvu9p-flga2104-2L-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 1
	Number of BUFGCE: 1
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
Pre-CRP Checker took 0 secs

**************************************
Clock Nets/Source Overview (CRP Input)
**************************************
Clock 1: mmcm_out_clk
	Clock source type: BUFGCE
	Clock source region: X4Y8
	initial rect ((4, 7), (5, 9))



*****************************
Clocks With User Constraints:
*****************************
No clocks with user constraints found


