2025.2:
 * Version 4.1 (Rev. 13)
 * No changes

2025.1.1:
 * Version 4.1 (Rev. 13)
 * No changes

2025.1:
 * Version 4.1 (Rev. 13)
 * General: Updated IP Catalog taxonomy structure. This change has no impact to the IP.

2024.2.2:
 * Version 4.1 (Rev. 12)
 * No changes

2024.2.1:
 * Version 4.1 (Rev. 12)
 * General: Spartan Ultrascale plus family support addition

2024.2:
 * Version 4.1 (Rev. 11)
 * General: Re-Packaged to improve internal automation, no functional changes

2024.1.2:
 * Version 4.1 (Rev. 10)
 * No changes

2024.1.1:
 * Version 4.1 (Rev. 10)
 * No changes

2024.1:
 * Version 4.1 (Rev. 10)
 * General: IP packaging adjustments to address warnings from IP Packager integrity check

2023.2.2:
 * Version 4.1 (Rev. 9)
 * No changes

2023.2.1:
 * Version 4.1 (Rev. 9)
 * No changes

2023.2:
 * Version 4.1 (Rev. 9)
 * General: Rebrand to AMD copyright information

2023.1.2:
 * Version 4.1 (Rev. 8)
 * No changes

2023.1.1:
 * Version 4.1 (Rev. 8)
 * No changes

2023.1:
 * Version 4.1 (Rev. 8)
 * General: Hamming ECC-64 checkbit handler internal bits reversed
 * General: Memory Range calculation algorithm changed, no functional change

2022.2.2:
 * Version 4.1 (Rev. 7)
 * No changes

2022.2.1:
 * Version 4.1 (Rev. 7)
 * No changes

2022.2:
 * Version 4.1 (Rev. 7)
 * General: Using physical address segment to fix IPI propagation issues

2022.1.2:
 * Version 4.1 (Rev. 6)
 * No changes

2022.1.1:
 * Version 4.1 (Rev. 6)
 * No changes

2022.1:
 * Version 4.1 (Rev. 6)
 * No changes

2021.2.2:
 * Version 4.1 (Rev. 6)
 * No changes

2021.2.1:
 * Version 4.1 (Rev. 6)
 * No changes

2021.2:
 * Version 4.1 (Rev. 6)
 * General: ECC_TYPE parameter default value change

2021.1.1:
 * Version 4.1 (Rev. 5)
 * No changes

2021.1:
 * Version 4.1 (Rev. 5)
 * General: removed Xilinx Internal markings from TLM model sources

2020.3:
 * Version 4.1 (Rev. 4)
 * No changes

2020.2.2:
 * Version 4.1 (Rev. 4)
 * No changes

2020.2.1:
 * Version 4.1 (Rev. 4)
 * No changes

2020.2:
 * Version 4.1 (Rev. 4)
 * General: Vivado Block Design warnings on READ_LATENCY and RD_CMD_OPT parameters fixed. No functional change.

2020.1.1:
 * Version 4.1 (Rev. 3)
 * No changes

2020.1:
 * Version 4.1 (Rev. 3)
 * Feature Enhancement: SystemC models added

2019.2.2:
 * Version 4.1 (Rev. 2)
 * No changes

2019.2.1:
 * Version 4.1 (Rev. 2)
 * No changes

2019.2:
 * Version 4.1 (Rev. 2)
 * Bug Fix: BRAM address in full_axi module is not driving properly for dual port ECC configurations. This issue is fixed.

2019.1.3:
 * Version 4.1 (Rev. 1)
 * No changes

2019.1.2:
 * Version 4.1 (Rev. 1)
 * No changes

2019.1.1:
 * Version 4.1 (Rev. 1)
 * No changes

2019.1:
 * Version 4.1 (Rev. 1)
 * Feature Enhancement: Read Latency Support added
 * Feature Enhancement: ECC bits organization logic retained for all devices
 * Feature Enhancement: Read Command Optimization Parameter added to Optimize the Read Command latency
 * Other: BMG support removed and corresponding parameter to select between BMG and XPM also removed

2018.3.1:
 * Version 4.1
 * No changes

2018.3:
 * Version 4.1
 * General: Range calculation added when in multiple master segments

2018.2:
 * Version 4.0 (Rev. 14)
 * No changes

2018.1:
 * Version 4.0 (Rev. 14)
 * Bug Fix: Removed the address width constraint for wrap transactions as part of reducing synthesis warnings

2017.4:
 * Version 4.0 (Rev. 13)
 * General: Modified Memory_Depth to support 64bit addressing

2017.3:
 * Version 4.0 (Rev. 12)
 * General: Migrated to use XPM Memory in place of Block Memory Generator

2017.2:
 * Version 4.0 (Rev. 11)
 * No changes

2017.1:
 * Version 4.0 (Rev. 11)
 * General: Internal device family change, no functional changes
 * Revision change in one or more subcores

2016.4:
 * Version 4.0 (Rev. 10)
 * Revision change in one or more subcores

2016.3:
 * Version 4.0 (Rev. 9)
 * General: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
 * Revision change in one or more subcores

2016.2:
 * Version 4.0 (Rev. 8)
 * Revision change in one or more subcores

2016.1:
 * Version 4.0 (Rev. 7)
 * Minimum depth allowed is changed to 512 for IPI designs, in case depth is less than 512 it will be reset to 512
 * Simulation file set updated to support mixed language
 * Revision change in one or more subcores

2015.4.2:
 * Version 4.0 (Rev. 6)
 * No changes

2015.4.1:
 * Version 4.0 (Rev. 6)
 * No changes

2015.4:
 * Version 4.0 (Rev. 6)
 * Revision change in one or more subcores

2015.3:
 * Version 4.0 (Rev. 5)
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Address range supported is increased to 2G in IP Integrator

2015.2.1:
 * Version 4.0 (Rev. 4)
 * No changes

2015.2:
 * Version 4.0 (Rev. 4)
 * No changes

2015.1:
 * Version 4.0 (Rev. 4)
 * Increased the supporting memory depth to 256k
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 4.0 (Rev. 3)
 * No changes

2014.4:
 * Version 4.0 (Rev. 3)
 * Internal device family change, no functional changes
 * Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
 * Reduced the IP INFO messages sent to the tool while creation of the IP

2014.3:
 * Version 4.0 (Rev. 2)
 * Re-Packaged to improve internal automation, no functional changes

2014.2:
 * Version 4.0 (Rev. 1)
 * Constrained the range for the variable "size_plus_lsb" between 1 to 256 in narrow.vhd file to improve the timing
 * Re-Packaged to improve internal automation, no functional changes

2014.1:
 * Version 4.0
 * The ID Ports s_axi_arid,s_axi_awid,s_axi_bid,s_axi_rid shall be generated only when the ID width is greater than or equal to '1'. when upgrading the previously released core, the ID ports mentioned above will not be generated unless the ID width is greater than or equal to '1'
 * Internal device family name change, no functional changes

2013.4:
 * Version 3.0 (Rev. 3)
 * Added support for Hamming Code
 * Added support for Ultrascale devices

2013.3:
 * Version 3.0 (Rev. 2)
 * Updated the port names to lower case
 * Added example design
 * Reduced warnings in synthesis and simulation
 * Improved GUI speed and responsivness, no functional changes
 * Added Support for Cadence IES and Synopsys VCS simulators
 * Changed BRAM Interface DIN and DOUT to match bus interface directions.

2013.2:
 * Version 3.0 (Rev. 1)
 * Updated Address width to 32 for ECC configurations
 * Updated to support ECC in IPI Mode
 * Added support for Future Devices

2013.1:
 * Version 3.0
 * Native Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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