axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi_vip_if.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
clk_vip_if.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
rst_vip_if.sv,systemverilog,xilinx_vip,../xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_cdc.sv,systemverilog,xpm,../ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_fifo.sv,systemverilog,xpm,../ip/xpm/xpm_fifo/hdl/xpm_fifo.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_memory.sv,systemverilog,xpm,../ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_VCOMP.vhd,vhdl,xpm,../ip/xpm/xpm_VCOMP.vhd,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nmu_mm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nmu_mm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nsu_mm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nsu_mm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nmu_strm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nmu_strm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nsu_strm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nsu_strm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi_bram_ctrl_v4_1_rfs.vhd,vhdl,axi_bram_ctrl_v4_1_13,../../../ipstatic/hdl/axi_bram_ctrl_v4_1_rfs.vhd,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi_bram_ctrl_pl_slave_from_ps.vhd,vhdl,xil_defaultlib,../../../../mod_noc.gen/sources_1/ip/axi_bram_ctrl_pl_slave_from_ps/sim/axi_bram_ctrl_pl_slave_from_ps.vhd,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
glbl.v,Verilog,xil_defaultlib,glbl.v
