xpm_nmu_mm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nmu_mm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nsu_mm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nsu_mm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nmu_strm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nmu_strm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
xpm_nsu_strm.sv,systemverilog,xpm_noc,../ip/xpm/xpm_noc/hdl/xpm_nsu_strm.sv,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
axi_bram_ctrl_pl_slave_from_ps.vhd,vhdl,xil_defaultlib,../../../../mod_noc.gen/sources_1/ip/axi_bram_ctrl_pl_slave_from_ps/sim/axi_bram_ctrl_pl_slave_from_ps.vhd,incdir="../../../../../../../../../opt/amd/2025.2/data/rsb/busdef"
glbl.v,Verilog,xil_defaultlib,glbl.v
