-------------------------------------
| Tool Version : Vivado v.2026.1
| Date         : Wed Sep 23 15:33:03 2026
| Host         : amd-VirtualBox
| Design       : design_1
| Device       : xcvu5p-flva2104-2-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 5
	Number of BUFGCE: 5
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 0
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 3 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
Pre-CRP Checker took 0 secs

**************************************
Clock Nets/Source Overview (CRP Input)
**************************************
Clock 1: slr1_captured[63]_i_1_n_0_BUFG
	Clock source type: BUFGCE
	Clock source region: X4Y0
	initial rect X0Y0:X5Y5

Clock 2: mmcm1_inst/inst/clk_a
	Clock source type: BUFGCE
	Clock source region: X4Y3
	initial rect X0Y0:X5Y4

Clock 3: mmcm1_inst/inst/clk_combo
	Clock source type: BUFGCE
	Clock source region: X4Y3
	initial rect X2Y3:X4Y6

Clock 4: mmcm1_inst/inst/clk_slr
	Clock source type: BUFGCE
	Clock source region: X4Y3
	initial rect X0Y3:X5Y6

Clock 5: mmcm2_inst/inst/clk_b
	Clock source type: BUFGCE
	Clock source region: X4Y2
	initial rect X2Y2:X4Y2



*****************************
Clocks With User Constraints:
*****************************
No clocks with user constraints found




