Design Guidance Report

CopyrightCopyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Tool Versionxcd v.2025.1 (lin64) Build 0
DateMon Aug 25 14:07:47 2025
HostCustEd-VM running 64-bit Ubuntu 22.04.5 LTS
CommandAIE Compilation

Table of Contents
1 REPORT SUMMARY
2 VIOLATION DETAILS

1 REPORT SUMMARY

Violations found: 4
Rule Specs Violated: 2

2 VIOLATION DETAILS

Items that may require attention
Id Name Severity Impact Full Name Categories Details Resolution
2 AIE-MEM-01 ADVISORY Memory Management Memory.24_1 Alignment of global array __const._Z11cos_sin_magiiPiS_S_.rotation_sin_lut is 4 bytes; automatically aligning it to 16 bytes. Align global arrays to 16 byte boundary. Refer to the chess user manual for details on specifying the alignment constraints.
4 AIE-PERF-01 ADVISORY AIE-PL Interface Performance The resolved frequency of PLIO "DataOut1" is 312.5 MHz and the data width is 32 bit. It is less than the maximum AIE stream throughput with 32-bit data width at 1250 MHz frequency. Either increase PLIO frequency or increase PLIO data width to achieve full AIE stream throughput. For more information, refer to UG1076
3 AIE-PERF-01 ADVISORY AIE-PL Interface Performance The resolved frequency of PLIO "DataIn1" is 312.5 MHz and the data width is 32 bit. It is less than the maximum AIE stream throughput with 32-bit data width at 1250 MHz frequency. Either increase PLIO frequency or increase PLIO data width to achieve full AIE stream throughput. For more information, refer to UG1076
1 AIE-MEM-01 ADVISORY Memory Management Memory.24_1 Alignment of global array __const._Z11cos_sin_magiiPiS_S_.rotation_cos_lut is 4 bytes; automatically aligning it to 16 bytes. Align global arrays to 16 byte boundary. Refer to the chess user manual for details on specifying the alignment constraints.