Items that may require attention
| Id |
Name |
Severity |
Impact |
Full Name |
Categories |
Details |
Resolution |
| 5 |
Kernel |
ADVISORY |
|
HLS Kernel Related |
Accelerator.mm2s.Kernel |
**** Loop Constraint Status: All loop constraints were satisfied.
|
Vitis HLS User Guide (UG1399) |
| 3 |
Throughput |
ADVISORY |
|
HLS Throughput Related |
Accelerator.mm2s.Throughput |
Pipelining result : Target II = 1, Final II = 1, Depth = 77, loop 'VITIS_LOOP_37_1'
|
Vitis HLS User Guide (UG1399) |
| 6 |
Kernel |
ADVISORY |
|
HLS Kernel Related |
Accelerator.mm2s.Kernel |
**** Estimated Fmax: 142.05 MHz
|
Vitis HLS User Guide (UG1399) |
| 1 |
Interface |
ADVISORY |
|
HLS Interface Related |
Accelerator.mm2s.Interface |
Multiple burst reads of variable length and bit width 32 in loop 'VITIS_LOOP_37_1'(mm2s.cpp) has been inferred on bundle 'gmem'. These burst requests might be further partitioned into multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings. (mm2s.cpp)
|
Vitis HLS User Guide (UG1399) |
| 4 |
Interface |
ADVISORY |
|
HLS Interface Related |
Accelerator.mm2s.Interface |
Design has inferred MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
|
Vitis HLS User Guide (UG1399) |
| 2 |
Kernel |
ADVISORY |
|
HLS Kernel Related |
Accelerator.mm2s.Kernel |
Unable to schedule the whole 74 cycles bus request operation ('empty_20', mm2s.cpp) on port 'gmem' (mm2s.cpp) within the first cycle (II = 1). Simulation mismatch may occur if the input data is modified before this operation completes.
|
Vitis HLS User Guide (UG1399) |