Design Guidance Report

CopyrightCopyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Tool Versionxcd v.2025.1 (lin64) Build 0
DateMon Aug 25 15:08:50 2025
HostCustEd-VM running 64-bit Ubuntu 22.04.5 LTS
Command/opt/amd/2025.1/Vitis/bin/unwrapped/lnx64.o/v++ -c --mode hls --config /home/amd/training/system_simulation/lab/sys_project/s2mm/s2mm_config.cfg --work_dir s2mm

Table of Contents
1 REPORT SUMMARY
2 VIOLATION DETAILS

1 REPORT SUMMARY

Violations found: 5
Rule Specs Violated: 3

2 VIOLATION DETAILS

Items that may require attention
Id Name Severity Impact Full Name Categories Details Resolution
4 Kernel ADVISORY HLS Kernel Related Accelerator.s2mm.Kernel **** Loop Constraint Status: All loop constraints were satisfied. Vitis HLS User Guide (UG1399)
1 Interface ADVISORY HLS Interface Related Accelerator.s2mm.Interface Multiple burst writes of variable length and bit width 32 in loop 'VITIS_LOOP_37_1'(s2mm.cpp) has been inferred on bundle 'gmem'. These burst requests might be further partitioned into multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings. (s2mm.cpp) Vitis HLS User Guide (UG1399)
5 Kernel ADVISORY HLS Kernel Related Accelerator.s2mm.Kernel **** Estimated Fmax: 142.05 MHz Vitis HLS User Guide (UG1399)
2 Throughput ADVISORY HLS Throughput Related Accelerator.s2mm.Throughput Pipelining result : Target II = 1, Final II = 1, Depth = 77, loop 'VITIS_LOOP_37_1' Vitis HLS User Guide (UG1399)
3 Interface ADVISORY HLS Interface Related Accelerator.s2mm.Interface Design has inferred MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information. Vitis HLS User Guide (UG1399)