====================================================================
Version:    xcd v2025.1 (64-bit)
Copyright:  Copyright 1986-2025 Xilinx, Inc. All Rights Reserved.
Created:    Mon Aug 25 16:01:21 2025
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1. Kernel and compute unit information
======================================

Compute Unit: ai_engine_0
Kernel: ai_engine
Clock Pins: aclk1, aclk0
Reset Pin: aresetn0

Compute Unit: mm2s
Kernel: mm2s
Base Address: 0xa4000000
Clock Pin: ap_clk
Reset Pin: ap_rst_n

Compute Unit: s2mm
Kernel: s2mm
Base Address: 0xa4010000
Clock Pin: ap_clk
Reset Pin: ap_rst_n

2. Interface Connections
========================

Compute Unit to Compute Unit
----------------------------
Source Pin: mm2s/s
Destination Pin: ai_engine_0/S00_AXIS

Source Pin: ai_engine_0/M00_AXIS
Destination Pin: s2mm/s

IP to Compute Unit
------------------
Source Pin: axi_smc_vip_hier/M06_AXI
Destination Pin: mm2s/s_axi_control

Source Pin: System_DPA/MON_S_AXI
Destination Pin: mm2s/s_axi_control

Source Pin: System_DPA/MON_AXIS1
Destination Pin: s2mm/s

Source Pin: axi_smc_vip_hier/M07_AXI
Destination Pin: s2mm/s_axi_control

Source Pin: System_DPA/MON_S_AXI1
Destination Pin: s2mm/s_axi_control

Source Pin: cips_noc/M00_AXI
Destination Pin: ai_engine_0/S00_AXI

Source Pin: System_DPA/MON_AXIS
Destination Pin: ai_engine_0/S00_AXIS

Compute Unit to IP
------------------
Source Pin: mm2s/m_axi_gmem
Destination Pin: noc_ddr4/S00_AXI

Source Pin: mm2s/m_axi_gmem
Destination Pin: System_DPA/MON_M_AXI

Source Pin: mm2s/s
Destination Pin: System_DPA/MON_AXIS

Source Pin: s2mm/m_axi_gmem
Destination Pin: noc_ddr4/S01_AXI

Source Pin: s2mm/m_axi_gmem
Destination Pin: System_DPA/MON_M_AXI1

Source Pin: ai_engine_0/M00_AXIS
Destination Pin: System_DPA/MON_AXIS1

3. Clock Connections
====================

Compute Unit: mm2s
Clock ID: 2
Platform Clock Frequency: 312.50 MHz
Requested Kernel Clock Frequency: 312.50 MHz
Source Pin: clk_wizard_0/clk_out1_o2
Destination Pin: mm2s/ap_clk

Compute Unit: s2mm
Clock ID: 2
Platform Clock Frequency: 312.50 MHz
Requested Kernel Clock Frequency: 312.50 MHz
Source Pin: clk_wizard_0/clk_out1_o2
Destination Pin: s2mm/ap_clk

Compute Unit: ai_engine_0
Clock ID: 2
Platform Clock Frequency: 312.50 MHz
Requested Kernel Clock Frequency: 312.50 MHz
Source Pin: clk_wizard_0/clk_out1_o2
Destination Pin: ai_engine_0/aclk0

Clock Instance: clk_wizard_0
Source Pin: CIPS_0/pl0_ref_clk
Destination Pin: clk_wizard_0/clk_in1

4. Reset Connections
====================

Compute Unit: mm2s
Source Pin: proc_sys_reset_1/peripheral_aresetn
Destination Pin: mm2s/ap_rst_n
Associated Clock Pin: mm2s/ap_clk

Compute Unit: s2mm
Source Pin: proc_sys_reset_1/peripheral_aresetn
Destination Pin: s2mm/ap_rst_n
Associated Clock Pin: s2mm/ap_clk

Compute Unit: ai_engine_0
Source Pin: proc_sys_reset_1/peripheral_aresetn
Destination Pin: ai_engine_0/aresetn0
Associated Clock Pin: ai_engine_0/aclk0

5. Clock Summary
================

AIE
+-------------+-----------+----------+---------------+------------+---------------+------------+
| Instance    | Kernel    | PLIO     | Annotated Arg | Clock Port | Compile (MHz) | Link (MHz) |
+-------------+-----------+----------+---------------+------------+---------------+------------+
| ai_engine_0 | ai_engine | M00_AXIS | DataOut1      | aclk0      | 312.50        | 312.50     |
| ai_engine_0 | ai_engine | S00_AXIS | DataIn1       | aclk0      | 312.50        | 312.50     |
+-------------+-----------+----------+---------------+------------+---------------+------------+

PL
+----------+--------+------------+---------------+------------+
| Instance | Kernel | Clock Port | Compile (MHz) | Link (MHz) |
+----------+--------+------------+---------------+------------+
| mm2s     | mm2s   | ap_clk     | 125.00        | 312.50     |
| s2mm     | s2mm   | ap_clk     | 125.00        | 312.50     |
+----------+--------+------------+---------------+------------+

