//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
//Date        : Tue Nov 18 15:59:31 2025
//Host        : xhdshabbirk50x running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
//Command     : generate_target scu35_io_design.bd
//Design      : scu35_io_design
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module microblaze_riscv_0_local_memory_imp_WXRDSO
   (DLMB_abus,
    DLMB_addrstrobe,
    DLMB_be,
    DLMB_ce,
    DLMB_readdbus,
    DLMB_readstrobe,
    DLMB_ready,
    DLMB_ue,
    DLMB_wait,
    DLMB_writedbus,
    DLMB_writestrobe,
    ILMB_abus,
    ILMB_addrstrobe,
    ILMB_ce,
    ILMB_readdbus,
    ILMB_readstrobe,
    ILMB_ready,
    ILMB_ue,
    ILMB_wait,
    LMB_Clk,
    SYS_Rst);
  input [0:31]DLMB_abus;
  input DLMB_addrstrobe;
  input [0:3]DLMB_be;
  output DLMB_ce;
  output [0:31]DLMB_readdbus;
  input DLMB_readstrobe;
  output DLMB_ready;
  output DLMB_ue;
  output DLMB_wait;
  input [0:31]DLMB_writedbus;
  input DLMB_writestrobe;
  input [0:31]ILMB_abus;
  input ILMB_addrstrobe;
  output ILMB_ce;
  output [0:31]ILMB_readdbus;
  input ILMB_readstrobe;
  output ILMB_ready;
  output ILMB_ue;
  output ILMB_wait;
  input LMB_Clk;
  input SYS_Rst;

  wire [0:31]DLMB_abus;
  wire DLMB_addrstrobe;
  wire [0:3]DLMB_be;
  wire DLMB_ce;
  wire [0:31]DLMB_readdbus;
  wire DLMB_readstrobe;
  wire DLMB_ready;
  wire DLMB_ue;
  wire DLMB_wait;
  wire [0:31]DLMB_writedbus;
  wire DLMB_writestrobe;
  wire [0:31]ILMB_abus;
  wire ILMB_addrstrobe;
  wire ILMB_ce;
  wire [0:31]ILMB_readdbus;
  wire ILMB_readstrobe;
  wire ILMB_ready;
  wire ILMB_ue;
  wire ILMB_wait;
  wire LMB_Clk;
  wire SYS_Rst;
  wire [0:31]microblaze_riscv_0_dlmb_bus_ABUS;
  wire microblaze_riscv_0_dlmb_bus_ADDRSTROBE;
  wire [0:3]microblaze_riscv_0_dlmb_bus_BE;
  wire microblaze_riscv_0_dlmb_bus_CE;
  wire [0:31]microblaze_riscv_0_dlmb_bus_READDBUS;
  wire microblaze_riscv_0_dlmb_bus_READSTROBE;
  wire microblaze_riscv_0_dlmb_bus_READY;
  wire microblaze_riscv_0_dlmb_bus_UE;
  wire microblaze_riscv_0_dlmb_bus_WAIT;
  wire [0:31]microblaze_riscv_0_dlmb_bus_WRITEDBUS;
  wire microblaze_riscv_0_dlmb_bus_WRITESTROBE;
  wire [0:31]microblaze_riscv_0_dlmb_cntlr_ADDR;
  wire microblaze_riscv_0_dlmb_cntlr_CLK;
  wire [0:31]microblaze_riscv_0_dlmb_cntlr_DIN;
  wire [31:0]microblaze_riscv_0_dlmb_cntlr_DOUT;
  wire microblaze_riscv_0_dlmb_cntlr_EN;
  wire microblaze_riscv_0_dlmb_cntlr_RST;
  wire [0:3]microblaze_riscv_0_dlmb_cntlr_WE;
  wire [0:31]microblaze_riscv_0_ilmb_bus_ABUS;
  wire microblaze_riscv_0_ilmb_bus_ADDRSTROBE;
  wire [0:3]microblaze_riscv_0_ilmb_bus_BE;
  wire microblaze_riscv_0_ilmb_bus_CE;
  wire [0:31]microblaze_riscv_0_ilmb_bus_READDBUS;
  wire microblaze_riscv_0_ilmb_bus_READSTROBE;
  wire microblaze_riscv_0_ilmb_bus_READY;
  wire microblaze_riscv_0_ilmb_bus_UE;
  wire microblaze_riscv_0_ilmb_bus_WAIT;
  wire [0:31]microblaze_riscv_0_ilmb_bus_WRITEDBUS;
  wire microblaze_riscv_0_ilmb_bus_WRITESTROBE;
  wire [0:31]microblaze_riscv_0_ilmb_cntlr_ADDR;
  wire microblaze_riscv_0_ilmb_cntlr_CLK;
  wire [0:31]microblaze_riscv_0_ilmb_cntlr_DIN;
  wire [31:0]microblaze_riscv_0_ilmb_cntlr_DOUT;
  wire microblaze_riscv_0_ilmb_cntlr_EN;
  wire microblaze_riscv_0_ilmb_cntlr_RST;
  wire [0:3]microblaze_riscv_0_ilmb_cntlr_WE;

  (* BMM_INFO_ADDRESS_SPACE = "byte  0x00000000 32 > scu35_io_design microblaze_riscv_0_local_memory/lmb_bram" *) 
  (* KEEP_HIERARCHY = "YES" *) 
  scu35_io_design_dlmb_bram_if_cntlr_0 dlmb_bram_if_cntlr
       (.BRAM_Addr_A(microblaze_riscv_0_dlmb_cntlr_ADDR),
        .BRAM_Clk_A(microblaze_riscv_0_dlmb_cntlr_CLK),
        .BRAM_Din_A({microblaze_riscv_0_dlmb_cntlr_DOUT[31],microblaze_riscv_0_dlmb_cntlr_DOUT[30],microblaze_riscv_0_dlmb_cntlr_DOUT[29],microblaze_riscv_0_dlmb_cntlr_DOUT[28],microblaze_riscv_0_dlmb_cntlr_DOUT[27],microblaze_riscv_0_dlmb_cntlr_DOUT[26],microblaze_riscv_0_dlmb_cntlr_DOUT[25],microblaze_riscv_0_dlmb_cntlr_DOUT[24],microblaze_riscv_0_dlmb_cntlr_DOUT[23],microblaze_riscv_0_dlmb_cntlr_DOUT[22],microblaze_riscv_0_dlmb_cntlr_DOUT[21],microblaze_riscv_0_dlmb_cntlr_DOUT[20],microblaze_riscv_0_dlmb_cntlr_DOUT[19],microblaze_riscv_0_dlmb_cntlr_DOUT[18],microblaze_riscv_0_dlmb_cntlr_DOUT[17],microblaze_riscv_0_dlmb_cntlr_DOUT[16],microblaze_riscv_0_dlmb_cntlr_DOUT[15],microblaze_riscv_0_dlmb_cntlr_DOUT[14],microblaze_riscv_0_dlmb_cntlr_DOUT[13],microblaze_riscv_0_dlmb_cntlr_DOUT[12],microblaze_riscv_0_dlmb_cntlr_DOUT[11],microblaze_riscv_0_dlmb_cntlr_DOUT[10],microblaze_riscv_0_dlmb_cntlr_DOUT[9],microblaze_riscv_0_dlmb_cntlr_DOUT[8],microblaze_riscv_0_dlmb_cntlr_DOUT[7],microblaze_riscv_0_dlmb_cntlr_DOUT[6],microblaze_riscv_0_dlmb_cntlr_DOUT[5],microblaze_riscv_0_dlmb_cntlr_DOUT[4],microblaze_riscv_0_dlmb_cntlr_DOUT[3],microblaze_riscv_0_dlmb_cntlr_DOUT[2],microblaze_riscv_0_dlmb_cntlr_DOUT[1],microblaze_riscv_0_dlmb_cntlr_DOUT[0]}),
        .BRAM_Dout_A(microblaze_riscv_0_dlmb_cntlr_DIN),
        .BRAM_EN_A(microblaze_riscv_0_dlmb_cntlr_EN),
        .BRAM_Rst_A(microblaze_riscv_0_dlmb_cntlr_RST),
        .BRAM_WEN_A(microblaze_riscv_0_dlmb_cntlr_WE),
        .LMB_ABus(microblaze_riscv_0_dlmb_bus_ABUS),
        .LMB_AddrStrobe(microblaze_riscv_0_dlmb_bus_ADDRSTROBE),
        .LMB_BE(microblaze_riscv_0_dlmb_bus_BE),
        .LMB_Clk(LMB_Clk),
        .LMB_ReadStrobe(microblaze_riscv_0_dlmb_bus_READSTROBE),
        .LMB_Rst(SYS_Rst),
        .LMB_WriteDBus(microblaze_riscv_0_dlmb_bus_WRITEDBUS),
        .LMB_WriteStrobe(microblaze_riscv_0_dlmb_bus_WRITESTROBE),
        .Sl_CE(microblaze_riscv_0_dlmb_bus_CE),
        .Sl_DBus(microblaze_riscv_0_dlmb_bus_READDBUS),
        .Sl_Ready(microblaze_riscv_0_dlmb_bus_READY),
        .Sl_UE(microblaze_riscv_0_dlmb_bus_UE),
        .Sl_Wait(microblaze_riscv_0_dlmb_bus_WAIT));
  scu35_io_design_dlmb_v10_0 dlmb_v10
       (.LMB_ABus(microblaze_riscv_0_dlmb_bus_ABUS),
        .LMB_AddrStrobe(microblaze_riscv_0_dlmb_bus_ADDRSTROBE),
        .LMB_BE(microblaze_riscv_0_dlmb_bus_BE),
        .LMB_CE(DLMB_ce),
        .LMB_Clk(LMB_Clk),
        .LMB_ReadDBus(DLMB_readdbus),
        .LMB_ReadStrobe(microblaze_riscv_0_dlmb_bus_READSTROBE),
        .LMB_Ready(DLMB_ready),
        .LMB_UE(DLMB_ue),
        .LMB_Wait(DLMB_wait),
        .LMB_WriteDBus(microblaze_riscv_0_dlmb_bus_WRITEDBUS),
        .LMB_WriteStrobe(microblaze_riscv_0_dlmb_bus_WRITESTROBE),
        .M_ABus(DLMB_abus),
        .M_AddrStrobe(DLMB_addrstrobe),
        .M_BE(DLMB_be),
        .M_DBus(DLMB_writedbus),
        .M_ReadStrobe(DLMB_readstrobe),
        .M_WriteStrobe(DLMB_writestrobe),
        .SYS_Rst(SYS_Rst),
        .Sl_CE(microblaze_riscv_0_dlmb_bus_CE),
        .Sl_DBus(microblaze_riscv_0_dlmb_bus_READDBUS),
        .Sl_Ready(microblaze_riscv_0_dlmb_bus_READY),
        .Sl_UE(microblaze_riscv_0_dlmb_bus_UE),
        .Sl_Wait(microblaze_riscv_0_dlmb_bus_WAIT));
  scu35_io_design_ilmb_bram_if_cntlr_0 ilmb_bram_if_cntlr
       (.BRAM_Addr_A(microblaze_riscv_0_ilmb_cntlr_ADDR),
        .BRAM_Clk_A(microblaze_riscv_0_ilmb_cntlr_CLK),
        .BRAM_Din_A({microblaze_riscv_0_ilmb_cntlr_DOUT[31],microblaze_riscv_0_ilmb_cntlr_DOUT[30],microblaze_riscv_0_ilmb_cntlr_DOUT[29],microblaze_riscv_0_ilmb_cntlr_DOUT[28],microblaze_riscv_0_ilmb_cntlr_DOUT[27],microblaze_riscv_0_ilmb_cntlr_DOUT[26],microblaze_riscv_0_ilmb_cntlr_DOUT[25],microblaze_riscv_0_ilmb_cntlr_DOUT[24],microblaze_riscv_0_ilmb_cntlr_DOUT[23],microblaze_riscv_0_ilmb_cntlr_DOUT[22],microblaze_riscv_0_ilmb_cntlr_DOUT[21],microblaze_riscv_0_ilmb_cntlr_DOUT[20],microblaze_riscv_0_ilmb_cntlr_DOUT[19],microblaze_riscv_0_ilmb_cntlr_DOUT[18],microblaze_riscv_0_ilmb_cntlr_DOUT[17],microblaze_riscv_0_ilmb_cntlr_DOUT[16],microblaze_riscv_0_ilmb_cntlr_DOUT[15],microblaze_riscv_0_ilmb_cntlr_DOUT[14],microblaze_riscv_0_ilmb_cntlr_DOUT[13],microblaze_riscv_0_ilmb_cntlr_DOUT[12],microblaze_riscv_0_ilmb_cntlr_DOUT[11],microblaze_riscv_0_ilmb_cntlr_DOUT[10],microblaze_riscv_0_ilmb_cntlr_DOUT[9],microblaze_riscv_0_ilmb_cntlr_DOUT[8],microblaze_riscv_0_ilmb_cntlr_DOUT[7],microblaze_riscv_0_ilmb_cntlr_DOUT[6],microblaze_riscv_0_ilmb_cntlr_DOUT[5],microblaze_riscv_0_ilmb_cntlr_DOUT[4],microblaze_riscv_0_ilmb_cntlr_DOUT[3],microblaze_riscv_0_ilmb_cntlr_DOUT[2],microblaze_riscv_0_ilmb_cntlr_DOUT[1],microblaze_riscv_0_ilmb_cntlr_DOUT[0]}),
        .BRAM_Dout_A(microblaze_riscv_0_ilmb_cntlr_DIN),
        .BRAM_EN_A(microblaze_riscv_0_ilmb_cntlr_EN),
        .BRAM_Rst_A(microblaze_riscv_0_ilmb_cntlr_RST),
        .BRAM_WEN_A(microblaze_riscv_0_ilmb_cntlr_WE),
        .LMB_ABus(microblaze_riscv_0_ilmb_bus_ABUS),
        .LMB_AddrStrobe(microblaze_riscv_0_ilmb_bus_ADDRSTROBE),
        .LMB_BE(microblaze_riscv_0_ilmb_bus_BE),
        .LMB_Clk(LMB_Clk),
        .LMB_ReadStrobe(microblaze_riscv_0_ilmb_bus_READSTROBE),
        .LMB_Rst(SYS_Rst),
        .LMB_WriteDBus(microblaze_riscv_0_ilmb_bus_WRITEDBUS),
        .LMB_WriteStrobe(microblaze_riscv_0_ilmb_bus_WRITESTROBE),
        .Sl_CE(microblaze_riscv_0_ilmb_bus_CE),
        .Sl_DBus(microblaze_riscv_0_ilmb_bus_READDBUS),
        .Sl_Ready(microblaze_riscv_0_ilmb_bus_READY),
        .Sl_UE(microblaze_riscv_0_ilmb_bus_UE),
        .Sl_Wait(microblaze_riscv_0_ilmb_bus_WAIT));
  scu35_io_design_ilmb_v10_0 ilmb_v10
       (.LMB_ABus(microblaze_riscv_0_ilmb_bus_ABUS),
        .LMB_AddrStrobe(microblaze_riscv_0_ilmb_bus_ADDRSTROBE),
        .LMB_BE(microblaze_riscv_0_ilmb_bus_BE),
        .LMB_CE(ILMB_ce),
        .LMB_Clk(LMB_Clk),
        .LMB_ReadDBus(ILMB_readdbus),
        .LMB_ReadStrobe(microblaze_riscv_0_ilmb_bus_READSTROBE),
        .LMB_Ready(ILMB_ready),
        .LMB_UE(ILMB_ue),
        .LMB_Wait(ILMB_wait),
        .LMB_WriteDBus(microblaze_riscv_0_ilmb_bus_WRITEDBUS),
        .LMB_WriteStrobe(microblaze_riscv_0_ilmb_bus_WRITESTROBE),
        .M_ABus(ILMB_abus),
        .M_AddrStrobe(ILMB_addrstrobe),
        .M_BE({1'b0,1'b0,1'b0,1'b0}),
        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_ReadStrobe(ILMB_readstrobe),
        .M_WriteStrobe(1'b0),
        .SYS_Rst(SYS_Rst),
        .Sl_CE(microblaze_riscv_0_ilmb_bus_CE),
        .Sl_DBus(microblaze_riscv_0_ilmb_bus_READDBUS),
        .Sl_Ready(microblaze_riscv_0_ilmb_bus_READY),
        .Sl_UE(microblaze_riscv_0_ilmb_bus_UE),
        .Sl_Wait(microblaze_riscv_0_ilmb_bus_WAIT));
  scu35_io_design_lmb_bram_0 lmb_bram
       (.addra({microblaze_riscv_0_dlmb_cntlr_ADDR[0],microblaze_riscv_0_dlmb_cntlr_ADDR[1],microblaze_riscv_0_dlmb_cntlr_ADDR[2],microblaze_riscv_0_dlmb_cntlr_ADDR[3],microblaze_riscv_0_dlmb_cntlr_ADDR[4],microblaze_riscv_0_dlmb_cntlr_ADDR[5],microblaze_riscv_0_dlmb_cntlr_ADDR[6],microblaze_riscv_0_dlmb_cntlr_ADDR[7],microblaze_riscv_0_dlmb_cntlr_ADDR[8],microblaze_riscv_0_dlmb_cntlr_ADDR[9],microblaze_riscv_0_dlmb_cntlr_ADDR[10],microblaze_riscv_0_dlmb_cntlr_ADDR[11],microblaze_riscv_0_dlmb_cntlr_ADDR[12],microblaze_riscv_0_dlmb_cntlr_ADDR[13],microblaze_riscv_0_dlmb_cntlr_ADDR[14],microblaze_riscv_0_dlmb_cntlr_ADDR[15],microblaze_riscv_0_dlmb_cntlr_ADDR[16],microblaze_riscv_0_dlmb_cntlr_ADDR[17],microblaze_riscv_0_dlmb_cntlr_ADDR[18],microblaze_riscv_0_dlmb_cntlr_ADDR[19],microblaze_riscv_0_dlmb_cntlr_ADDR[20],microblaze_riscv_0_dlmb_cntlr_ADDR[21],microblaze_riscv_0_dlmb_cntlr_ADDR[22],microblaze_riscv_0_dlmb_cntlr_ADDR[23],microblaze_riscv_0_dlmb_cntlr_ADDR[24],microblaze_riscv_0_dlmb_cntlr_ADDR[25],microblaze_riscv_0_dlmb_cntlr_ADDR[26],microblaze_riscv_0_dlmb_cntlr_ADDR[27],microblaze_riscv_0_dlmb_cntlr_ADDR[28],microblaze_riscv_0_dlmb_cntlr_ADDR[29],microblaze_riscv_0_dlmb_cntlr_ADDR[30],microblaze_riscv_0_dlmb_cntlr_ADDR[31]}),
        .addrb({microblaze_riscv_0_ilmb_cntlr_ADDR[0],microblaze_riscv_0_ilmb_cntlr_ADDR[1],microblaze_riscv_0_ilmb_cntlr_ADDR[2],microblaze_riscv_0_ilmb_cntlr_ADDR[3],microblaze_riscv_0_ilmb_cntlr_ADDR[4],microblaze_riscv_0_ilmb_cntlr_ADDR[5],microblaze_riscv_0_ilmb_cntlr_ADDR[6],microblaze_riscv_0_ilmb_cntlr_ADDR[7],microblaze_riscv_0_ilmb_cntlr_ADDR[8],microblaze_riscv_0_ilmb_cntlr_ADDR[9],microblaze_riscv_0_ilmb_cntlr_ADDR[10],microblaze_riscv_0_ilmb_cntlr_ADDR[11],microblaze_riscv_0_ilmb_cntlr_ADDR[12],microblaze_riscv_0_ilmb_cntlr_ADDR[13],microblaze_riscv_0_ilmb_cntlr_ADDR[14],microblaze_riscv_0_ilmb_cntlr_ADDR[15],microblaze_riscv_0_ilmb_cntlr_ADDR[16],microblaze_riscv_0_ilmb_cntlr_ADDR[17],microblaze_riscv_0_ilmb_cntlr_ADDR[18],microblaze_riscv_0_ilmb_cntlr_ADDR[19],microblaze_riscv_0_ilmb_cntlr_ADDR[20],microblaze_riscv_0_ilmb_cntlr_ADDR[21],microblaze_riscv_0_ilmb_cntlr_ADDR[22],microblaze_riscv_0_ilmb_cntlr_ADDR[23],microblaze_riscv_0_ilmb_cntlr_ADDR[24],microblaze_riscv_0_ilmb_cntlr_ADDR[25],microblaze_riscv_0_ilmb_cntlr_ADDR[26],microblaze_riscv_0_ilmb_cntlr_ADDR[27],microblaze_riscv_0_ilmb_cntlr_ADDR[28],microblaze_riscv_0_ilmb_cntlr_ADDR[29],microblaze_riscv_0_ilmb_cntlr_ADDR[30],microblaze_riscv_0_ilmb_cntlr_ADDR[31]}),
        .clka(microblaze_riscv_0_dlmb_cntlr_CLK),
        .clkb(microblaze_riscv_0_ilmb_cntlr_CLK),
        .dina({microblaze_riscv_0_dlmb_cntlr_DIN[0],microblaze_riscv_0_dlmb_cntlr_DIN[1],microblaze_riscv_0_dlmb_cntlr_DIN[2],microblaze_riscv_0_dlmb_cntlr_DIN[3],microblaze_riscv_0_dlmb_cntlr_DIN[4],microblaze_riscv_0_dlmb_cntlr_DIN[5],microblaze_riscv_0_dlmb_cntlr_DIN[6],microblaze_riscv_0_dlmb_cntlr_DIN[7],microblaze_riscv_0_dlmb_cntlr_DIN[8],microblaze_riscv_0_dlmb_cntlr_DIN[9],microblaze_riscv_0_dlmb_cntlr_DIN[10],microblaze_riscv_0_dlmb_cntlr_DIN[11],microblaze_riscv_0_dlmb_cntlr_DIN[12],microblaze_riscv_0_dlmb_cntlr_DIN[13],microblaze_riscv_0_dlmb_cntlr_DIN[14],microblaze_riscv_0_dlmb_cntlr_DIN[15],microblaze_riscv_0_dlmb_cntlr_DIN[16],microblaze_riscv_0_dlmb_cntlr_DIN[17],microblaze_riscv_0_dlmb_cntlr_DIN[18],microblaze_riscv_0_dlmb_cntlr_DIN[19],microblaze_riscv_0_dlmb_cntlr_DIN[20],microblaze_riscv_0_dlmb_cntlr_DIN[21],microblaze_riscv_0_dlmb_cntlr_DIN[22],microblaze_riscv_0_dlmb_cntlr_DIN[23],microblaze_riscv_0_dlmb_cntlr_DIN[24],microblaze_riscv_0_dlmb_cntlr_DIN[25],microblaze_riscv_0_dlmb_cntlr_DIN[26],microblaze_riscv_0_dlmb_cntlr_DIN[27],microblaze_riscv_0_dlmb_cntlr_DIN[28],microblaze_riscv_0_dlmb_cntlr_DIN[29],microblaze_riscv_0_dlmb_cntlr_DIN[30],microblaze_riscv_0_dlmb_cntlr_DIN[31]}),
        .dinb({microblaze_riscv_0_ilmb_cntlr_DIN[0],microblaze_riscv_0_ilmb_cntlr_DIN[1],microblaze_riscv_0_ilmb_cntlr_DIN[2],microblaze_riscv_0_ilmb_cntlr_DIN[3],microblaze_riscv_0_ilmb_cntlr_DIN[4],microblaze_riscv_0_ilmb_cntlr_DIN[5],microblaze_riscv_0_ilmb_cntlr_DIN[6],microblaze_riscv_0_ilmb_cntlr_DIN[7],microblaze_riscv_0_ilmb_cntlr_DIN[8],microblaze_riscv_0_ilmb_cntlr_DIN[9],microblaze_riscv_0_ilmb_cntlr_DIN[10],microblaze_riscv_0_ilmb_cntlr_DIN[11],microblaze_riscv_0_ilmb_cntlr_DIN[12],microblaze_riscv_0_ilmb_cntlr_DIN[13],microblaze_riscv_0_ilmb_cntlr_DIN[14],microblaze_riscv_0_ilmb_cntlr_DIN[15],microblaze_riscv_0_ilmb_cntlr_DIN[16],microblaze_riscv_0_ilmb_cntlr_DIN[17],microblaze_riscv_0_ilmb_cntlr_DIN[18],microblaze_riscv_0_ilmb_cntlr_DIN[19],microblaze_riscv_0_ilmb_cntlr_DIN[20],microblaze_riscv_0_ilmb_cntlr_DIN[21],microblaze_riscv_0_ilmb_cntlr_DIN[22],microblaze_riscv_0_ilmb_cntlr_DIN[23],microblaze_riscv_0_ilmb_cntlr_DIN[24],microblaze_riscv_0_ilmb_cntlr_DIN[25],microblaze_riscv_0_ilmb_cntlr_DIN[26],microblaze_riscv_0_ilmb_cntlr_DIN[27],microblaze_riscv_0_ilmb_cntlr_DIN[28],microblaze_riscv_0_ilmb_cntlr_DIN[29],microblaze_riscv_0_ilmb_cntlr_DIN[30],microblaze_riscv_0_ilmb_cntlr_DIN[31]}),
        .douta(microblaze_riscv_0_dlmb_cntlr_DOUT),
        .doutb(microblaze_riscv_0_ilmb_cntlr_DOUT),
        .ena(microblaze_riscv_0_dlmb_cntlr_EN),
        .enb(microblaze_riscv_0_ilmb_cntlr_EN),
        .rsta(microblaze_riscv_0_dlmb_cntlr_RST),
        .rstb(microblaze_riscv_0_ilmb_cntlr_RST),
        .wea({microblaze_riscv_0_dlmb_cntlr_WE[0],microblaze_riscv_0_dlmb_cntlr_WE[1],microblaze_riscv_0_dlmb_cntlr_WE[2],microblaze_riscv_0_dlmb_cntlr_WE[3]}),
        .web({microblaze_riscv_0_ilmb_cntlr_WE[0],microblaze_riscv_0_ilmb_cntlr_WE[1],microblaze_riscv_0_ilmb_cntlr_WE[2],microblaze_riscv_0_ilmb_cntlr_WE[3]}));
endmodule

(* CORE_GENERATION_INFO = "scu35_io_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=scu35_io_design,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=21,numReposBlks=20,numNonXlnxBlks=0,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}" *) (* HW_HANDOFF = "scu35_io_design.hwdef" *) 
module scu35_io_design
   (DIP_tri_i,
    DIP_tri_o,
    DIP_tri_t,
    LEDs_tri_i,
    LEDs_tri_o,
    LEDs_tri_t,
    PMOD_i_tri_i,
    PMOD_i_tri_o,
    PMOD_i_tri_t,
    iic_acl_main_scl_i,
    iic_acl_main_scl_o,
    iic_acl_main_scl_t,
    iic_acl_main_sda_i,
    iic_acl_main_sda_o,
    iic_acl_main_sda_t,
    iic_eeprom_main_scl_i,
    iic_eeprom_main_scl_o,
    iic_eeprom_main_scl_t,
    iic_eeprom_main_sda_i,
    iic_eeprom_main_sda_o,
    iic_eeprom_main_sda_t,
    iic_ina_main_scl_i,
    iic_ina_main_scl_o,
    iic_ina_main_scl_t,
    iic_ina_main_sda_i,
    iic_ina_main_sda_o,
    iic_ina_main_sda_t,
    push_buttons_tri_i,
    reset,
    scu35_uartb_rxd,
    scu35_uartb_txd,
    sys_diff_clock_clk_n,
    sys_diff_clock_clk_p);
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 DIP TRI_I" *) (* X_INTERFACE_MODE = "Master" *) input [7:0]DIP_tri_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 DIP TRI_O" *) output [7:0]DIP_tri_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 DIP TRI_T" *) output [7:0]DIP_tri_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 LEDs TRI_I" *) (* X_INTERFACE_MODE = "Master" *) input [14:0]LEDs_tri_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 LEDs TRI_O" *) output [14:0]LEDs_tri_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 LEDs TRI_T" *) output [14:0]LEDs_tri_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 PMOD_i TRI_I" *) (* X_INTERFACE_MODE = "Master" *) input [31:0]PMOD_i_tri_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 PMOD_i TRI_O" *) output [31:0]PMOD_i_tri_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 PMOD_i TRI_T" *) output [31:0]PMOD_i_tri_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_acl_main SCL_I" *) (* X_INTERFACE_MODE = "Master" *) input iic_acl_main_scl_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_acl_main SCL_O" *) output iic_acl_main_scl_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_acl_main SCL_T" *) output iic_acl_main_scl_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_acl_main SDA_I" *) input iic_acl_main_sda_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_acl_main SDA_O" *) output iic_acl_main_sda_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_acl_main SDA_T" *) output iic_acl_main_sda_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_eeprom_main SCL_I" *) (* X_INTERFACE_MODE = "Master" *) input iic_eeprom_main_scl_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_eeprom_main SCL_O" *) output iic_eeprom_main_scl_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_eeprom_main SCL_T" *) output iic_eeprom_main_scl_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_eeprom_main SDA_I" *) input iic_eeprom_main_sda_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_eeprom_main SDA_O" *) output iic_eeprom_main_sda_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_eeprom_main SDA_T" *) output iic_eeprom_main_sda_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_ina_main SCL_I" *) (* X_INTERFACE_MODE = "Master" *) input iic_ina_main_scl_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_ina_main SCL_O" *) output iic_ina_main_scl_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_ina_main SCL_T" *) output iic_ina_main_scl_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_ina_main SDA_I" *) input iic_ina_main_sda_i;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_ina_main SDA_O" *) output iic_ina_main_sda_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 iic_ina_main SDA_T" *) output iic_ina_main_sda_t;
  (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 push_buttons TRI_I" *) (* X_INTERFACE_MODE = "Master" *) input [4:0]push_buttons_tri_i;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input reset;
  (* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 scu35_uartb RxD" *) (* X_INTERFACE_MODE = "Master" *) input scu35_uartb_rxd;
  (* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 scu35_uartb TxD" *) output scu35_uartb_txd;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 sys_diff_clock CLK_N" *) (* X_INTERFACE_MODE = "Slave" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME sys_diff_clock, CAN_DEBUG false, FREQ_HZ 100000000" *) input sys_diff_clock_clk_n;
  (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 sys_diff_clock CLK_P" *) input sys_diff_clock_clk_p;

  wire [7:0]DIP_tri_i;
  wire [7:0]DIP_tri_o;
  wire [7:0]DIP_tri_t;
  wire [14:0]LEDs_tri_i;
  wire [14:0]LEDs_tri_o;
  wire [14:0]LEDs_tri_t;
  wire [31:0]PMOD_i_tri_i;
  wire [31:0]PMOD_i_tri_o;
  wire [31:0]PMOD_i_tri_t;
  wire axi_timer_0_interrupt;
  wire axi_uartlite_0_interrupt;
  wire clk_wiz_1_locked;
  wire iic_acl_main_scl_i;
  wire iic_acl_main_scl_o;
  wire iic_acl_main_scl_t;
  wire iic_acl_main_sda_i;
  wire iic_acl_main_sda_o;
  wire iic_acl_main_sda_t;
  wire iic_eeprom_main_scl_i;
  wire iic_eeprom_main_scl_o;
  wire iic_eeprom_main_scl_t;
  wire iic_eeprom_main_sda_i;
  wire iic_eeprom_main_sda_o;
  wire iic_eeprom_main_sda_t;
  wire iic_ina_main_scl_i;
  wire iic_ina_main_scl_o;
  wire iic_ina_main_scl_t;
  wire iic_ina_main_sda_i;
  wire iic_ina_main_sda_o;
  wire iic_ina_main_sda_t;
  wire mdm_1_debug_sys_rst;
  wire microblaze_riscv_0_Clk;
  wire [31:0]microblaze_riscv_0_axi_dp_ARADDR;
  wire [2:0]microblaze_riscv_0_axi_dp_ARPROT;
  wire microblaze_riscv_0_axi_dp_ARREADY;
  wire microblaze_riscv_0_axi_dp_ARVALID;
  wire [31:0]microblaze_riscv_0_axi_dp_AWADDR;
  wire [2:0]microblaze_riscv_0_axi_dp_AWPROT;
  wire microblaze_riscv_0_axi_dp_AWREADY;
  wire microblaze_riscv_0_axi_dp_AWVALID;
  wire microblaze_riscv_0_axi_dp_BREADY;
  wire [1:0]microblaze_riscv_0_axi_dp_BRESP;
  wire microblaze_riscv_0_axi_dp_BVALID;
  wire [31:0]microblaze_riscv_0_axi_dp_RDATA;
  wire microblaze_riscv_0_axi_dp_RREADY;
  wire [1:0]microblaze_riscv_0_axi_dp_RRESP;
  wire microblaze_riscv_0_axi_dp_RVALID;
  wire [31:0]microblaze_riscv_0_axi_dp_WDATA;
  wire microblaze_riscv_0_axi_dp_WREADY;
  wire [3:0]microblaze_riscv_0_axi_dp_WSTRB;
  wire microblaze_riscv_0_axi_dp_WVALID;
  wire [4:0]microblaze_riscv_0_axi_periph_M01_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M01_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M01_AXI_ARVALID;
  wire [4:0]microblaze_riscv_0_axi_periph_M01_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M01_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M01_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M01_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M01_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M01_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M01_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M01_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M01_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M01_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M01_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M01_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M01_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M01_AXI_WVALID;
  wire [3:0]microblaze_riscv_0_axi_periph_M02_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M02_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M02_AXI_ARVALID;
  wire [3:0]microblaze_riscv_0_axi_periph_M02_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M02_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M02_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M02_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M02_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M02_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M02_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M02_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M02_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M02_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M02_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M02_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M02_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M02_AXI_WVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M03_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M03_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M03_AXI_ARVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M03_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M03_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M03_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M03_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M03_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M03_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M03_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M03_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M03_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M03_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M03_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M03_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M03_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M03_AXI_WVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M04_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M04_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M04_AXI_ARVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M04_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M04_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M04_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M04_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M04_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M04_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M04_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M04_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M04_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M04_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M04_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M04_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M04_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M04_AXI_WVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M05_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M05_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M05_AXI_ARVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M05_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M05_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M05_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M05_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M05_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M05_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M05_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M05_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M05_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M05_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M05_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M05_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M05_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M05_AXI_WVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M06_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M06_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M06_AXI_ARVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M06_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M06_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M06_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M06_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M06_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M06_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M06_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M06_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M06_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M06_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M06_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M06_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M06_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M06_AXI_WVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M07_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M07_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M07_AXI_ARVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M07_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M07_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M07_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M07_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M07_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M07_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M07_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M07_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M07_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M07_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M07_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M07_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M07_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M07_AXI_WVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M08_AXI_ARADDR;
  wire microblaze_riscv_0_axi_periph_M08_AXI_ARREADY;
  wire microblaze_riscv_0_axi_periph_M08_AXI_ARVALID;
  wire [8:0]microblaze_riscv_0_axi_periph_M08_AXI_AWADDR;
  wire microblaze_riscv_0_axi_periph_M08_AXI_AWREADY;
  wire microblaze_riscv_0_axi_periph_M08_AXI_AWVALID;
  wire microblaze_riscv_0_axi_periph_M08_AXI_BREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M08_AXI_BRESP;
  wire microblaze_riscv_0_axi_periph_M08_AXI_BVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M08_AXI_RDATA;
  wire microblaze_riscv_0_axi_periph_M08_AXI_RREADY;
  wire [1:0]microblaze_riscv_0_axi_periph_M08_AXI_RRESP;
  wire microblaze_riscv_0_axi_periph_M08_AXI_RVALID;
  wire [31:0]microblaze_riscv_0_axi_periph_M08_AXI_WDATA;
  wire microblaze_riscv_0_axi_periph_M08_AXI_WREADY;
  wire [3:0]microblaze_riscv_0_axi_periph_M08_AXI_WSTRB;
  wire microblaze_riscv_0_axi_periph_M08_AXI_WVALID;
  wire microblaze_riscv_0_debug_CAPTURE;
  wire microblaze_riscv_0_debug_CLK;
  wire microblaze_riscv_0_debug_DISABLE;
  wire [0:7]microblaze_riscv_0_debug_REG_EN;
  wire microblaze_riscv_0_debug_RST;
  wire microblaze_riscv_0_debug_SHIFT;
  wire microblaze_riscv_0_debug_TDI;
  wire microblaze_riscv_0_debug_TDO;
  wire microblaze_riscv_0_debug_UPDATE;
  wire [0:31]microblaze_riscv_0_dlmb_1_ABUS;
  wire microblaze_riscv_0_dlmb_1_ADDRSTROBE;
  wire [0:3]microblaze_riscv_0_dlmb_1_BE;
  wire microblaze_riscv_0_dlmb_1_CE;
  wire [0:31]microblaze_riscv_0_dlmb_1_READDBUS;
  wire microblaze_riscv_0_dlmb_1_READSTROBE;
  wire microblaze_riscv_0_dlmb_1_READY;
  wire microblaze_riscv_0_dlmb_1_UE;
  wire microblaze_riscv_0_dlmb_1_WAIT;
  wire [0:31]microblaze_riscv_0_dlmb_1_WRITEDBUS;
  wire microblaze_riscv_0_dlmb_1_WRITESTROBE;
  wire [0:31]microblaze_riscv_0_ilmb_1_ABUS;
  wire microblaze_riscv_0_ilmb_1_ADDRSTROBE;
  wire microblaze_riscv_0_ilmb_1_CE;
  wire [0:31]microblaze_riscv_0_ilmb_1_READDBUS;
  wire microblaze_riscv_0_ilmb_1_READSTROBE;
  wire microblaze_riscv_0_ilmb_1_READY;
  wire microblaze_riscv_0_ilmb_1_UE;
  wire microblaze_riscv_0_ilmb_1_WAIT;
  wire [8:0]microblaze_riscv_0_intc_axi_ARADDR;
  wire microblaze_riscv_0_intc_axi_ARREADY;
  wire microblaze_riscv_0_intc_axi_ARVALID;
  wire [8:0]microblaze_riscv_0_intc_axi_AWADDR;
  wire microblaze_riscv_0_intc_axi_AWREADY;
  wire microblaze_riscv_0_intc_axi_AWVALID;
  wire microblaze_riscv_0_intc_axi_BREADY;
  wire [1:0]microblaze_riscv_0_intc_axi_BRESP;
  wire microblaze_riscv_0_intc_axi_BVALID;
  wire [31:0]microblaze_riscv_0_intc_axi_RDATA;
  wire microblaze_riscv_0_intc_axi_RREADY;
  wire [1:0]microblaze_riscv_0_intc_axi_RRESP;
  wire microblaze_riscv_0_intc_axi_RVALID;
  wire [31:0]microblaze_riscv_0_intc_axi_WDATA;
  wire microblaze_riscv_0_intc_axi_WREADY;
  wire [3:0]microblaze_riscv_0_intc_axi_WSTRB;
  wire microblaze_riscv_0_intc_axi_WVALID;
  wire [0:1]microblaze_riscv_0_interrupt_ACK;
  wire [31:0]microblaze_riscv_0_interrupt_ADDRESS;
  wire microblaze_riscv_0_interrupt_INTERRUPT;
  wire [1:0]microblaze_riscv_0_intr;
  wire [4:0]push_buttons_tri_i;
  wire reset;
  wire [0:0]rst_clk_wiz_1_100M_bus_struct_reset;
  wire rst_clk_wiz_1_100M_mb_reset;
  wire [0:0]rst_clk_wiz_1_100M_peripheral_aresetn;
  wire scu35_uartb_rxd;
  wire scu35_uartb_txd;
  wire sys_diff_clock_clk_n;
  wire sys_diff_clock_clk_p;

  scu35_io_design_axi_timer_0_0 axi_timer_0
       (.capturetrig0(1'b0),
        .capturetrig1(1'b0),
        .freeze(1'b0),
        .interrupt(axi_timer_0_interrupt),
        .s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M01_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M01_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M01_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M01_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M01_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M01_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M01_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M01_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M01_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M01_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M01_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M01_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M01_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M01_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M01_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M01_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M01_AXI_WVALID));
  scu35_io_design_axi_uartlite_0_0 axi_uartlite_0
       (.interrupt(axi_uartlite_0_interrupt),
        .rx(scu35_uartb_rxd),
        .s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M02_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M02_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M02_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M02_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M02_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M02_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M02_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M02_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M02_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M02_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M02_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M02_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M02_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M02_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M02_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M02_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M02_AXI_WVALID),
        .tx(scu35_uartb_txd));
  scu35_io_design_clk_wiz_1_0 clk_wiz_1
       (.clk_in1_n(sys_diff_clock_clk_n),
        .clk_in1_p(sys_diff_clock_clk_p),
        .clk_out1(microblaze_riscv_0_Clk),
        .locked(clk_wiz_1_locked),
        .resetn(reset));
  scu35_io_design_gpio_LEDs_0 gpio_LEDs
       (.gpio_io_i(LEDs_tri_i),
        .gpio_io_o(LEDs_tri_o),
        .gpio_io_t(LEDs_tri_t),
        .s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M03_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M03_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M03_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M03_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M03_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M03_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M03_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M03_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M03_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M03_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M03_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M03_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M03_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M03_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M03_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M03_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M03_AXI_WVALID));
  scu35_io_design_gpio_PMOD_i_0 gpio_PMOD_i
       (.gpio_io_i(PMOD_i_tri_i),
        .gpio_io_o(PMOD_i_tri_o),
        .gpio_io_t(PMOD_i_tri_t),
        .s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M08_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M08_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M08_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M08_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M08_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M08_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M08_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M08_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M08_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M08_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M08_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M08_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M08_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M08_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M08_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M08_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M08_AXI_WVALID));
  scu35_io_design_gpio_pushB_DIP_0 gpio_pushB_DIP
       (.gpio2_io_i(DIP_tri_i),
        .gpio2_io_o(DIP_tri_o),
        .gpio2_io_t(DIP_tri_t),
        .gpio_io_i(push_buttons_tri_i),
        .s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M04_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M04_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M04_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M04_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M04_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M04_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M04_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M04_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M04_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M04_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M04_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M04_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M04_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M04_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M04_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M04_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M04_AXI_WVALID));
  scu35_io_design_iic_acl_0 iic_acl
       (.s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M05_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M05_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M05_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M05_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M05_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M05_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M05_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M05_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M05_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M05_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M05_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M05_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M05_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M05_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M05_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M05_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M05_AXI_WVALID),
        .scl_i(iic_acl_main_scl_i),
        .scl_o(iic_acl_main_scl_o),
        .scl_t(iic_acl_main_scl_t),
        .sda_i(iic_acl_main_sda_i),
        .sda_o(iic_acl_main_sda_o),
        .sda_t(iic_acl_main_sda_t));
  scu35_io_design_iic_eeprom_0 iic_eeprom
       (.s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M06_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M06_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M06_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M06_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M06_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M06_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M06_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M06_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M06_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M06_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M06_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M06_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M06_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M06_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M06_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M06_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M06_AXI_WVALID),
        .scl_i(iic_eeprom_main_scl_i),
        .scl_o(iic_eeprom_main_scl_o),
        .scl_t(iic_eeprom_main_scl_t),
        .sda_i(iic_eeprom_main_sda_i),
        .sda_o(iic_eeprom_main_sda_o),
        .sda_t(iic_eeprom_main_sda_t));
  scu35_io_design_iic_ina_0 iic_ina
       (.s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_axi_periph_M07_AXI_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_axi_periph_M07_AXI_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_axi_periph_M07_AXI_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_axi_periph_M07_AXI_AWADDR),
        .s_axi_awready(microblaze_riscv_0_axi_periph_M07_AXI_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_axi_periph_M07_AXI_AWVALID),
        .s_axi_bready(microblaze_riscv_0_axi_periph_M07_AXI_BREADY),
        .s_axi_bresp(microblaze_riscv_0_axi_periph_M07_AXI_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_axi_periph_M07_AXI_BVALID),
        .s_axi_rdata(microblaze_riscv_0_axi_periph_M07_AXI_RDATA),
        .s_axi_rready(microblaze_riscv_0_axi_periph_M07_AXI_RREADY),
        .s_axi_rresp(microblaze_riscv_0_axi_periph_M07_AXI_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_axi_periph_M07_AXI_RVALID),
        .s_axi_wdata(microblaze_riscv_0_axi_periph_M07_AXI_WDATA),
        .s_axi_wready(microblaze_riscv_0_axi_periph_M07_AXI_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_axi_periph_M07_AXI_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_axi_periph_M07_AXI_WVALID),
        .scl_i(iic_ina_main_scl_i),
        .scl_o(iic_ina_main_scl_o),
        .scl_t(iic_ina_main_scl_t),
        .sda_i(iic_ina_main_sda_i),
        .sda_o(iic_ina_main_sda_o),
        .sda_t(iic_ina_main_sda_t));
  scu35_io_design_mdm_1_0 mdm_1
       (.Dbg_Capture_0(microblaze_riscv_0_debug_CAPTURE),
        .Dbg_Clk_0(microblaze_riscv_0_debug_CLK),
        .Dbg_Disable_0(microblaze_riscv_0_debug_DISABLE),
        .Dbg_Reg_En_0(microblaze_riscv_0_debug_REG_EN),
        .Dbg_Rst_0(microblaze_riscv_0_debug_RST),
        .Dbg_Shift_0(microblaze_riscv_0_debug_SHIFT),
        .Dbg_TDI_0(microblaze_riscv_0_debug_TDI),
        .Dbg_TDO_0(microblaze_riscv_0_debug_TDO),
        .Dbg_Update_0(microblaze_riscv_0_debug_UPDATE),
        .Debug_SYS_Rst(mdm_1_debug_sys_rst));
  (* BMM_INFO_PROCESSOR = "riscv > scu35_io_design microblaze_riscv_0_local_memory/dlmb_bram_if_cntlr" *) 
  (* KEEP_HIERARCHY = "YES" *) 
  scu35_io_design_microblaze_riscv_0_0 microblaze_riscv_0
       (.Byte_Enable(microblaze_riscv_0_dlmb_1_BE),
        .Clk(microblaze_riscv_0_Clk),
        .DCE(microblaze_riscv_0_dlmb_1_CE),
        .DReady(microblaze_riscv_0_dlmb_1_READY),
        .DUE(microblaze_riscv_0_dlmb_1_UE),
        .DWait(microblaze_riscv_0_dlmb_1_WAIT),
        .D_AS(microblaze_riscv_0_dlmb_1_ADDRSTROBE),
        .Data_Addr(microblaze_riscv_0_dlmb_1_ABUS),
        .Data_Read(microblaze_riscv_0_dlmb_1_READDBUS),
        .Data_Write(microblaze_riscv_0_dlmb_1_WRITEDBUS),
        .Dbg_Capture(microblaze_riscv_0_debug_CAPTURE),
        .Dbg_Clk(microblaze_riscv_0_debug_CLK),
        .Dbg_Disable(microblaze_riscv_0_debug_DISABLE),
        .Dbg_Reg_En(microblaze_riscv_0_debug_REG_EN),
        .Dbg_Shift(microblaze_riscv_0_debug_SHIFT),
        .Dbg_TDI(microblaze_riscv_0_debug_TDI),
        .Dbg_TDO(microblaze_riscv_0_debug_TDO),
        .Dbg_Trig_Ack_In({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Trig_Out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Update(microblaze_riscv_0_debug_UPDATE),
        .Debug_Rst(microblaze_riscv_0_debug_RST),
        .ICE(microblaze_riscv_0_ilmb_1_CE),
        .IFetch(microblaze_riscv_0_ilmb_1_READSTROBE),
        .IReady(microblaze_riscv_0_ilmb_1_READY),
        .IUE(microblaze_riscv_0_ilmb_1_UE),
        .IWAIT(microblaze_riscv_0_ilmb_1_WAIT),
        .I_AS(microblaze_riscv_0_ilmb_1_ADDRSTROBE),
        .Instr(microblaze_riscv_0_ilmb_1_READDBUS),
        .Instr_Addr(microblaze_riscv_0_ilmb_1_ABUS),
        .Interrupt(microblaze_riscv_0_interrupt_INTERRUPT),
        .Interrupt_Ack(microblaze_riscv_0_interrupt_ACK),
        .Interrupt_Address({microblaze_riscv_0_interrupt_ADDRESS[31],microblaze_riscv_0_interrupt_ADDRESS[30],microblaze_riscv_0_interrupt_ADDRESS[29],microblaze_riscv_0_interrupt_ADDRESS[28],microblaze_riscv_0_interrupt_ADDRESS[27],microblaze_riscv_0_interrupt_ADDRESS[26],microblaze_riscv_0_interrupt_ADDRESS[25],microblaze_riscv_0_interrupt_ADDRESS[24],microblaze_riscv_0_interrupt_ADDRESS[23],microblaze_riscv_0_interrupt_ADDRESS[22],microblaze_riscv_0_interrupt_ADDRESS[21],microblaze_riscv_0_interrupt_ADDRESS[20],microblaze_riscv_0_interrupt_ADDRESS[19],microblaze_riscv_0_interrupt_ADDRESS[18],microblaze_riscv_0_interrupt_ADDRESS[17],microblaze_riscv_0_interrupt_ADDRESS[16],microblaze_riscv_0_interrupt_ADDRESS[15],microblaze_riscv_0_interrupt_ADDRESS[14],microblaze_riscv_0_interrupt_ADDRESS[13],microblaze_riscv_0_interrupt_ADDRESS[12],microblaze_riscv_0_interrupt_ADDRESS[11],microblaze_riscv_0_interrupt_ADDRESS[10],microblaze_riscv_0_interrupt_ADDRESS[9],microblaze_riscv_0_interrupt_ADDRESS[8],microblaze_riscv_0_interrupt_ADDRESS[7],microblaze_riscv_0_interrupt_ADDRESS[6],microblaze_riscv_0_interrupt_ADDRESS[5],microblaze_riscv_0_interrupt_ADDRESS[4],microblaze_riscv_0_interrupt_ADDRESS[3],microblaze_riscv_0_interrupt_ADDRESS[2],microblaze_riscv_0_interrupt_ADDRESS[1],microblaze_riscv_0_interrupt_ADDRESS[0]}),
        .M_AXI_DP_ARADDR(microblaze_riscv_0_axi_dp_ARADDR),
        .M_AXI_DP_ARPROT(microblaze_riscv_0_axi_dp_ARPROT),
        .M_AXI_DP_ARREADY(microblaze_riscv_0_axi_dp_ARREADY),
        .M_AXI_DP_ARVALID(microblaze_riscv_0_axi_dp_ARVALID),
        .M_AXI_DP_AWADDR(microblaze_riscv_0_axi_dp_AWADDR),
        .M_AXI_DP_AWPROT(microblaze_riscv_0_axi_dp_AWPROT),
        .M_AXI_DP_AWREADY(microblaze_riscv_0_axi_dp_AWREADY),
        .M_AXI_DP_AWVALID(microblaze_riscv_0_axi_dp_AWVALID),
        .M_AXI_DP_BREADY(microblaze_riscv_0_axi_dp_BREADY),
        .M_AXI_DP_BRESP(microblaze_riscv_0_axi_dp_BRESP),
        .M_AXI_DP_BVALID(microblaze_riscv_0_axi_dp_BVALID),
        .M_AXI_DP_RDATA(microblaze_riscv_0_axi_dp_RDATA),
        .M_AXI_DP_RREADY(microblaze_riscv_0_axi_dp_RREADY),
        .M_AXI_DP_RRESP(microblaze_riscv_0_axi_dp_RRESP),
        .M_AXI_DP_RVALID(microblaze_riscv_0_axi_dp_RVALID),
        .M_AXI_DP_WDATA(microblaze_riscv_0_axi_dp_WDATA),
        .M_AXI_DP_WREADY(microblaze_riscv_0_axi_dp_WREADY),
        .M_AXI_DP_WSTRB(microblaze_riscv_0_axi_dp_WSTRB),
        .M_AXI_DP_WVALID(microblaze_riscv_0_axi_dp_WVALID),
        .Read_Strobe(microblaze_riscv_0_dlmb_1_READSTROBE),
        .Reset(rst_clk_wiz_1_100M_mb_reset),
        .Write_Strobe(microblaze_riscv_0_dlmb_1_WRITESTROBE));
  scu35_io_design_microblaze_riscv_0_axi_intc_0 microblaze_riscv_0_axi_intc
       (.interrupt_address(microblaze_riscv_0_interrupt_ADDRESS),
        .intr(microblaze_riscv_0_intr),
        .irq(microblaze_riscv_0_interrupt_INTERRUPT),
        .processor_ack({microblaze_riscv_0_interrupt_ACK[0],microblaze_riscv_0_interrupt_ACK[1]}),
        .processor_clk(microblaze_riscv_0_Clk),
        .processor_rst(rst_clk_wiz_1_100M_mb_reset),
        .s_axi_aclk(microblaze_riscv_0_Clk),
        .s_axi_araddr(microblaze_riscv_0_intc_axi_ARADDR),
        .s_axi_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .s_axi_arready(microblaze_riscv_0_intc_axi_ARREADY),
        .s_axi_arvalid(microblaze_riscv_0_intc_axi_ARVALID),
        .s_axi_awaddr(microblaze_riscv_0_intc_axi_AWADDR),
        .s_axi_awready(microblaze_riscv_0_intc_axi_AWREADY),
        .s_axi_awvalid(microblaze_riscv_0_intc_axi_AWVALID),
        .s_axi_bready(microblaze_riscv_0_intc_axi_BREADY),
        .s_axi_bresp(microblaze_riscv_0_intc_axi_BRESP),
        .s_axi_bvalid(microblaze_riscv_0_intc_axi_BVALID),
        .s_axi_rdata(microblaze_riscv_0_intc_axi_RDATA),
        .s_axi_rready(microblaze_riscv_0_intc_axi_RREADY),
        .s_axi_rresp(microblaze_riscv_0_intc_axi_RRESP),
        .s_axi_rvalid(microblaze_riscv_0_intc_axi_RVALID),
        .s_axi_wdata(microblaze_riscv_0_intc_axi_WDATA),
        .s_axi_wready(microblaze_riscv_0_intc_axi_WREADY),
        .s_axi_wstrb(microblaze_riscv_0_intc_axi_WSTRB),
        .s_axi_wvalid(microblaze_riscv_0_intc_axi_WVALID));
  scu35_io_design_microblaze_riscv_0_axi_periph_0 microblaze_riscv_0_axi_periph
       (.M00_AXI_araddr(microblaze_riscv_0_intc_axi_ARADDR),
        .M00_AXI_arready(microblaze_riscv_0_intc_axi_ARREADY),
        .M00_AXI_arvalid(microblaze_riscv_0_intc_axi_ARVALID),
        .M00_AXI_awaddr(microblaze_riscv_0_intc_axi_AWADDR),
        .M00_AXI_awready(microblaze_riscv_0_intc_axi_AWREADY),
        .M00_AXI_awvalid(microblaze_riscv_0_intc_axi_AWVALID),
        .M00_AXI_bready(microblaze_riscv_0_intc_axi_BREADY),
        .M00_AXI_bresp(microblaze_riscv_0_intc_axi_BRESP),
        .M00_AXI_bvalid(microblaze_riscv_0_intc_axi_BVALID),
        .M00_AXI_rdata(microblaze_riscv_0_intc_axi_RDATA),
        .M00_AXI_rready(microblaze_riscv_0_intc_axi_RREADY),
        .M00_AXI_rresp(microblaze_riscv_0_intc_axi_RRESP),
        .M00_AXI_rvalid(microblaze_riscv_0_intc_axi_RVALID),
        .M00_AXI_wdata(microblaze_riscv_0_intc_axi_WDATA),
        .M00_AXI_wready(microblaze_riscv_0_intc_axi_WREADY),
        .M00_AXI_wstrb(microblaze_riscv_0_intc_axi_WSTRB),
        .M00_AXI_wvalid(microblaze_riscv_0_intc_axi_WVALID),
        .M01_AXI_araddr(microblaze_riscv_0_axi_periph_M01_AXI_ARADDR),
        .M01_AXI_arready(microblaze_riscv_0_axi_periph_M01_AXI_ARREADY),
        .M01_AXI_arvalid(microblaze_riscv_0_axi_periph_M01_AXI_ARVALID),
        .M01_AXI_awaddr(microblaze_riscv_0_axi_periph_M01_AXI_AWADDR),
        .M01_AXI_awready(microblaze_riscv_0_axi_periph_M01_AXI_AWREADY),
        .M01_AXI_awvalid(microblaze_riscv_0_axi_periph_M01_AXI_AWVALID),
        .M01_AXI_bready(microblaze_riscv_0_axi_periph_M01_AXI_BREADY),
        .M01_AXI_bresp(microblaze_riscv_0_axi_periph_M01_AXI_BRESP),
        .M01_AXI_bvalid(microblaze_riscv_0_axi_periph_M01_AXI_BVALID),
        .M01_AXI_rdata(microblaze_riscv_0_axi_periph_M01_AXI_RDATA),
        .M01_AXI_rready(microblaze_riscv_0_axi_periph_M01_AXI_RREADY),
        .M01_AXI_rresp(microblaze_riscv_0_axi_periph_M01_AXI_RRESP),
        .M01_AXI_rvalid(microblaze_riscv_0_axi_periph_M01_AXI_RVALID),
        .M01_AXI_wdata(microblaze_riscv_0_axi_periph_M01_AXI_WDATA),
        .M01_AXI_wready(microblaze_riscv_0_axi_periph_M01_AXI_WREADY),
        .M01_AXI_wstrb(microblaze_riscv_0_axi_periph_M01_AXI_WSTRB),
        .M01_AXI_wvalid(microblaze_riscv_0_axi_periph_M01_AXI_WVALID),
        .M02_AXI_araddr(microblaze_riscv_0_axi_periph_M02_AXI_ARADDR),
        .M02_AXI_arready(microblaze_riscv_0_axi_periph_M02_AXI_ARREADY),
        .M02_AXI_arvalid(microblaze_riscv_0_axi_periph_M02_AXI_ARVALID),
        .M02_AXI_awaddr(microblaze_riscv_0_axi_periph_M02_AXI_AWADDR),
        .M02_AXI_awready(microblaze_riscv_0_axi_periph_M02_AXI_AWREADY),
        .M02_AXI_awvalid(microblaze_riscv_0_axi_periph_M02_AXI_AWVALID),
        .M02_AXI_bready(microblaze_riscv_0_axi_periph_M02_AXI_BREADY),
        .M02_AXI_bresp(microblaze_riscv_0_axi_periph_M02_AXI_BRESP),
        .M02_AXI_bvalid(microblaze_riscv_0_axi_periph_M02_AXI_BVALID),
        .M02_AXI_rdata(microblaze_riscv_0_axi_periph_M02_AXI_RDATA),
        .M02_AXI_rready(microblaze_riscv_0_axi_periph_M02_AXI_RREADY),
        .M02_AXI_rresp(microblaze_riscv_0_axi_periph_M02_AXI_RRESP),
        .M02_AXI_rvalid(microblaze_riscv_0_axi_periph_M02_AXI_RVALID),
        .M02_AXI_wdata(microblaze_riscv_0_axi_periph_M02_AXI_WDATA),
        .M02_AXI_wready(microblaze_riscv_0_axi_periph_M02_AXI_WREADY),
        .M02_AXI_wstrb(microblaze_riscv_0_axi_periph_M02_AXI_WSTRB),
        .M02_AXI_wvalid(microblaze_riscv_0_axi_periph_M02_AXI_WVALID),
        .M03_AXI_araddr(microblaze_riscv_0_axi_periph_M03_AXI_ARADDR),
        .M03_AXI_arready(microblaze_riscv_0_axi_periph_M03_AXI_ARREADY),
        .M03_AXI_arvalid(microblaze_riscv_0_axi_periph_M03_AXI_ARVALID),
        .M03_AXI_awaddr(microblaze_riscv_0_axi_periph_M03_AXI_AWADDR),
        .M03_AXI_awready(microblaze_riscv_0_axi_periph_M03_AXI_AWREADY),
        .M03_AXI_awvalid(microblaze_riscv_0_axi_periph_M03_AXI_AWVALID),
        .M03_AXI_bready(microblaze_riscv_0_axi_periph_M03_AXI_BREADY),
        .M03_AXI_bresp(microblaze_riscv_0_axi_periph_M03_AXI_BRESP),
        .M03_AXI_bvalid(microblaze_riscv_0_axi_periph_M03_AXI_BVALID),
        .M03_AXI_rdata(microblaze_riscv_0_axi_periph_M03_AXI_RDATA),
        .M03_AXI_rready(microblaze_riscv_0_axi_periph_M03_AXI_RREADY),
        .M03_AXI_rresp(microblaze_riscv_0_axi_periph_M03_AXI_RRESP),
        .M03_AXI_rvalid(microblaze_riscv_0_axi_periph_M03_AXI_RVALID),
        .M03_AXI_wdata(microblaze_riscv_0_axi_periph_M03_AXI_WDATA),
        .M03_AXI_wready(microblaze_riscv_0_axi_periph_M03_AXI_WREADY),
        .M03_AXI_wstrb(microblaze_riscv_0_axi_periph_M03_AXI_WSTRB),
        .M03_AXI_wvalid(microblaze_riscv_0_axi_periph_M03_AXI_WVALID),
        .M04_AXI_araddr(microblaze_riscv_0_axi_periph_M04_AXI_ARADDR),
        .M04_AXI_arready(microblaze_riscv_0_axi_periph_M04_AXI_ARREADY),
        .M04_AXI_arvalid(microblaze_riscv_0_axi_periph_M04_AXI_ARVALID),
        .M04_AXI_awaddr(microblaze_riscv_0_axi_periph_M04_AXI_AWADDR),
        .M04_AXI_awready(microblaze_riscv_0_axi_periph_M04_AXI_AWREADY),
        .M04_AXI_awvalid(microblaze_riscv_0_axi_periph_M04_AXI_AWVALID),
        .M04_AXI_bready(microblaze_riscv_0_axi_periph_M04_AXI_BREADY),
        .M04_AXI_bresp(microblaze_riscv_0_axi_periph_M04_AXI_BRESP),
        .M04_AXI_bvalid(microblaze_riscv_0_axi_periph_M04_AXI_BVALID),
        .M04_AXI_rdata(microblaze_riscv_0_axi_periph_M04_AXI_RDATA),
        .M04_AXI_rready(microblaze_riscv_0_axi_periph_M04_AXI_RREADY),
        .M04_AXI_rresp(microblaze_riscv_0_axi_periph_M04_AXI_RRESP),
        .M04_AXI_rvalid(microblaze_riscv_0_axi_periph_M04_AXI_RVALID),
        .M04_AXI_wdata(microblaze_riscv_0_axi_periph_M04_AXI_WDATA),
        .M04_AXI_wready(microblaze_riscv_0_axi_periph_M04_AXI_WREADY),
        .M04_AXI_wstrb(microblaze_riscv_0_axi_periph_M04_AXI_WSTRB),
        .M04_AXI_wvalid(microblaze_riscv_0_axi_periph_M04_AXI_WVALID),
        .M05_AXI_araddr(microblaze_riscv_0_axi_periph_M05_AXI_ARADDR),
        .M05_AXI_arready(microblaze_riscv_0_axi_periph_M05_AXI_ARREADY),
        .M05_AXI_arvalid(microblaze_riscv_0_axi_periph_M05_AXI_ARVALID),
        .M05_AXI_awaddr(microblaze_riscv_0_axi_periph_M05_AXI_AWADDR),
        .M05_AXI_awready(microblaze_riscv_0_axi_periph_M05_AXI_AWREADY),
        .M05_AXI_awvalid(microblaze_riscv_0_axi_periph_M05_AXI_AWVALID),
        .M05_AXI_bready(microblaze_riscv_0_axi_periph_M05_AXI_BREADY),
        .M05_AXI_bresp(microblaze_riscv_0_axi_periph_M05_AXI_BRESP),
        .M05_AXI_bvalid(microblaze_riscv_0_axi_periph_M05_AXI_BVALID),
        .M05_AXI_rdata(microblaze_riscv_0_axi_periph_M05_AXI_RDATA),
        .M05_AXI_rready(microblaze_riscv_0_axi_periph_M05_AXI_RREADY),
        .M05_AXI_rresp(microblaze_riscv_0_axi_periph_M05_AXI_RRESP),
        .M05_AXI_rvalid(microblaze_riscv_0_axi_periph_M05_AXI_RVALID),
        .M05_AXI_wdata(microblaze_riscv_0_axi_periph_M05_AXI_WDATA),
        .M05_AXI_wready(microblaze_riscv_0_axi_periph_M05_AXI_WREADY),
        .M05_AXI_wstrb(microblaze_riscv_0_axi_periph_M05_AXI_WSTRB),
        .M05_AXI_wvalid(microblaze_riscv_0_axi_periph_M05_AXI_WVALID),
        .M06_AXI_araddr(microblaze_riscv_0_axi_periph_M06_AXI_ARADDR),
        .M06_AXI_arready(microblaze_riscv_0_axi_periph_M06_AXI_ARREADY),
        .M06_AXI_arvalid(microblaze_riscv_0_axi_periph_M06_AXI_ARVALID),
        .M06_AXI_awaddr(microblaze_riscv_0_axi_periph_M06_AXI_AWADDR),
        .M06_AXI_awready(microblaze_riscv_0_axi_periph_M06_AXI_AWREADY),
        .M06_AXI_awvalid(microblaze_riscv_0_axi_periph_M06_AXI_AWVALID),
        .M06_AXI_bready(microblaze_riscv_0_axi_periph_M06_AXI_BREADY),
        .M06_AXI_bresp(microblaze_riscv_0_axi_periph_M06_AXI_BRESP),
        .M06_AXI_bvalid(microblaze_riscv_0_axi_periph_M06_AXI_BVALID),
        .M06_AXI_rdata(microblaze_riscv_0_axi_periph_M06_AXI_RDATA),
        .M06_AXI_rready(microblaze_riscv_0_axi_periph_M06_AXI_RREADY),
        .M06_AXI_rresp(microblaze_riscv_0_axi_periph_M06_AXI_RRESP),
        .M06_AXI_rvalid(microblaze_riscv_0_axi_periph_M06_AXI_RVALID),
        .M06_AXI_wdata(microblaze_riscv_0_axi_periph_M06_AXI_WDATA),
        .M06_AXI_wready(microblaze_riscv_0_axi_periph_M06_AXI_WREADY),
        .M06_AXI_wstrb(microblaze_riscv_0_axi_periph_M06_AXI_WSTRB),
        .M06_AXI_wvalid(microblaze_riscv_0_axi_periph_M06_AXI_WVALID),
        .M07_AXI_araddr(microblaze_riscv_0_axi_periph_M07_AXI_ARADDR),
        .M07_AXI_arready(microblaze_riscv_0_axi_periph_M07_AXI_ARREADY),
        .M07_AXI_arvalid(microblaze_riscv_0_axi_periph_M07_AXI_ARVALID),
        .M07_AXI_awaddr(microblaze_riscv_0_axi_periph_M07_AXI_AWADDR),
        .M07_AXI_awready(microblaze_riscv_0_axi_periph_M07_AXI_AWREADY),
        .M07_AXI_awvalid(microblaze_riscv_0_axi_periph_M07_AXI_AWVALID),
        .M07_AXI_bready(microblaze_riscv_0_axi_periph_M07_AXI_BREADY),
        .M07_AXI_bresp(microblaze_riscv_0_axi_periph_M07_AXI_BRESP),
        .M07_AXI_bvalid(microblaze_riscv_0_axi_periph_M07_AXI_BVALID),
        .M07_AXI_rdata(microblaze_riscv_0_axi_periph_M07_AXI_RDATA),
        .M07_AXI_rready(microblaze_riscv_0_axi_periph_M07_AXI_RREADY),
        .M07_AXI_rresp(microblaze_riscv_0_axi_periph_M07_AXI_RRESP),
        .M07_AXI_rvalid(microblaze_riscv_0_axi_periph_M07_AXI_RVALID),
        .M07_AXI_wdata(microblaze_riscv_0_axi_periph_M07_AXI_WDATA),
        .M07_AXI_wready(microblaze_riscv_0_axi_periph_M07_AXI_WREADY),
        .M07_AXI_wstrb(microblaze_riscv_0_axi_periph_M07_AXI_WSTRB),
        .M07_AXI_wvalid(microblaze_riscv_0_axi_periph_M07_AXI_WVALID),
        .M08_AXI_araddr(microblaze_riscv_0_axi_periph_M08_AXI_ARADDR),
        .M08_AXI_arready(microblaze_riscv_0_axi_periph_M08_AXI_ARREADY),
        .M08_AXI_arvalid(microblaze_riscv_0_axi_periph_M08_AXI_ARVALID),
        .M08_AXI_awaddr(microblaze_riscv_0_axi_periph_M08_AXI_AWADDR),
        .M08_AXI_awready(microblaze_riscv_0_axi_periph_M08_AXI_AWREADY),
        .M08_AXI_awvalid(microblaze_riscv_0_axi_periph_M08_AXI_AWVALID),
        .M08_AXI_bready(microblaze_riscv_0_axi_periph_M08_AXI_BREADY),
        .M08_AXI_bresp(microblaze_riscv_0_axi_periph_M08_AXI_BRESP),
        .M08_AXI_bvalid(microblaze_riscv_0_axi_periph_M08_AXI_BVALID),
        .M08_AXI_rdata(microblaze_riscv_0_axi_periph_M08_AXI_RDATA),
        .M08_AXI_rready(microblaze_riscv_0_axi_periph_M08_AXI_RREADY),
        .M08_AXI_rresp(microblaze_riscv_0_axi_periph_M08_AXI_RRESP),
        .M08_AXI_rvalid(microblaze_riscv_0_axi_periph_M08_AXI_RVALID),
        .M08_AXI_wdata(microblaze_riscv_0_axi_periph_M08_AXI_WDATA),
        .M08_AXI_wready(microblaze_riscv_0_axi_periph_M08_AXI_WREADY),
        .M08_AXI_wstrb(microblaze_riscv_0_axi_periph_M08_AXI_WSTRB),
        .M08_AXI_wvalid(microblaze_riscv_0_axi_periph_M08_AXI_WVALID),
        .S00_AXI_araddr(microblaze_riscv_0_axi_dp_ARADDR),
        .S00_AXI_arprot(microblaze_riscv_0_axi_dp_ARPROT),
        .S00_AXI_arready(microblaze_riscv_0_axi_dp_ARREADY),
        .S00_AXI_arvalid(microblaze_riscv_0_axi_dp_ARVALID),
        .S00_AXI_awaddr(microblaze_riscv_0_axi_dp_AWADDR),
        .S00_AXI_awprot(microblaze_riscv_0_axi_dp_AWPROT),
        .S00_AXI_awready(microblaze_riscv_0_axi_dp_AWREADY),
        .S00_AXI_awvalid(microblaze_riscv_0_axi_dp_AWVALID),
        .S00_AXI_bready(microblaze_riscv_0_axi_dp_BREADY),
        .S00_AXI_bresp(microblaze_riscv_0_axi_dp_BRESP),
        .S00_AXI_bvalid(microblaze_riscv_0_axi_dp_BVALID),
        .S00_AXI_rdata(microblaze_riscv_0_axi_dp_RDATA),
        .S00_AXI_rready(microblaze_riscv_0_axi_dp_RREADY),
        .S00_AXI_rresp(microblaze_riscv_0_axi_dp_RRESP),
        .S00_AXI_rvalid(microblaze_riscv_0_axi_dp_RVALID),
        .S00_AXI_wdata(microblaze_riscv_0_axi_dp_WDATA),
        .S00_AXI_wready(microblaze_riscv_0_axi_dp_WREADY),
        .S00_AXI_wstrb(microblaze_riscv_0_axi_dp_WSTRB),
        .S00_AXI_wvalid(microblaze_riscv_0_axi_dp_WVALID),
        .aclk(microblaze_riscv_0_Clk),
        .aresetn(rst_clk_wiz_1_100M_peripheral_aresetn));
  assign microblaze_riscv_0_intr = {axi_timer_0_interrupt, axi_uartlite_0_interrupt};
  microblaze_riscv_0_local_memory_imp_WXRDSO microblaze_riscv_0_local_memory
       (.DLMB_abus(microblaze_riscv_0_dlmb_1_ABUS),
        .DLMB_addrstrobe(microblaze_riscv_0_dlmb_1_ADDRSTROBE),
        .DLMB_be(microblaze_riscv_0_dlmb_1_BE),
        .DLMB_ce(microblaze_riscv_0_dlmb_1_CE),
        .DLMB_readdbus(microblaze_riscv_0_dlmb_1_READDBUS),
        .DLMB_readstrobe(microblaze_riscv_0_dlmb_1_READSTROBE),
        .DLMB_ready(microblaze_riscv_0_dlmb_1_READY),
        .DLMB_ue(microblaze_riscv_0_dlmb_1_UE),
        .DLMB_wait(microblaze_riscv_0_dlmb_1_WAIT),
        .DLMB_writedbus(microblaze_riscv_0_dlmb_1_WRITEDBUS),
        .DLMB_writestrobe(microblaze_riscv_0_dlmb_1_WRITESTROBE),
        .ILMB_abus(microblaze_riscv_0_ilmb_1_ABUS),
        .ILMB_addrstrobe(microblaze_riscv_0_ilmb_1_ADDRSTROBE),
        .ILMB_ce(microblaze_riscv_0_ilmb_1_CE),
        .ILMB_readdbus(microblaze_riscv_0_ilmb_1_READDBUS),
        .ILMB_readstrobe(microblaze_riscv_0_ilmb_1_READSTROBE),
        .ILMB_ready(microblaze_riscv_0_ilmb_1_READY),
        .ILMB_ue(microblaze_riscv_0_ilmb_1_UE),
        .ILMB_wait(microblaze_riscv_0_ilmb_1_WAIT),
        .LMB_Clk(microblaze_riscv_0_Clk),
        .SYS_Rst(rst_clk_wiz_1_100M_bus_struct_reset));
  scu35_io_design_rst_clk_wiz_1_200M_0 rst_clk_wiz_1_200M
       (.aux_reset_in(1'b1),
        .bus_struct_reset(rst_clk_wiz_1_100M_bus_struct_reset),
        .dcm_locked(clk_wiz_1_locked),
        .ext_reset_in(reset),
        .mb_debug_sys_rst(mdm_1_debug_sys_rst),
        .mb_reset(rst_clk_wiz_1_100M_mb_reset),
        .peripheral_aresetn(rst_clk_wiz_1_100M_peripheral_aresetn),
        .slowest_sync_clk(microblaze_riscv_0_Clk));
endmodule
