-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date        : Tue Nov 18 10:29:30 2025
-- Host        : xhdshabbirk50x running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command     : write_vhdl -force -mode funcsim
--               /scratch/shabbirk/scu35-io-trd/hw/project/scu35_io_design.gen/sources_1/bd/scu35_io_design/ip/scu35_io_design_mdm_1_0/scu35_io_design_mdm_1_0_sim_netlist.vhdl
-- Design      : scu35_io_design_mdm_1_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xcsu35p-sbvb625-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MB_BSCANE2 is
  port (
    \Use_E2.BSCANE2_I_0\ : out STD_LOGIC;
    \Use_E2.BSCANE2_I_1\ : out STD_LOGIC;
    tck : out STD_LOGIC;
    I0 : out STD_LOGIC;
    \Use_JTAG_BSCAN.mode_reg_reg\ : out STD_LOGIC;
    CO : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Use_JTAG_BSCAN.tap_cnt_ok_reg\ : out STD_LOGIC;
    \Use_JTAG_BSCAN.tap_cnt_ok_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Use_JTAG_BSCAN.id_flag_reg\ : out STD_LOGIC;
    \Internal_BSCANID.bscanid_sel_reg\ : out STD_LOGIC;
    \Internal_BSCANID.bscanid_done_reg\ : out STD_LOGIC;
    \Use_JTAG_BSCAN.tap_cnt_ok_reg_1\ : out STD_LOGIC;
    \Use_E2.BSCANE2_I_2\ : out STD_LOGIC;
    \Use_JTAG_BSCAN.mode_reg__0\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.tms_ok_reg\ : in STD_LOGIC;
    O : in STD_LOGIC;
    \Use_JTAG_BSCAN.tms_ok_reg_0\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.tap_cnt_ok\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.id_flag\ : in STD_LOGIC;
    \Internal_BSCANID.bscanid_sel\ : in STD_LOGIC;
    JTAG_TDO : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \Internal_BSCANID.bscanid_done\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MB_BSCANE2 : entity is "MB_BSCANE2";
end scu35_io_design_mdm_1_0_MB_BSCANE2;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MB_BSCANE2 is
  signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal SEL : STD_LOGIC;
  signal \^use_e2.bscane2_i_0\ : STD_LOGIC;
  signal \^use_e2.bscane2_i_1\ : STD_LOGIC;
  signal \Use_E2.BSCANE2_I_n_0\ : STD_LOGIC;
  signal \Use_E2.BSCANE2_I_n_1\ : STD_LOGIC;
  signal \Use_E2.BSCANE2_I_n_3\ : STD_LOGIC;
  signal \Use_E2.BSCANE2_I_n_9\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_10_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_11_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_12_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_5_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_6_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_7_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_8_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_9_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_reg_i_3_n_5\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_reg_i_3_n_6\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_reg_i_3_n_7\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tms_ok_i_2_n_0\ : STD_LOGIC;
  signal m_bscan_tdo : STD_LOGIC;
  signal tms : STD_LOGIC;
  signal \NLW_Use_JTAG_BSCAN.mode_reg_reg_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_Use_JTAG_BSCAN.mode_reg_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Internal_BSCANID.bscanid_done_i_1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \Internal_BSCANID.bscanid_sel_i_1\ : label is "soft_lutpair71";
  attribute box_type : string;
  attribute box_type of \Use_E2.BSCANE2_I\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[7]_i_1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bscanid[26]_i_1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.id_flag_i_1\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.mode_reg_i_1\ : label is "soft_lutpair68";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of \Use_JTAG_BSCAN.mode_reg_reg_i_3\ : label is 11;
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.tap_cnt[7]_i_1\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.tap_cnt_ok_i_1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.tms_ok_i_2\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.tms_reg_i_2\ : label is "soft_lutpair69";
begin
  CO(0) <= \^co\(0);
  \Use_E2.BSCANE2_I_0\ <= \^use_e2.bscane2_i_0\;
  \Use_E2.BSCANE2_I_1\ <= \^use_e2.bscane2_i_1\;
\Internal_BSCANID.bscanid_done_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \Use_E2.BSCANE2_I_n_9\,
      I1 => \Internal_BSCANID.bscanid_done\,
      O => \Use_E2.BSCANE2_I_2\
    );
\Internal_BSCANID.bscanid_sel_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F04"
    )
        port map (
      I0 => \Internal_BSCANID.bscanid_done\,
      I1 => SEL,
      I2 => \Use_E2.BSCANE2_I_n_9\,
      I3 => \Internal_BSCANID.bscanid_sel\,
      O => \Internal_BSCANID.bscanid_done_reg\
    );
\Use_E2.BSCANE2_I\: unisim.vcomponents.BSCANE2
    generic map(
      DISABLE_JTAG => "FALSE",
      JTAG_CHAIN => 2
    )
        port map (
      CAPTURE => \Use_E2.BSCANE2_I_n_0\,
      DRCK => \Use_E2.BSCANE2_I_n_1\,
      RESET => \^use_e2.bscane2_i_0\,
      RUNTEST => \Use_E2.BSCANE2_I_n_3\,
      SEL => SEL,
      SHIFT => \^use_e2.bscane2_i_1\,
      TCK => tck,
      TDI => I0,
      TDO => m_bscan_tdo,
      TMS => tms,
      UPDATE => \Use_E2.BSCANE2_I_n_9\
    );
\Use_E2.BSCANE2_I_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEAA02AA"
    )
        port map (
      I0 => JTAG_TDO,
      I1 => \Use_E2.BSCANE2_I_n_0\,
      I2 => \^use_e2.bscane2_i_1\,
      I3 => \Internal_BSCANID.bscanid_sel\,
      I4 => Q(0),
      O => m_bscan_tdo
    );
\Use_JTAG_BSCAN.bit_cnt[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D000"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.tms_ok_reg\,
      I1 => \^co\(0),
      I2 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I3 => \^use_e2.bscane2_i_1\,
      O => \Use_JTAG_BSCAN.tap_cnt_ok_reg_0\(0)
    );
\Use_JTAG_BSCAN.bscanid[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFDFDFFF"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.id_flag\,
      I1 => \^use_e2.bscane2_i_0\,
      I2 => \Internal_BSCANID.bscanid_sel\,
      I3 => \^use_e2.bscane2_i_1\,
      I4 => \Use_E2.BSCANE2_I_n_0\,
      O => \Use_JTAG_BSCAN.id_flag_reg\
    );
\Use_JTAG_BSCAN.id_flag_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A8"
    )
        port map (
      I0 => \Internal_BSCANID.bscanid_sel\,
      I1 => \^use_e2.bscane2_i_1\,
      I2 => \Use_E2.BSCANE2_I_n_0\,
      I3 => \^use_e2.bscane2_i_0\,
      O => \Internal_BSCANID.bscanid_sel_reg\
    );
\Use_JTAG_BSCAN.mode_reg_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF80"
    )
        port map (
      I0 => tms,
      I1 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I2 => \^use_e2.bscane2_i_1\,
      I3 => \Use_E2.BSCANE2_I_n_9\,
      I4 => \Use_E2.BSCANE2_I_n_0\,
      O => SR(0)
    );
\Use_JTAG_BSCAN.mode_reg_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(5),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(5),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(4),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(4),
      O => \Use_JTAG_BSCAN.mode_reg_i_10_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(3),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(3),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(2),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(2),
      O => \Use_JTAG_BSCAN.mode_reg_i_11_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(1),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(1),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(0),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(0),
      O => \Use_JTAG_BSCAN.mode_reg_i_12_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(7),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(7),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(6),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(6),
      O => \Use_JTAG_BSCAN.mode_reg_i_5_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(5),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(5),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(4),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(4),
      O => \Use_JTAG_BSCAN.mode_reg_i_6_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(3),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(3),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(2),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(2),
      O => \Use_JTAG_BSCAN.mode_reg_i_7_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(1),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(1),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(0),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(0),
      O => \Use_JTAG_BSCAN.mode_reg_i_8_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(7),
      I1 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(7),
      I2 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(6),
      I3 => \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(6),
      O => \Use_JTAG_BSCAN.mode_reg_i_9_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_reg_i_3\: unisim.vcomponents.CARRY8
     port map (
      CI => '0',
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_Use_JTAG_BSCAN.mode_reg_reg_i_3_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \^co\(0),
      CO(2) => \Use_JTAG_BSCAN.mode_reg_reg_i_3_n_5\,
      CO(1) => \Use_JTAG_BSCAN.mode_reg_reg_i_3_n_6\,
      CO(0) => \Use_JTAG_BSCAN.mode_reg_reg_i_3_n_7\,
      DI(7 downto 4) => B"0000",
      DI(3) => \Use_JTAG_BSCAN.mode_reg_i_5_n_0\,
      DI(2) => \Use_JTAG_BSCAN.mode_reg_i_6_n_0\,
      DI(1) => \Use_JTAG_BSCAN.mode_reg_i_7_n_0\,
      DI(0) => \Use_JTAG_BSCAN.mode_reg_i_8_n_0\,
      O(7 downto 0) => \NLW_Use_JTAG_BSCAN.mode_reg_reg_i_3_O_UNCONNECTED\(7 downto 0),
      S(7 downto 4) => B"0000",
      S(3) => \Use_JTAG_BSCAN.mode_reg_i_9_n_0\,
      S(2) => \Use_JTAG_BSCAN.mode_reg_i_10_n_0\,
      S(1) => \Use_JTAG_BSCAN.mode_reg_i_11_n_0\,
      S(0) => \Use_JTAG_BSCAN.mode_reg_i_12_n_0\
    );
\Use_JTAG_BSCAN.tap_cnt[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I1 => \^use_e2.bscane2_i_1\,
      I2 => \Use_E2.BSCANE2_I_n_9\,
      I3 => \Use_E2.BSCANE2_I_n_0\,
      O => E(0)
    );
\Use_JTAG_BSCAN.tap_cnt_ok_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I1 => SEL,
      I2 => \Use_E2.BSCANE2_I_n_9\,
      I3 => \^use_e2.bscane2_i_0\,
      O => \Use_JTAG_BSCAN.tap_cnt_ok_reg_1\
    );
\Use_JTAG_BSCAN.tms_ok_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFBFF07000400"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg__0\,
      I1 => \Use_JTAG_BSCAN.tms_ok_reg\,
      I2 => \^co\(0),
      I3 => \Use_JTAG_BSCAN.tms_ok_i_2_n_0\,
      I4 => O,
      I5 => \Use_JTAG_BSCAN.tms_ok_reg_0\,
      O => \Use_JTAG_BSCAN.mode_reg_reg\
    );
\Use_JTAG_BSCAN.tms_ok_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I1 => \^use_e2.bscane2_i_1\,
      O => \Use_JTAG_BSCAN.tms_ok_i_2_n_0\
    );
\Use_JTAG_BSCAN.tms_reg_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => \^co\(0),
      I1 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I2 => \^use_e2.bscane2_i_1\,
      I3 => \Use_JTAG_BSCAN.mode_reg__0\,
      O => \Use_JTAG_BSCAN.tap_cnt_ok_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MB_BUFG is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Test_Access_Port.update_unbuf\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MB_BUFG : entity is "MB_BUFG";
end scu35_io_design_mdm_1_0_MB_BUFG;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MB_BUFG is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "BUFG";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native\ : label is "VCC:CE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.BUFGCE
    generic map(
      CE_TYPE => "ASYNC",
      SIM_DEVICE => "SPARTAN_ULTRASCALE_PLUS"
    )
        port map (
      CE => '1',
      I => \Test_Access_Port.update_unbuf\,
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MB_BUFGCE_1 is
  port (
    \Use_JTAG_BSCAN.tck_int\ : out STD_LOGIC;
    tck : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MB_BUFGCE_1 : entity is "MB_BUFGCE_1";
end scu35_io_design_mdm_1_0_MB_BUFGCE_1;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MB_BUFGCE_1 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "BUFGCE_1";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native\ : label is "CE:CE0 I:I0 GND:S1,IGNORE0,CE1 VCC:S0,IGNORE1,I1";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.BUFGCTRL
    generic map(
      INIT_OUT => 1,
      PRESELECT_I0 => true,
      PRESELECT_I1 => false,
      SIM_DEVICE => "SPARTAN_ULTRASCALE_PLUS"
    )
        port map (
      CE0 => \Using_FPGA.Native_0\,
      CE1 => '0',
      I0 => tck,
      I1 => '1',
      IGNORE0 => '0',
      IGNORE1 => '1',
      O => \Use_JTAG_BSCAN.tck_int\,
      S0 => '1',
      S1 => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MB_BUFGCE_1_0 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Use_JTAG_BSCAN.tck_int\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MB_BUFGCE_1_0 : entity is "MB_BUFGCE_1";
end scu35_io_design_mdm_1_0_MB_BUFGCE_1_0;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MB_BUFGCE_1_0 is
  signal \Test_Access_Port.drck_ena\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "BUFGCE_1";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native\ : label is "CE:CE0 I:I0 GND:S1,IGNORE0,CE1 VCC:S0,IGNORE1,I1";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.BUFGCTRL
    generic map(
      INIT_OUT => 1,
      PRESELECT_I0 => true,
      PRESELECT_I1 => false,
      SIM_DEVICE => "SPARTAN_ULTRASCALE_PLUS"
    )
        port map (
      CE0 => \Test_Access_Port.drck_ena\,
      CE1 => '0',
      I0 => \Use_JTAG_BSCAN.tck_int\,
      I1 => '1',
      IGNORE0 => '0',
      IGNORE1 => '1',
      O => \Using_FPGA.Native_0\,
      S0 => '1',
      S1 => '0'
    );
\Using_FPGA.Native_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => \Using_FPGA.Native_2\,
      O => \Test_Access_Port.drck_ena\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MB_LUT1 is
  port (
    \Use_JTAG_BSCAN.bit_cnt_reg[2]\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    O : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \Use_JTAG_BSCAN.mode_reg_i_4_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    Dbg_Capture_0 : in STD_LOGIC;
    \Test_Access_Port.ir_reg[4]\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.tms_reg_reg\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.tms_reg_reg_0\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.tms_reg_reg_1\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.mode_reg_reg\ : in STD_LOGIC;
    \Use_JTAG_BSCAN.tap_cnt_ok\ : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Use_JTAG_BSCAN.mode_reg__0\ : in STD_LOGIC;
    I0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MB_LUT1 : entity is "MB_LUT1";
end scu35_io_design_mdm_1_0_MB_LUT1;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MB_LUT1 is
  signal \^use_jtag_bscan.bit_cnt_reg[2]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_13_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_14_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_15_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg_i_16_n_0\ : STD_LOGIC;
  signal \Using_FPGA.lut1_o\ : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of \Using_FPGA.lut1_o\ : signal is std.standard.true;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  O <= \Using_FPGA.lut1_o\;
  \Use_JTAG_BSCAN.bit_cnt_reg[2]\ <= \^use_jtag_bscan.bit_cnt_reg[2]\;
\Test_Access_Port.ir[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Using_FPGA.lut1_o\,
      I1 => \Test_Access_Port.ir_reg[4]\,
      O => \Using_FPGA.Native_1\(0)
    );
\Use_JTAG_BSCAN.mode_reg_i_13\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => Q(2),
      I1 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(2),
      I2 => Q(3),
      I3 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(3),
      O => \Use_JTAG_BSCAN.mode_reg_i_13_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => Q(0),
      I1 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(0),
      I2 => Q(1),
      I3 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(1),
      O => \Use_JTAG_BSCAN.mode_reg_i_14_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => Q(6),
      I1 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(6),
      I2 => Q(7),
      I3 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(7),
      O => \Use_JTAG_BSCAN.mode_reg_i_15_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6FF6"
    )
        port map (
      I0 => Q(4),
      I1 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(4),
      I2 => Q(5),
      I3 => \Use_JTAG_BSCAN.mode_reg_i_4_0\(5),
      O => \Use_JTAG_BSCAN.mode_reg_i_16_n_0\
    );
\Use_JTAG_BSCAN.mode_reg_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000080"
    )
        port map (
      I0 => \Using_FPGA.lut1_o\,
      I1 => \Use_JTAG_BSCAN.mode_reg_reg\,
      I2 => \Use_JTAG_BSCAN.tap_cnt_ok\,
      I3 => CO(0),
      I4 => \^use_jtag_bscan.bit_cnt_reg[2]\,
      I5 => \Use_JTAG_BSCAN.mode_reg__0\,
      O => \Using_FPGA.Native_3\
    );
\Use_JTAG_BSCAN.mode_reg_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.mode_reg_i_13_n_0\,
      I1 => \Use_JTAG_BSCAN.mode_reg_i_14_n_0\,
      I2 => \Use_JTAG_BSCAN.mode_reg_i_15_n_0\,
      I3 => \Use_JTAG_BSCAN.mode_reg_i_16_n_0\,
      O => \^use_jtag_bscan.bit_cnt_reg[2]\
    );
\Use_JTAG_BSCAN.tms_reg_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFF2000"
    )
        port map (
      I0 => \Using_FPGA.lut1_o\,
      I1 => \Use_JTAG_BSCAN.tms_reg_reg\,
      I2 => \Use_JTAG_BSCAN.tms_reg_reg_0\,
      I3 => \^use_jtag_bscan.bit_cnt_reg[2]\,
      I4 => \Use_JTAG_BSCAN.tms_reg_reg_1\,
      O => \Using_FPGA.Native_2\
    );
\Using_FPGA.Native\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => I0,
      O => \Using_FPGA.lut1_o\
    );
\dtmcs[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Using_FPGA.lut1_o\,
      I1 => Dbg_Capture_0,
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_JTAG_CONTROL is
  port (
    \Using_FPGA.Native\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Test_Access_Port.shift_dtm_reg_0\ : out STD_LOGIC;
    dmcontrol_ndmreset_reg_0 : out STD_LOGIC;
    Dbg_Rst_0 : out STD_LOGIC;
    \Test_Access_Port.capture_dtm_reg_0\ : out STD_LOGIC;
    JTAG_TDO : out STD_LOGIC;
    \FSM_onehot_Test_Access_Port.state_reg[5]_0\ : out STD_LOGIC;
    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
    \Use_JTAG_BSCAN.tck_int\ : in STD_LOGIC;
    O : in STD_LOGIC;
    \dtmcs_reg[31]_0\ : in STD_LOGIC;
    jtag_tms : in STD_LOGIC;
    Dbg_TDO_0 : in STD_LOGIC;
    \Test_Access_Port.ir_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_JTAG_CONTROL : entity is "JTAG_CONTROL";
end scu35_io_design_mdm_1_0_JTAG_CONTROL;

architecture STRUCTURE of scu35_io_design_mdm_1_0_JTAG_CONTROL is
  signal \^dbg_rst_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[12]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[13]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[14]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[15]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[7]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[8]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state[9]_i_1_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_test_access_port.state_reg[5]_0\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[13]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[14]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[15]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[7]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[8]\ : STD_LOGIC;
  signal \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\ : STD_LOGIC;
  signal TDO_bypass : STD_LOGIC;
  signal TDO_dtm : STD_LOGIC;
  signal TDO_i_10_n_0 : STD_LOGIC;
  signal TDO_i_11_n_0 : STD_LOGIC;
  signal TDO_i_12_n_0 : STD_LOGIC;
  signal TDO_i_2_n_0 : STD_LOGIC;
  signal TDO_i_3_n_0 : STD_LOGIC;
  signal TDO_i_4_n_0 : STD_LOGIC;
  signal TDO_i_5_n_0 : STD_LOGIC;
  signal TDO_i_6_n_0 : STD_LOGIC;
  signal TDO_i_7_n_0 : STD_LOGIC;
  signal TDO_i_8_n_0 : STD_LOGIC;
  signal TDO_i_9_n_0 : STD_LOGIC;
  signal TDO_ir : STD_LOGIC;
  signal \^test_access_port.capture_dtm_reg_0\ : STD_LOGIC;
  signal \Test_Access_Port.capture_tck_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.capture_tck_reg_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \Test_Access_Port.idcode[0]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[10]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[11]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[12]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[13]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[14]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[15]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[1]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[2]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[3]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[4]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[5]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[6]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[7]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[8]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode[9]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.idcode_3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \Test_Access_Port.ir\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \Test_Access_Port.ir[4]_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.ir_reg_n_0_[1]\ : STD_LOGIC;
  signal \Test_Access_Port.ir_reg_n_0_[2]\ : STD_LOGIC;
  signal \Test_Access_Port.ir_reg_n_0_[3]\ : STD_LOGIC;
  signal \Test_Access_Port.ir_reg_n_0_[4]\ : STD_LOGIC;
  signal \Test_Access_Port.sel_dmi_i_1_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.sel_dmi_reg_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.sel_dtmcs_reg_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.sel_idcode_i_2_n_0\ : STD_LOGIC;
  signal \^test_access_port.shift_dtm_reg_0\ : STD_LOGIC;
  signal \Test_Access_Port.shift_tck\ : STD_LOGIC;
  signal \Test_Access_Port.shift_tck_reg_n_0\ : STD_LOGIC;
  signal \Test_Access_Port.update_unbuf\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal command : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \command[0]_i_1_n_0\ : STD_LOGIC;
  signal \command[1]_i_1_n_0\ : STD_LOGIC;
  signal \command[2]_i_1_n_0\ : STD_LOGIC;
  signal \command[3]_i_1_n_0\ : STD_LOGIC;
  signal \command[4]_i_1_n_0\ : STD_LOGIC;
  signal \command[5]_i_1_n_0\ : STD_LOGIC;
  signal \command[6]_i_1_n_0\ : STD_LOGIC;
  signal \command[7]_i_1_n_0\ : STD_LOGIC;
  signal dmcontrol : STD_LOGIC_VECTOR ( 0 to 0 );
  signal dmcontrol_hartreset : STD_LOGIC;
  signal dmcontrol_hartreset0 : STD_LOGIC;
  signal dmcontrol_ndmreset : STD_LOGIC;
  signal dmcontrol_ndmreset_i_3_n_0 : STD_LOGIC;
  signal \^dmcontrol_ndmreset_reg_0\ : STD_LOGIC;
  signal dmcontrol_read : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \dmcontrol_read[0]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[10]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[11]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[12]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[13]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[14]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[15]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[16]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[17]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[18]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[19]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[1]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[20]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[21]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[22]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[23]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[24]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[25]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[26]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[27]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[28]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[29]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[2]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[30]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[31]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[3]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[4]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[5]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[6]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[7]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[8]_i_1_n_0\ : STD_LOGIC;
  signal \dmcontrol_read[9]_i_1_n_0\ : STD_LOGIC;
  signal dmcontrol_read_2 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \dmi_reg[32]_srl2_n_0\ : STD_LOGIC;
  signal \dmi_reg[4]_srl27_n_0\ : STD_LOGIC;
  signal \dmi_reg_n_0_[0]\ : STD_LOGIC;
  signal \dmi_reg_n_0_[1]\ : STD_LOGIC;
  signal \dmi_reg_n_0_[2]\ : STD_LOGIC;
  signal dmihardreset : STD_LOGIC;
  signal dmihardreset_reg_n_0 : STD_LOGIC;
  signal dmireset : STD_LOGIC;
  signal dmireset_reg_n_0 : STD_LOGIC;
  signal dmistat15_out : STD_LOGIC;
  signal \dmistat[0]_i_1_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_10_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_11_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_12_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_13_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_14_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_1_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_2_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_3_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_4_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_5_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_6_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_7_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_8_n_0\ : STD_LOGIC;
  signal \dmistat[1]_i_9_n_0\ : STD_LOGIC;
  signal dmistat_current : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \dmistat_current[0]_i_1_n_0\ : STD_LOGIC;
  signal \dmistat_current[1]_i_2_n_0\ : STD_LOGIC;
  signal \dmistat_current_reg_n_0_[0]\ : STD_LOGIC;
  signal \dmistat_current_reg_n_0_[1]\ : STD_LOGIC;
  signal \dmistat_shift_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \dmistat_shift_count[1]_i_1_n_0\ : STD_LOGIC;
  signal \dmistat_shift_count[1]_i_2_n_0\ : STD_LOGIC;
  signal \dmistat_shift_count_reg_n_0_[0]\ : STD_LOGIC;
  signal \dmistat_shift_count_reg_n_0_[1]\ : STD_LOGIC;
  signal \dmstatus_shift_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \dmstatus_shift_count[1]_i_1_n_0\ : STD_LOGIC;
  signal dmstatus_shift_count_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \dtmcs[0]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[10]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[11]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[12]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[13]_i_2_n_0\ : STD_LOGIC;
  signal \dtmcs[16]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[17]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[18]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[19]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[1]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[20]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[21]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[22]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[23]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[24]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[25]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[26]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[27]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[28]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[29]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[2]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[30]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[3]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[4]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[5]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[6]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[7]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[8]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs[9]_i_1_n_0\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[0]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[10]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[11]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[12]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[13]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[16]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[18]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[19]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[1]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[20]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[21]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[22]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[23]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[24]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[25]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[26]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[27]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[28]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[29]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[2]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[30]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[31]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[3]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[4]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[5]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[6]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[7]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[8]\ : STD_LOGIC;
  signal \dtmcs_reg_n_0_[9]\ : STD_LOGIC;
  signal haltsum0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \haltsum0[0]_i_1_n_0\ : STD_LOGIC;
  signal haltsum0_read : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal \haltsum0_read[0]_i_1_n_0\ : STD_LOGIC;
  signal \haltsum0_read[1]_i_1_n_0\ : STD_LOGIC;
  signal \haltsum0_read[2]_i_2_n_0\ : STD_LOGIC;
  signal \haltsum0_read_reg_n_0_[0]\ : STD_LOGIC;
  signal idle_reg : STD_LOGIC;
  signal idle_reg_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal p_0_in0_in : STD_LOGIC;
  signal p_0_in2_in : STD_LOGIC;
  signal p_0_in3_in : STD_LOGIC;
  signal p_0_in_4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 10 );
  signal sel_bypass : STD_LOGIC;
  signal sel_bypass_1 : STD_LOGIC;
  signal sel_dmi : STD_LOGIC;
  signal sel_dtmcs : STD_LOGIC;
  signal sel_idcode : STD_LOGIC;
  signal sel_idcode_0 : STD_LOGIC;
  signal sel_ir : STD_LOGIC;
  signal \NLW_dmi_reg[4]_srl27_Q31_UNCONNECTED\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[0]_INST_0\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[1]_INST_0\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[2]_INST_0\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[3]_INST_0\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[4]_INST_0\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[5]_INST_0\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[6]_INST_0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \Dbg_Reg_En_0[7]_INST_0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[0]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[12]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[13]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[14]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[15]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[1]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[2]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[3]_i_1\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[4]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[5]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[6]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[7]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[8]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \FSM_onehot_Test_Access_Port.state[9]_i_1\ : label is "soft_lutpair15";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[0]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[12]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[13]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[14]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[15]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[1]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[2]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[3]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[4]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[5]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[6]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[7]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[8]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_Test_Access_Port.state_reg[9]\ : label is "shift_dr:0000100000000000,capture_dr:0000010000000000,pause_ir:0000000010000000,select_dr:0000000000000100,exit1_ir:0000000001000000,shift_ir:0000000000100000,capture_ir:0000000000010000,idle:0000000000000010,tl_reset:0000000000000001,exit2_dr:0100000000000000,select_ir:0000000000001000,pause_dr:0010000000000000,update_dr:1000000000000000,update_ir:0000001000000000,exit2_ir:0000000100000000,exit1_dr:0001000000000000";
  attribute SOFT_HLUTNM of TDO_i_6 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of TDO_i_8 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \Test_Access_Port.capture_tck_i_1\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[0]_i_1\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[10]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[11]_i_1\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[12]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[13]_i_1\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[14]_i_1\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[15]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[1]_i_1\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[2]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[3]_i_1\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[4]_i_1\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[5]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[6]_i_1\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[7]_i_1\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[8]_i_1\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \Test_Access_Port.idcode[9]_i_1\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \Test_Access_Port.ir[0]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \Test_Access_Port.ir[2]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \Test_Access_Port.ir[3]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \Test_Access_Port.sel_idcode_i_2\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \Test_Access_Port.shift_tck_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \command[0]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \command[1]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \command[2]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \command[3]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \command[4]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \command[5]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \command[6]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \command[7]_i_1\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of dmcontrol_hartreset_i_1 : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of dmcontrol_ndmreset_i_2 : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \dmcontrol_read[0]_i_1\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \dmcontrol_read[10]_i_1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \dmcontrol_read[11]_i_1\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \dmcontrol_read[12]_i_1\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \dmcontrol_read[13]_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \dmcontrol_read[14]_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \dmcontrol_read[15]_i_1\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \dmcontrol_read[16]_i_1\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \dmcontrol_read[17]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \dmcontrol_read[18]_i_1\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \dmcontrol_read[19]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \dmcontrol_read[1]_i_1\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \dmcontrol_read[20]_i_1\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \dmcontrol_read[21]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \dmcontrol_read[22]_i_1\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \dmcontrol_read[23]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \dmcontrol_read[24]_i_1\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \dmcontrol_read[25]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \dmcontrol_read[26]_i_1\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \dmcontrol_read[27]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \dmcontrol_read[28]_i_1\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \dmcontrol_read[29]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \dmcontrol_read[2]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \dmcontrol_read[30]_i_1\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \dmcontrol_read[31]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \dmcontrol_read[3]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \dmcontrol_read[4]_i_1\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \dmcontrol_read[5]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \dmcontrol_read[6]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \dmcontrol_read[7]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \dmcontrol_read[8]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \dmcontrol_read[9]_i_1\ : label is "soft_lutpair49";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \dmi_reg[32]_srl2\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/dmi_reg ";
  attribute srl_name : string;
  attribute srl_name of \dmi_reg[32]_srl2\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/dmi_reg[32]_srl2 ";
  attribute srl_bus_name of \dmi_reg[4]_srl27\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/dmi_reg ";
  attribute srl_name of \dmi_reg[4]_srl27\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/dmi_reg[4]_srl27 ";
  attribute SOFT_HLUTNM of dmihardreset_i_1 : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of dmireset_i_1 : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \dmistat[0]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \dmistat[1]_i_10\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \dmistat[1]_i_14\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \dmistat[1]_i_3\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \dmistat_current[0]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \dmistat_current[1]_i_2\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \dmistat_shift_count[0]_i_1\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \dmistat_shift_count[1]_i_2\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \dmstatus_shift_count[0]_i_1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \dmstatus_shift_count[1]_i_1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \dmstatus_shift_count[2]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \dmstatus_shift_count[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \dtmcs[0]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \dtmcs[10]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \dtmcs[11]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \dtmcs[12]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \dtmcs[13]_i_2\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \dtmcs[16]_i_1\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \dtmcs[17]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \dtmcs[18]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \dtmcs[19]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \dtmcs[1]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \dtmcs[20]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \dtmcs[21]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \dtmcs[22]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \dtmcs[23]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \dtmcs[24]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \dtmcs[25]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \dtmcs[26]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \dtmcs[27]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \dtmcs[28]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \dtmcs[29]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \dtmcs[2]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \dtmcs[30]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \dtmcs[3]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \dtmcs[4]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \dtmcs[5]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \dtmcs[6]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \dtmcs[7]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \dtmcs[8]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \dtmcs[9]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \haltsum0_read[0]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \haltsum0_read[1]_i_1\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \haltsum0_read[2]_i_2\ : label is "soft_lutpair45";
begin
  Dbg_Rst_0 <= \^dbg_rst_0\;
  \FSM_onehot_Test_Access_Port.state_reg[5]_0\ <= \^fsm_onehot_test_access_port.state_reg[5]_0\;
  \Test_Access_Port.capture_dtm_reg_0\ <= \^test_access_port.capture_dtm_reg_0\;
  \Test_Access_Port.shift_dtm_reg_0\ <= \^test_access_port.shift_dtm_reg_0\;
  \Using_FPGA.Native\ <= \^using_fpga.native\;
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  dmcontrol_ndmreset_reg_0 <= \^dmcontrol_ndmreset_reg_0\;
\Dbg_Reg_En_0[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(7),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(7),
      O => Dbg_Reg_En_0(0)
    );
\Dbg_Reg_En_0[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(6),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(6),
      O => Dbg_Reg_En_0(1)
    );
\Dbg_Reg_En_0[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(5),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(5),
      O => Dbg_Reg_En_0(2)
    );
\Dbg_Reg_En_0[3]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(4),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(4),
      O => Dbg_Reg_En_0(3)
    );
\Dbg_Reg_En_0[4]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(3),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(3),
      O => Dbg_Reg_En_0(4)
    );
\Dbg_Reg_En_0[5]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(2),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(2),
      O => Dbg_Reg_En_0(5)
    );
\Dbg_Reg_En_0[6]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(1),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(1),
      O => Dbg_Reg_En_0(6)
    );
\Dbg_Reg_En_0[7]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => command(0),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => p_0_in_4(0),
      O => Dbg_Reg_En_0(7)
    );
\FSM_onehot_Test_Access_Port.state[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[0]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[0]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \Test_Access_Port.shift_tck_reg_n_0\,
      I1 => \Test_Access_Port.capture_tck_reg_n_0\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[12]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[12]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[13]\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[13]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => jtag_tms,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[13]\,
      O => \FSM_onehot_Test_Access_Port.state[14]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[14]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[12]\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[15]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"33333332"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[0]\,
      I1 => jtag_tms,
      I2 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[15]\,
      I3 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I4 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[1]\,
      O => \FSM_onehot_Test_Access_Port.state[1]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE00"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[1]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I2 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[15]\,
      I3 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[2]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => jtag_tms,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[2]\,
      O => \FSM_onehot_Test_Access_Port.state[3]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      I1 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[4]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0E"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[4]\,
      I1 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      I2 => jtag_tms,
      I3 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[8]\,
      O => \FSM_onehot_Test_Access_Port.state[5]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[4]\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[6]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[6]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[7]\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[7]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => jtag_tms,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[7]\,
      O => \FSM_onehot_Test_Access_Port.state[8]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[6]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[8]\,
      I2 => jtag_tms,
      O => \FSM_onehot_Test_Access_Port.state[9]_i_1_n_0\
    );
\FSM_onehot_Test_Access_Port.state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[0]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[0]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[12]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[12]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[13]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[13]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[14]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[14]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[15]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[15]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[1]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[2]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[2]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[3]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[4]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[4]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[5]_i_1_n_0\,
      Q => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[6]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[6]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[7]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[7]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[8]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[8]\,
      R => '0'
    );
\FSM_onehot_Test_Access_Port.state_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state[9]_i_1_n_0\,
      Q => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      R => '0'
    );
TDO_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEAEAEA"
    )
        port map (
      I0 => TDO_i_2_n_0,
      I1 => TDO_i_3_n_0,
      I2 => TDO_i_4_n_0,
      I3 => TDO_ir,
      I4 => sel_ir,
      I5 => TDO_i_5_n_0,
      O => TDO_dtm
    );
TDO_i_10: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8FAF8AA"
    )
        port map (
      I0 => command(5),
      I1 => command(2),
      I2 => command(6),
      I3 => command(3),
      I4 => command(4),
      O => TDO_i_10_n_0
    );
TDO_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000004"
    )
        port map (
      I0 => command(2),
      I1 => command(3),
      I2 => command(1),
      I3 => command(0),
      I4 => command(5),
      I5 => command(7),
      O => TDO_i_11_n_0
    );
TDO_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"888F"
    )
        port map (
      I0 => command(2),
      I1 => command(1),
      I2 => command(6),
      I3 => command(4),
      O => TDO_i_12_n_0
    );
TDO_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEAEAEAEAEAEAEA"
    )
        port map (
      I0 => TDO_i_6_n_0,
      I1 => TDO_i_7_n_0,
      I2 => TDO_i_8_n_0,
      I3 => dmcontrol_read(0),
      I4 => \dmistat[1]_i_10_n_0\,
      I5 => \dmistat[1]_i_9_n_0\,
      O => TDO_i_2_n_0
    );
TDO_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      I1 => sel_ir,
      I2 => sel_bypass,
      I3 => sel_idcode,
      I4 => Dbg_TDO_0,
      O => TDO_i_3_n_0
    );
TDO_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFFFE"
    )
        port map (
      I0 => TDO_i_9_n_0,
      I1 => TDO_i_10_n_0,
      I2 => TDO_i_11_n_0,
      I3 => TDO_i_12_n_0,
      I4 => \dmistat[1]_i_13_n_0\,
      I5 => \dmistat[1]_i_14_n_0\,
      O => TDO_i_4_n_0
    );
TDO_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000080"
    )
        port map (
      I0 => \dmistat[1]_i_9_n_0\,
      I1 => \dmistat[1]_i_14_n_0\,
      I2 => \^dmcontrol_ndmreset_reg_0\,
      I3 => command(1),
      I4 => \dmistat[1]_i_13_n_0\,
      I5 => \dmistat[1]_i_6_n_0\,
      O => TDO_i_5_n_0
    );
TDO_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B080808"
    )
        port map (
      I0 => TDO_bypass,
      I1 => sel_bypass,
      I2 => sel_ir,
      I3 => \Test_Access_Port.idcode\(0),
      I4 => sel_idcode,
      O => TDO_i_6_n_0
    );
TDO_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      I1 => \dtmcs_reg_n_0_[0]\,
      O => TDO_i_7_n_0
    );
TDO_i_8: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => sel_ir,
      I1 => sel_bypass,
      I2 => sel_idcode,
      O => TDO_i_8_n_0
    );
TDO_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEF0FEFEEEE00"
    )
        port map (
      I0 => command(5),
      I1 => command(6),
      I2 => command(3),
      I3 => command(1),
      I4 => command(0),
      I5 => command(2),
      O => TDO_i_9_n_0
    );
TDO_reg: unisim.vcomponents.FDRE
     port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => TDO_dtm,
      Q => JTAG_TDO,
      R => '0'
    );
\Test_Access_Port.BUFG_DRCK\: entity work.scu35_io_design_mdm_1_0_MB_BUFGCE_1_0
     port map (
      \Use_JTAG_BSCAN.tck_int\ => \Use_JTAG_BSCAN.tck_int\,
      \Using_FPGA.Native_0\ => \^using_fpga.native\,
      \Using_FPGA.Native_1\ => \Test_Access_Port.capture_tck_reg_n_0\,
      \Using_FPGA.Native_2\ => \Test_Access_Port.shift_tck_reg_n_0\
    );
\Test_Access_Port.BUFG_UPDATE\: entity work.scu35_io_design_mdm_1_0_MB_BUFG
     port map (
      \Test_Access_Port.update_unbuf\ => \Test_Access_Port.update_unbuf\,
      \Using_FPGA.Native_0\ => \^using_fpga.native_0\
    );
\Test_Access_Port.TDO_bypass_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => O,
      Q => TDO_bypass,
      R => '0'
    );
\Test_Access_Port.capture_dtm_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \Test_Access_Port.capture_tck_reg_n_0\,
      Q => \^test_access_port.capture_dtm_reg_0\,
      R => '0'
    );
\Test_Access_Port.capture_tck_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[2]\,
      I1 => jtag_tms,
      O => \Test_Access_Port.capture_tck_i_1_n_0\
    );
\Test_Access_Port.capture_tck_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \Test_Access_Port.capture_tck_i_1_n_0\,
      Q => \Test_Access_Port.capture_tck_reg_n_0\,
      R => '0'
    );
\Test_Access_Port.idcode[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.idcode\(1),
      O => \Test_Access_Port.idcode[0]_i_1_n_0\
    );
\Test_Access_Port.idcode[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(11),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[10]_i_1_n_0\
    );
\Test_Access_Port.idcode[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(12),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[11]_i_1_n_0\
    );
\Test_Access_Port.idcode[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(13),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[12]_i_1_n_0\
    );
\Test_Access_Port.idcode[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(14),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[13]_i_1_n_0\
    );
\Test_Access_Port.idcode[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(15),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[14]_i_1_n_0\
    );
\Test_Access_Port.idcode[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[16]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[15]_i_1_n_0\
    );
\Test_Access_Port.idcode[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.idcode\(2),
      O => \Test_Access_Port.idcode[1]_i_1_n_0\
    );
\Test_Access_Port.idcode[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(3),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[2]_i_1_n_0\
    );
\Test_Access_Port.idcode[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(4),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[3]_i_1_n_0\
    );
\Test_Access_Port.idcode[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.idcode\(5),
      O => \Test_Access_Port.idcode[4]_i_1_n_0\
    );
\Test_Access_Port.idcode[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(6),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[5]_i_1_n_0\
    );
\Test_Access_Port.idcode[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(7),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[6]_i_1_n_0\
    );
\Test_Access_Port.idcode[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.idcode\(8),
      O => \Test_Access_Port.idcode[7]_i_1_n_0\
    );
\Test_Access_Port.idcode[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(9),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[8]_i_1_n_0\
    );
\Test_Access_Port.idcode[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \Test_Access_Port.idcode\(10),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode[9]_i_1_n_0\
    );
\Test_Access_Port.idcode_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[0]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(0),
      R => '0'
    );
\Test_Access_Port.idcode_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[10]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(10),
      R => '0'
    );
\Test_Access_Port.idcode_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[11]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(11),
      R => '0'
    );
\Test_Access_Port.idcode_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[12]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(12),
      R => '0'
    );
\Test_Access_Port.idcode_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[13]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(13),
      R => '0'
    );
\Test_Access_Port.idcode_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[14]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(14),
      R => '0'
    );
\Test_Access_Port.idcode_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[15]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(15),
      R => '0'
    );
\Test_Access_Port.idcode_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[1]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(1),
      R => '0'
    );
\Test_Access_Port.idcode_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[2]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(2),
      R => '0'
    );
\Test_Access_Port.idcode_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[3]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(3),
      R => '0'
    );
\Test_Access_Port.idcode_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[4]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(4),
      R => '0'
    );
\Test_Access_Port.idcode_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[5]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(5),
      R => '0'
    );
\Test_Access_Port.idcode_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[6]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(6),
      R => '0'
    );
\Test_Access_Port.idcode_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[7]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(7),
      R => '0'
    );
\Test_Access_Port.idcode_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[8]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(8),
      R => '0'
    );
\Test_Access_Port.idcode_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \Test_Access_Port.idcode[9]_i_1_n_0\,
      Q => \Test_Access_Port.idcode\(9),
      R => '0'
    );
\Test_Access_Port.ir[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      I1 => \Test_Access_Port.ir_reg_n_0_[1]\,
      I2 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      O => \Test_Access_Port.ir\(0)
    );
\Test_Access_Port.ir[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      I1 => \Test_Access_Port.ir_reg_n_0_[2]\,
      O => \Test_Access_Port.ir\(1)
    );
\Test_Access_Port.ir[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      I1 => \Test_Access_Port.ir_reg_n_0_[3]\,
      O => \Test_Access_Port.ir\(2)
    );
\Test_Access_Port.ir[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      I1 => \Test_Access_Port.ir_reg_n_0_[4]\,
      O => \Test_Access_Port.ir\(3)
    );
\Test_Access_Port.ir[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      I1 => jtag_tms,
      I2 => \^fsm_onehot_test_access_port.state_reg[5]_0\,
      O => \Test_Access_Port.ir[4]_i_1_n_0\
    );
\Test_Access_Port.ir_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.ir[4]_i_1_n_0\,
      D => \Test_Access_Port.ir\(0),
      Q => TDO_ir,
      R => '0'
    );
\Test_Access_Port.ir_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.ir[4]_i_1_n_0\,
      D => \Test_Access_Port.ir\(1),
      Q => \Test_Access_Port.ir_reg_n_0_[1]\,
      R => '0'
    );
\Test_Access_Port.ir_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.ir[4]_i_1_n_0\,
      D => \Test_Access_Port.ir\(2),
      Q => \Test_Access_Port.ir_reg_n_0_[2]\,
      R => '0'
    );
\Test_Access_Port.ir_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.ir[4]_i_1_n_0\,
      D => \Test_Access_Port.ir\(3),
      Q => \Test_Access_Port.ir_reg_n_0_[3]\,
      R => '0'
    );
\Test_Access_Port.ir_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.ir[4]_i_1_n_0\,
      D => \Test_Access_Port.ir_reg[4]_0\(0),
      Q => \Test_Access_Port.ir_reg_n_0_[4]\,
      R => '0'
    );
\Test_Access_Port.sel_bypass_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE00FE00FE00FF00"
    )
        port map (
      I0 => \Test_Access_Port.ir_reg_n_0_[3]\,
      I1 => \Test_Access_Port.ir_reg_n_0_[2]\,
      I2 => \Test_Access_Port.ir_reg_n_0_[1]\,
      I3 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I4 => TDO_ir,
      I5 => \Test_Access_Port.ir_reg_n_0_[4]\,
      O => sel_bypass_1
    );
\Test_Access_Port.sel_bypass_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.sel_dmi_i_1_n_0\,
      D => sel_bypass_1,
      Q => sel_bypass,
      R => '0'
    );
\Test_Access_Port.sel_dmi_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAA"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I1 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      I2 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[2]\,
      I3 => jtag_tms,
      O => \Test_Access_Port.sel_dmi_i_1_n_0\
    );
\Test_Access_Port.sel_dmi_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I1 => TDO_ir,
      I2 => \Test_Access_Port.ir_reg_n_0_[4]\,
      I3 => \Test_Access_Port.ir_reg_n_0_[1]\,
      I4 => \Test_Access_Port.ir_reg_n_0_[2]\,
      I5 => \Test_Access_Port.ir_reg_n_0_[3]\,
      O => sel_dmi
    );
\Test_Access_Port.sel_dmi_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.sel_dmi_i_1_n_0\,
      D => sel_dmi,
      Q => \Test_Access_Port.sel_dmi_reg_n_0\,
      R => '0'
    );
\Test_Access_Port.sel_dtmcs_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I1 => \Test_Access_Port.ir_reg_n_0_[4]\,
      I2 => TDO_ir,
      I3 => \Test_Access_Port.ir_reg_n_0_[1]\,
      I4 => \Test_Access_Port.ir_reg_n_0_[2]\,
      I5 => \Test_Access_Port.ir_reg_n_0_[3]\,
      O => sel_dtmcs
    );
\Test_Access_Port.sel_dtmcs_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.sel_dmi_i_1_n_0\,
      D => sel_dtmcs,
      Q => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      R => '0'
    );
\Test_Access_Port.sel_idcode_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF100010001000"
    )
        port map (
      I0 => \Test_Access_Port.sel_idcode_i_2_n_0\,
      I1 => \Test_Access_Port.ir_reg_n_0_[4]\,
      I2 => TDO_ir,
      I3 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[9]\,
      I4 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[3]\,
      I5 => jtag_tms,
      O => sel_idcode_0
    );
\Test_Access_Port.sel_idcode_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \Test_Access_Port.ir_reg_n_0_[3]\,
      I1 => \Test_Access_Port.ir_reg_n_0_[2]\,
      I2 => \Test_Access_Port.ir_reg_n_0_[1]\,
      O => \Test_Access_Port.sel_idcode_i_2_n_0\
    );
\Test_Access_Port.sel_idcode_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.sel_dmi_i_1_n_0\,
      D => sel_idcode_0,
      Q => sel_idcode,
      R => '0'
    );
\Test_Access_Port.sel_ir_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => \Test_Access_Port.sel_dmi_i_1_n_0\,
      D => \FSM_onehot_Test_Access_Port.state[3]_i_1_n_0\,
      Q => sel_ir,
      R => '0'
    );
\Test_Access_Port.shift_dtm_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \Test_Access_Port.shift_tck_reg_n_0\,
      Q => \^test_access_port.shift_dtm_reg_0\,
      R => '0'
    );
\Test_Access_Port.shift_tck_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00FE"
    )
        port map (
      I0 => \FSM_onehot_Test_Access_Port.state_reg_n_0_[14]\,
      I1 => \Test_Access_Port.capture_tck_reg_n_0\,
      I2 => \Test_Access_Port.shift_tck_reg_n_0\,
      I3 => jtag_tms,
      O => \Test_Access_Port.shift_tck\
    );
\Test_Access_Port.shift_tck_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \Test_Access_Port.shift_tck\,
      Q => \Test_Access_Port.shift_tck_reg_n_0\,
      R => '0'
    );
\Test_Access_Port.update_unbuf_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \Use_JTAG_BSCAN.tck_int\,
      CE => '1',
      D => \FSM_onehot_Test_Access_Port.state_reg_n_0_[15]\,
      Q => \Test_Access_Port.update_unbuf\,
      R => '0'
    );
\command[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(0),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[0]_i_1_n_0\
    );
\command[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(1),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[1]_i_1_n_0\
    );
\command[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(2),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[2]_i_1_n_0\
    );
\command[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(3),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[3]_i_1_n_0\
    );
\command[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(4),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[4]_i_1_n_0\
    );
\command[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(5),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[5]_i_1_n_0\
    );
\command[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(6),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[6]_i_1_n_0\
    );
\command[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in_4(7),
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => \command[7]_i_1_n_0\
    );
\command_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[0]_i_1_n_0\,
      Q => command(0),
      R => '0'
    );
\command_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[1]_i_1_n_0\,
      Q => command(1),
      R => '0'
    );
\command_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[2]_i_1_n_0\,
      Q => command(2),
      R => '0'
    );
\command_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[3]_i_1_n_0\,
      Q => command(3),
      R => '0'
    );
\command_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[4]_i_1_n_0\,
      Q => command(4),
      R => '0'
    );
\command_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[5]_i_1_n_0\,
      Q => command(5),
      R => '0'
    );
\command_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[6]_i_1_n_0\,
      Q => command(6),
      R => '0'
    );
\command_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => \command[7]_i_1_n_0\,
      Q => command(7),
      R => '0'
    );
dmcontrol_dmactive_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => dmcontrol_hartreset0,
      D => \dmi_reg_n_0_[2]\,
      Q => dmcontrol(0),
      R => '0'
    );
dmcontrol_hartreset_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => dmcontrol(0),
      I1 => p_0_in2_in,
      O => dmcontrol_hartreset
    );
dmcontrol_hartreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => dmcontrol_hartreset0,
      D => dmcontrol_hartreset,
      Q => \^dbg_rst_0\,
      R => '0'
    );
dmcontrol_ndmreset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => p_0_in_4(1),
      I1 => p_0_in_4(2),
      I2 => p_0_in_4(0),
      I3 => \dmi_reg_n_0_[1]\,
      I4 => \dmi_reg_n_0_[0]\,
      I5 => dmcontrol_ndmreset_i_3_n_0,
      O => dmcontrol_hartreset0
    );
dmcontrol_ndmreset_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => dmcontrol(0),
      I1 => p_0_in3_in,
      O => dmcontrol_ndmreset
    );
dmcontrol_ndmreset_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => p_0_in_4(5),
      I1 => p_0_in_4(6),
      I2 => p_0_in_4(4),
      I3 => p_0_in_4(3),
      I4 => p_0_in_4(7),
      I5 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => dmcontrol_ndmreset_i_3_n_0
    );
dmcontrol_ndmreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native_0\,
      CE => dmcontrol_hartreset0,
      D => dmcontrol_ndmreset,
      Q => \^dmcontrol_ndmreset_reg_0\,
      R => '0'
    );
\dmcontrol_read[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(1),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[0]_i_1_n_0\
    );
\dmcontrol_read[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(11),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[10]_i_1_n_0\
    );
\dmcontrol_read[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(12),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[11]_i_1_n_0\
    );
\dmcontrol_read[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(13),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[12]_i_1_n_0\
    );
\dmcontrol_read[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(14),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[13]_i_1_n_0\
    );
\dmcontrol_read[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(15),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[14]_i_1_n_0\
    );
\dmcontrol_read[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(16),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[15]_i_1_n_0\
    );
\dmcontrol_read[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(17),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[16]_i_1_n_0\
    );
\dmcontrol_read[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(18),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[17]_i_1_n_0\
    );
\dmcontrol_read[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(19),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[18]_i_1_n_0\
    );
\dmcontrol_read[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(20),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[19]_i_1_n_0\
    );
\dmcontrol_read[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(2),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[1]_i_1_n_0\
    );
\dmcontrol_read[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(21),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[20]_i_1_n_0\
    );
\dmcontrol_read[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(22),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[21]_i_1_n_0\
    );
\dmcontrol_read[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(23),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[22]_i_1_n_0\
    );
\dmcontrol_read[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(24),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[23]_i_1_n_0\
    );
\dmcontrol_read[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(25),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[24]_i_1_n_0\
    );
\dmcontrol_read[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(26),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[25]_i_1_n_0\
    );
\dmcontrol_read[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(27),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[26]_i_1_n_0\
    );
\dmcontrol_read[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(28),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[27]_i_1_n_0\
    );
\dmcontrol_read[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(29),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[28]_i_1_n_0\
    );
\dmcontrol_read[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(30),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[29]_i_1_n_0\
    );
\dmcontrol_read[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => dmcontrol(0),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      I2 => dmcontrol_read(3),
      O => \dmcontrol_read[2]_i_1_n_0\
    );
\dmcontrol_read[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(31),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[30]_i_1_n_0\
    );
\dmcontrol_read[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^dbg_rst_0\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      I2 => O,
      O => \dmcontrol_read[31]_i_1_n_0\
    );
\dmcontrol_read[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^dmcontrol_ndmreset_reg_0\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      I2 => dmcontrol_read(4),
      O => \dmcontrol_read[3]_i_1_n_0\
    );
\dmcontrol_read[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(5),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[4]_i_1_n_0\
    );
\dmcontrol_read[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(6),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[5]_i_1_n_0\
    );
\dmcontrol_read[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(7),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[6]_i_1_n_0\
    );
\dmcontrol_read[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(8),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[7]_i_1_n_0\
    );
\dmcontrol_read[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(9),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[8]_i_1_n_0\
    );
\dmcontrol_read[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => dmcontrol_read(10),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmcontrol_read[9]_i_1_n_0\
    );
\dmcontrol_read_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[0]_i_1_n_0\,
      Q => dmcontrol_read(0),
      R => '0'
    );
\dmcontrol_read_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[10]_i_1_n_0\,
      Q => dmcontrol_read(10),
      R => '0'
    );
\dmcontrol_read_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[11]_i_1_n_0\,
      Q => dmcontrol_read(11),
      R => '0'
    );
\dmcontrol_read_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[12]_i_1_n_0\,
      Q => dmcontrol_read(12),
      R => '0'
    );
\dmcontrol_read_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[13]_i_1_n_0\,
      Q => dmcontrol_read(13),
      R => '0'
    );
\dmcontrol_read_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[14]_i_1_n_0\,
      Q => dmcontrol_read(14),
      R => '0'
    );
\dmcontrol_read_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[15]_i_1_n_0\,
      Q => dmcontrol_read(15),
      R => '0'
    );
\dmcontrol_read_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[16]_i_1_n_0\,
      Q => dmcontrol_read(16),
      R => '0'
    );
\dmcontrol_read_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[17]_i_1_n_0\,
      Q => dmcontrol_read(17),
      R => '0'
    );
\dmcontrol_read_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[18]_i_1_n_0\,
      Q => dmcontrol_read(18),
      R => '0'
    );
\dmcontrol_read_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[19]_i_1_n_0\,
      Q => dmcontrol_read(19),
      R => '0'
    );
\dmcontrol_read_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[1]_i_1_n_0\,
      Q => dmcontrol_read(1),
      R => '0'
    );
\dmcontrol_read_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[20]_i_1_n_0\,
      Q => dmcontrol_read(20),
      R => '0'
    );
\dmcontrol_read_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[21]_i_1_n_0\,
      Q => dmcontrol_read(21),
      R => '0'
    );
\dmcontrol_read_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[22]_i_1_n_0\,
      Q => dmcontrol_read(22),
      R => '0'
    );
\dmcontrol_read_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[23]_i_1_n_0\,
      Q => dmcontrol_read(23),
      R => '0'
    );
\dmcontrol_read_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[24]_i_1_n_0\,
      Q => dmcontrol_read(24),
      R => '0'
    );
\dmcontrol_read_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[25]_i_1_n_0\,
      Q => dmcontrol_read(25),
      R => '0'
    );
\dmcontrol_read_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[26]_i_1_n_0\,
      Q => dmcontrol_read(26),
      R => '0'
    );
\dmcontrol_read_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[27]_i_1_n_0\,
      Q => dmcontrol_read(27),
      R => '0'
    );
\dmcontrol_read_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[28]_i_1_n_0\,
      Q => dmcontrol_read(28),
      R => '0'
    );
\dmcontrol_read_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[29]_i_1_n_0\,
      Q => dmcontrol_read(29),
      R => '0'
    );
\dmcontrol_read_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[2]_i_1_n_0\,
      Q => dmcontrol_read(2),
      R => '0'
    );
\dmcontrol_read_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[30]_i_1_n_0\,
      Q => dmcontrol_read(30),
      R => '0'
    );
\dmcontrol_read_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[31]_i_1_n_0\,
      Q => dmcontrol_read(31),
      R => '0'
    );
\dmcontrol_read_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[3]_i_1_n_0\,
      Q => dmcontrol_read(3),
      R => '0'
    );
\dmcontrol_read_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[4]_i_1_n_0\,
      Q => dmcontrol_read(4),
      R => '0'
    );
\dmcontrol_read_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[5]_i_1_n_0\,
      Q => dmcontrol_read(5),
      R => '0'
    );
\dmcontrol_read_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[6]_i_1_n_0\,
      Q => dmcontrol_read(6),
      R => '0'
    );
\dmcontrol_read_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[7]_i_1_n_0\,
      Q => dmcontrol_read(7),
      R => '0'
    );
\dmcontrol_read_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[8]_i_1_n_0\,
      Q => dmcontrol_read(8),
      R => '0'
    );
\dmcontrol_read_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmcontrol_read[9]_i_1_n_0\,
      Q => dmcontrol_read(9),
      R => '0'
    );
\dmi[41]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^test_access_port.shift_dtm_reg_0\,
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => dmistat15_out
    );
\dmi_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => \dmi_reg_n_0_[1]\,
      Q => \dmi_reg_n_0_[0]\,
      R => '0'
    );
\dmi_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => \dmi_reg_n_0_[2]\,
      Q => \dmi_reg_n_0_[1]\,
      R => '0'
    );
\dmi_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in3_in,
      Q => \dmi_reg_n_0_[2]\,
      R => '0'
    );
\dmi_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => \dmi_reg[32]_srl2_n_0\,
      Q => p_0_in2_in,
      R => '0'
    );
\dmi_reg[32]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => dmistat15_out,
      CLK => \^using_fpga.native\,
      D => p_0_in_4(0),
      Q => \dmi_reg[32]_srl2_n_0\
    );
\dmi_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(1),
      Q => p_0_in_4(0),
      R => '0'
    );
\dmi_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(2),
      Q => p_0_in_4(1),
      R => '0'
    );
\dmi_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(3),
      Q => p_0_in_4(2),
      R => '0'
    );
\dmi_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(4),
      Q => p_0_in_4(3),
      R => '0'
    );
\dmi_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(5),
      Q => p_0_in_4(4),
      R => '0'
    );
\dmi_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(6),
      Q => p_0_in_4(5),
      R => '0'
    );
\dmi_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => \dmi_reg[4]_srl27_n_0\,
      Q => p_0_in3_in,
      R => '0'
    );
\dmi_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => p_0_in_4(7),
      Q => p_0_in_4(6),
      R => '0'
    );
\dmi_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat15_out,
      D => O,
      Q => p_0_in_4(7),
      R => '0'
    );
\dmi_reg[4]_srl27\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11010",
      CE => dmistat15_out,
      CLK => \^using_fpga.native\,
      D => p_0_in2_in,
      Q => \dmi_reg[4]_srl27_n_0\,
      Q31 => \NLW_dmi_reg[4]_srl27_Q31_UNCONNECTED\
    );
dmihardreset_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in0_in,
      I1 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      O => dmihardreset
    );
dmihardreset_reg: unisim.vcomponents.FDRE
     port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => dmihardreset,
      Q => dmihardreset_reg_n_0,
      R => '0'
    );
dmireset_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[16]\,
      I1 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      O => dmireset
    );
dmireset_reg: unisim.vcomponents.FDRE
     port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => dmireset,
      Q => dmireset_reg_n_0,
      R => '0'
    );
\dmistat[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_1_in(11),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmistat[0]_i_1_n_0\
    );
\dmistat[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEE0000EEEEF000"
    )
        port map (
      I0 => dmireset_reg_n_0,
      I1 => dmihardreset_reg_n_0,
      I2 => \dmistat[1]_i_3_n_0\,
      I3 => dmistat15_out,
      I4 => \^test_access_port.capture_dtm_reg_0\,
      I5 => \dmistat_current_reg_n_0_[1]\,
      O => \dmistat[1]_i_1_n_0\
    );
\dmistat[1]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => command(3),
      I1 => command(2),
      I2 => command(1),
      I3 => command(0),
      O => \dmistat[1]_i_10_n_0\
    );
\dmistat[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      I2 => \dtmcs_reg_n_0_[0]\,
      I3 => sel_idcode,
      I4 => sel_bypass,
      I5 => sel_ir,
      O => \dmistat[1]_i_11_n_0\
    );
\dmistat[1]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      I1 => sel_ir,
      I2 => sel_bypass,
      I3 => sel_idcode,
      I4 => command(7),
      O => \dmistat[1]_i_12_n_0\
    );
\dmistat[1]_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
        port map (
      I0 => dmstatus_shift_count_reg(0),
      I1 => dmstatus_shift_count_reg(1),
      I2 => dmstatus_shift_count_reg(3),
      I3 => dmstatus_shift_count_reg(4),
      I4 => dmstatus_shift_count_reg(2),
      O => \dmistat[1]_i_13_n_0\
    );
\dmistat[1]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => command(3),
      I1 => command(2),
      I2 => command(0),
      O => \dmistat[1]_i_14_n_0\
    );
\dmistat[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEFE"
    )
        port map (
      I0 => \dmistat[1]_i_4_n_0\,
      I1 => \dmistat[1]_i_5_n_0\,
      I2 => \dmistat[1]_i_6_n_0\,
      I3 => \^test_access_port.capture_dtm_reg_0\,
      I4 => \dmistat[1]_i_7_n_0\,
      I5 => \dmistat[1]_i_8_n_0\,
      O => \dmistat[1]_i_2_n_0\
    );
\dmistat[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \dmistat_current_reg_n_0_[0]\,
      I1 => idle_reg,
      I2 => \dmistat_shift_count_reg_n_0_[1]\,
      O => \dmistat[1]_i_3_n_0\
    );
\dmistat[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F8008800880088"
    )
        port map (
      I0 => TDO_i_3_n_0,
      I1 => TDO_i_4_n_0,
      I2 => \dmistat[1]_i_9_n_0\,
      I3 => \^test_access_port.capture_dtm_reg_0\,
      I4 => dmcontrol_read(0),
      I5 => \dmistat[1]_i_10_n_0\,
      O => \dmistat[1]_i_4_n_0\
    );
\dmistat[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F0FFF0F8F8"
    )
        port map (
      I0 => TDO_bypass,
      I1 => sel_bypass,
      I2 => \dmistat[1]_i_11_n_0\,
      I3 => TDO_ir,
      I4 => sel_ir,
      I5 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmistat[1]_i_5_n_0\
    );
\dmistat[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000000000"
    )
        port map (
      I0 => \dmistat[1]_i_10_n_0\,
      I1 => command(4),
      I2 => \haltsum0_read_reg_n_0_[0]\,
      I3 => command(5),
      I4 => command(6),
      I5 => \dmistat[1]_i_12_n_0\,
      O => \dmistat[1]_i_6_n_0\
    );
\dmistat[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.idcode\(0),
      I2 => sel_idcode,
      I3 => sel_ir,
      I4 => sel_bypass,
      O => \dmistat[1]_i_7_n_0\
    );
\dmistat[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => \dmistat[1]_i_13_n_0\,
      I1 => \^dmcontrol_ndmreset_reg_0\,
      I2 => command(1),
      I3 => \^test_access_port.capture_dtm_reg_0\,
      I4 => \dmistat[1]_i_14_n_0\,
      I5 => \dmistat[1]_i_9_n_0\,
      O => \dmistat[1]_i_8_n_0\
    );
\dmistat[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => command(5),
      I1 => command(6),
      I2 => command(4),
      I3 => command(7),
      I4 => TDO_i_8_n_0,
      I5 => \Test_Access_Port.sel_dtmcs_reg_n_0\,
      O => \dmistat[1]_i_9_n_0\
    );
\dmistat_current[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I1 => p_1_in(10),
      I2 => dmihardreset_reg_n_0,
      I3 => dmireset_reg_n_0,
      O => \dmistat_current[0]_i_1_n_0\
    );
\dmistat_current[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AE00"
    )
        port map (
      I0 => dmihardreset_reg_n_0,
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I2 => dmireset_reg_n_0,
      I3 => \^test_access_port.capture_dtm_reg_0\,
      O => dmistat_current(0)
    );
\dmistat_current[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I1 => p_1_in(11),
      I2 => dmihardreset_reg_n_0,
      I3 => dmireset_reg_n_0,
      O => \dmistat_current[1]_i_2_n_0\
    );
\dmistat_current_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat_current(0),
      D => \dmistat_current[0]_i_1_n_0\,
      Q => \dmistat_current_reg_n_0_[0]\,
      R => '0'
    );
\dmistat_current_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmistat_current(0),
      D => \dmistat_current[1]_i_2_n_0\,
      Q => \dmistat_current_reg_n_0_[1]\,
      R => '0'
    );
\dmistat_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \dmistat[1]_i_1_n_0\,
      D => \dmistat[0]_i_1_n_0\,
      Q => p_1_in(10),
      R => '0'
    );
\dmistat_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \dmistat[1]_i_1_n_0\,
      D => \dmistat[1]_i_2_n_0\,
      Q => p_1_in(11),
      R => '0'
    );
\dmistat_shift_count[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \dmistat_shift_count_reg_n_0_[0]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmistat_shift_count[0]_i_1_n_0\
    );
\dmistat_shift_count[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAEA"
    )
        port map (
      I0 => dmistat_current(0),
      I1 => \^test_access_port.shift_dtm_reg_0\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I3 => idle_reg,
      I4 => \dmistat_shift_count_reg_n_0_[1]\,
      I5 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmistat_shift_count[1]_i_1_n_0\
    );
\dmistat_shift_count[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \dmistat_shift_count_reg_n_0_[1]\,
      I1 => \dmistat_shift_count_reg_n_0_[0]\,
      I2 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmistat_shift_count[1]_i_2_n_0\
    );
\dmistat_shift_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \dmistat_shift_count[1]_i_1_n_0\,
      D => \dmistat_shift_count[0]_i_1_n_0\,
      Q => \dmistat_shift_count_reg_n_0_[0]\,
      R => '0'
    );
\dmistat_shift_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \dmistat_shift_count[1]_i_1_n_0\,
      D => \dmistat_shift_count[1]_i_2_n_0\,
      Q => \dmistat_shift_count_reg_n_0_[1]\,
      R => '0'
    );
\dmstatus_shift_count[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => dmstatus_shift_count_reg(0),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmstatus_shift_count[0]_i_1_n_0\
    );
\dmstatus_shift_count[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => dmstatus_shift_count_reg(1),
      I1 => dmstatus_shift_count_reg(0),
      I2 => \^test_access_port.capture_dtm_reg_0\,
      O => \dmstatus_shift_count[1]_i_1_n_0\
    );
\dmstatus_shift_count[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"006A"
    )
        port map (
      I0 => dmstatus_shift_count_reg(2),
      I1 => dmstatus_shift_count_reg(0),
      I2 => dmstatus_shift_count_reg(1),
      I3 => \^test_access_port.capture_dtm_reg_0\,
      O => p_0_in(2)
    );
\dmstatus_shift_count[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006AAA"
    )
        port map (
      I0 => dmstatus_shift_count_reg(3),
      I1 => dmstatus_shift_count_reg(2),
      I2 => dmstatus_shift_count_reg(1),
      I3 => dmstatus_shift_count_reg(0),
      I4 => \^test_access_port.capture_dtm_reg_0\,
      O => p_0_in(3)
    );
\dmstatus_shift_count[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000006AAAAAAA"
    )
        port map (
      I0 => dmstatus_shift_count_reg(4),
      I1 => dmstatus_shift_count_reg(2),
      I2 => dmstatus_shift_count_reg(0),
      I3 => dmstatus_shift_count_reg(3),
      I4 => dmstatus_shift_count_reg(1),
      I5 => \^test_access_port.capture_dtm_reg_0\,
      O => p_0_in(4)
    );
\dmstatus_shift_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmstatus_shift_count[0]_i_1_n_0\,
      Q => dmstatus_shift_count_reg(0),
      R => '0'
    );
\dmstatus_shift_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \dmstatus_shift_count[1]_i_1_n_0\,
      Q => dmstatus_shift_count_reg(1),
      R => '0'
    );
\dmstatus_shift_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => p_0_in(2),
      Q => dmstatus_shift_count_reg(2),
      R => '0'
    );
\dmstatus_shift_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => p_0_in(3),
      Q => dmstatus_shift_count_reg(3),
      R => '0'
    );
\dmstatus_shift_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => p_0_in(4),
      Q => dmstatus_shift_count_reg(4),
      R => '0'
    );
\dtmcs[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[1]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[0]_i_1_n_0\
    );
\dtmcs[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(10),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      I2 => \dtmcs_reg_n_0_[11]\,
      O => \dtmcs[10]_i_1_n_0\
    );
\dtmcs[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_1_in(11),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      I2 => \dtmcs_reg_n_0_[12]\,
      O => \dtmcs[11]_i_1_n_0\
    );
\dtmcs[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[13]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[12]_i_1_n_0\
    );
\dtmcs[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^test_access_port.shift_dtm_reg_0\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \Test_Access_Port.idcode_3\(0)
    );
\dtmcs[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.idcode\(14),
      O => \dtmcs[13]_i_2_n_0\
    );
\dtmcs[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => p_0_in0_in,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[16]_i_1_n_0\
    );
\dtmcs[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[18]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[17]_i_1_n_0\
    );
\dtmcs[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[19]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[18]_i_1_n_0\
    );
\dtmcs[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[20]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[19]_i_1_n_0\
    );
\dtmcs[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[2]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[1]_i_1_n_0\
    );
\dtmcs[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[21]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[20]_i_1_n_0\
    );
\dtmcs[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[22]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[21]_i_1_n_0\
    );
\dtmcs[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[23]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[22]_i_1_n_0\
    );
\dtmcs[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[24]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[23]_i_1_n_0\
    );
\dtmcs[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[25]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[24]_i_1_n_0\
    );
\dtmcs[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[26]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[25]_i_1_n_0\
    );
\dtmcs[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[27]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[26]_i_1_n_0\
    );
\dtmcs[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[28]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[27]_i_1_n_0\
    );
\dtmcs[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[29]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[28]_i_1_n_0\
    );
\dtmcs[29]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[30]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[29]_i_1_n_0\
    );
\dtmcs[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[3]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[2]_i_1_n_0\
    );
\dtmcs[30]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[31]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[30]_i_1_n_0\
    );
\dtmcs[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[4]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[3]_i_1_n_0\
    );
\dtmcs[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[5]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[4]_i_1_n_0\
    );
\dtmcs[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[6]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[5]_i_1_n_0\
    );
\dtmcs[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[7]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[6]_i_1_n_0\
    );
\dtmcs[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[8]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[7]_i_1_n_0\
    );
\dtmcs[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[9]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[8]_i_1_n_0\
    );
\dtmcs[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \dtmcs_reg_n_0_[10]\,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \dtmcs[9]_i_1_n_0\
    );
\dtmcs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[0]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[0]\,
      R => '0'
    );
\dtmcs_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[10]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[10]\,
      R => '0'
    );
\dtmcs_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[11]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[11]\,
      R => '0'
    );
\dtmcs_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[12]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[12]\,
      R => '0'
    );
\dtmcs_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[13]_i_2_n_0\,
      Q => \dtmcs_reg_n_0_[13]\,
      R => '0'
    );
\dtmcs_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[16]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[16]\,
      R => '0'
    );
\dtmcs_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[17]_i_1_n_0\,
      Q => p_0_in0_in,
      R => '0'
    );
\dtmcs_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[18]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[18]\,
      R => '0'
    );
\dtmcs_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[19]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[19]\,
      R => '0'
    );
\dtmcs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[1]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[1]\,
      R => '0'
    );
\dtmcs_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[20]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[20]\,
      R => '0'
    );
\dtmcs_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[21]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[21]\,
      R => '0'
    );
\dtmcs_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[22]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[22]\,
      R => '0'
    );
\dtmcs_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[23]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[23]\,
      R => '0'
    );
\dtmcs_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[24]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[24]\,
      R => '0'
    );
\dtmcs_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[25]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[25]\,
      R => '0'
    );
\dtmcs_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[26]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[26]\,
      R => '0'
    );
\dtmcs_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[27]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[27]\,
      R => '0'
    );
\dtmcs_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[28]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[28]\,
      R => '0'
    );
\dtmcs_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[29]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[29]\,
      R => '0'
    );
\dtmcs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[2]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[2]\,
      R => '0'
    );
\dtmcs_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[30]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[30]\,
      R => '0'
    );
\dtmcs_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs_reg[31]_0\,
      Q => \dtmcs_reg_n_0_[31]\,
      R => '0'
    );
\dtmcs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[3]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[3]\,
      R => '0'
    );
\dtmcs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[4]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[4]\,
      R => '0'
    );
\dtmcs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[5]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[5]\,
      R => '0'
    );
\dtmcs_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[6]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[6]\,
      R => '0'
    );
\dtmcs_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[7]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[7]\,
      R => '0'
    );
\dtmcs_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[8]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[8]\,
      R => '0'
    );
\dtmcs_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => \Test_Access_Port.idcode_3\(0),
      D => \dtmcs[9]_i_1_n_0\,
      Q => \dtmcs_reg_n_0_[9]\,
      R => '0'
    );
\haltsum0[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Dbg_TDO_0,
      I1 => \^test_access_port.capture_dtm_reg_0\,
      I2 => haltsum0(0),
      O => \haltsum0[0]_i_1_n_0\
    );
\haltsum0_read[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => haltsum0_read(1),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \haltsum0_read[0]_i_1_n_0\
    );
\haltsum0_read[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => haltsum0_read(2),
      I1 => \^test_access_port.capture_dtm_reg_0\,
      O => \haltsum0_read[1]_i_1_n_0\
    );
\haltsum0_read[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => \Test_Access_Port.sel_dmi_reg_n_0\,
      I2 => \^test_access_port.shift_dtm_reg_0\,
      O => dmcontrol_read_2(0)
    );
\haltsum0_read[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^test_access_port.capture_dtm_reg_0\,
      I1 => haltsum0(0),
      O => \haltsum0_read[2]_i_2_n_0\
    );
\haltsum0_read_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \haltsum0_read[0]_i_1_n_0\,
      Q => \haltsum0_read_reg_n_0_[0]\,
      R => '0'
    );
\haltsum0_read_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \haltsum0_read[1]_i_1_n_0\,
      Q => haltsum0_read(1),
      R => '0'
    );
\haltsum0_read_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => dmcontrol_read_2(0),
      D => \haltsum0_read[2]_i_2_n_0\,
      Q => haltsum0_read(2),
      R => '0'
    );
\haltsum0_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^using_fpga.native\,
      CE => '1',
      D => \haltsum0[0]_i_1_n_0\,
      Q => haltsum0(0),
      R => '0'
    );
idle_reg_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \dmi_reg_n_0_[1]\,
      I1 => \dmi_reg_n_0_[0]\,
      I2 => \Test_Access_Port.sel_dmi_reg_n_0\,
      O => idle_reg_i_1_n_0
    );
idle_reg_reg: unisim.vcomponents.FDRE
     port map (
      C => \^using_fpga.native_0\,
      CE => '1',
      D => idle_reg_i_1_n_0,
      Q => idle_reg,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MDM_Core is
  port (
    \Using_FPGA.Native\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Test_Access_Port.shift_dtm_reg\ : out STD_LOGIC;
    dmcontrol_ndmreset_reg : out STD_LOGIC;
    Dbg_Rst_0 : out STD_LOGIC;
    \Test_Access_Port.capture_dtm_reg\ : out STD_LOGIC;
    JTAG_TDO : out STD_LOGIC;
    \FSM_onehot_Test_Access_Port.state_reg[5]\ : out STD_LOGIC;
    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
    \Use_JTAG_BSCAN.tck_int\ : in STD_LOGIC;
    O : in STD_LOGIC;
    \dtmcs_reg[31]\ : in STD_LOGIC;
    jtag_tms : in STD_LOGIC;
    \Test_Access_Port.ir_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_TDO_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MDM_Core : entity is "MDM_Core";
end scu35_io_design_mdm_1_0_MDM_Core;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MDM_Core is
begin
JTAG_CONTROL_I: entity work.scu35_io_design_mdm_1_0_JTAG_CONTROL
     port map (
      Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
      Dbg_Rst_0 => Dbg_Rst_0,
      Dbg_TDO_0 => Dbg_TDO_0,
      \FSM_onehot_Test_Access_Port.state_reg[5]_0\ => \FSM_onehot_Test_Access_Port.state_reg[5]\,
      JTAG_TDO => JTAG_TDO,
      O => O,
      \Test_Access_Port.capture_dtm_reg_0\ => \Test_Access_Port.capture_dtm_reg\,
      \Test_Access_Port.ir_reg[4]_0\(0) => \Test_Access_Port.ir_reg[4]\(0),
      \Test_Access_Port.shift_dtm_reg_0\ => \Test_Access_Port.shift_dtm_reg\,
      \Use_JTAG_BSCAN.tck_int\ => \Use_JTAG_BSCAN.tck_int\,
      \Using_FPGA.Native\ => \Using_FPGA.Native\,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      dmcontrol_ndmreset_reg_0 => dmcontrol_ndmreset_reg,
      \dtmcs_reg[31]_0\ => \dtmcs_reg[31]\,
      jtag_tms => jtag_tms
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0_MDM_RISCV is
  port (
    Config_Reset : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    S_AXI_ACLK : in STD_LOGIC;
    S_AXI_ARESETN : in STD_LOGIC;
    M_AXI_ACLK : in STD_LOGIC;
    M_AXI_ARESETN : in STD_LOGIC;
    M_AXIS_ACLK : in STD_LOGIC;
    M_AXIS_ARESETN : in STD_LOGIC;
    Interrupt : out STD_LOGIC;
    Ext_BRK : out STD_LOGIC;
    Ext_NM_BRK : out STD_LOGIC;
    Debug_SYS_Rst : out STD_LOGIC;
    Trig_In_0 : in STD_LOGIC;
    Trig_Ack_In_0 : out STD_LOGIC;
    Trig_Out_0 : out STD_LOGIC;
    Trig_Ack_Out_0 : in STD_LOGIC;
    Trig_In_1 : in STD_LOGIC;
    Trig_Ack_In_1 : out STD_LOGIC;
    Trig_Out_1 : out STD_LOGIC;
    Trig_Ack_Out_1 : in STD_LOGIC;
    Trig_In_2 : in STD_LOGIC;
    Trig_Ack_In_2 : out STD_LOGIC;
    Trig_Out_2 : out STD_LOGIC;
    Trig_Ack_Out_2 : in STD_LOGIC;
    Trig_In_3 : in STD_LOGIC;
    Trig_Ack_In_3 : out STD_LOGIC;
    Trig_Out_3 : out STD_LOGIC;
    Trig_Ack_Out_3 : in STD_LOGIC;
    S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S_AXI_AWVALID : in STD_LOGIC;
    S_AXI_AWREADY : out STD_LOGIC;
    S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S_AXI_WVALID : in STD_LOGIC;
    S_AXI_WREADY : out STD_LOGIC;
    S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S_AXI_BVALID : out STD_LOGIC;
    S_AXI_BREADY : in STD_LOGIC;
    S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S_AXI_ARVALID : in STD_LOGIC;
    S_AXI_ARREADY : out STD_LOGIC;
    S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S_AXI_RVALID : out STD_LOGIC;
    S_AXI_RREADY : in STD_LOGIC;
    M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_AWLOCK : out STD_LOGIC;
    M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_AWVALID : out STD_LOGIC;
    M_AXI_AWREADY : in STD_LOGIC;
    M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_WLAST : out STD_LOGIC;
    M_AXI_WVALID : out STD_LOGIC;
    M_AXI_WREADY : in STD_LOGIC;
    M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_BVALID : in STD_LOGIC;
    M_AXI_BREADY : out STD_LOGIC;
    M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_ARLOCK : out STD_LOGIC;
    M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_ARVALID : out STD_LOGIC;
    M_AXI_ARREADY : in STD_LOGIC;
    M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_RLAST : in STD_LOGIC;
    M_AXI_RVALID : in STD_LOGIC;
    M_AXI_RREADY : out STD_LOGIC;
    LMB_Data_Addr_0 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_0 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_0 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_0 : out STD_LOGIC;
    LMB_Read_Strobe_0 : out STD_LOGIC;
    LMB_Write_Strobe_0 : out STD_LOGIC;
    LMB_Ready_0 : in STD_LOGIC;
    LMB_Wait_0 : in STD_LOGIC;
    LMB_CE_0 : in STD_LOGIC;
    LMB_UE_0 : in STD_LOGIC;
    LMB_Byte_Enable_0 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_1 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_1 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_1 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_1 : out STD_LOGIC;
    LMB_Read_Strobe_1 : out STD_LOGIC;
    LMB_Write_Strobe_1 : out STD_LOGIC;
    LMB_Ready_1 : in STD_LOGIC;
    LMB_Wait_1 : in STD_LOGIC;
    LMB_CE_1 : in STD_LOGIC;
    LMB_UE_1 : in STD_LOGIC;
    LMB_Byte_Enable_1 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_2 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_2 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_2 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_2 : out STD_LOGIC;
    LMB_Read_Strobe_2 : out STD_LOGIC;
    LMB_Write_Strobe_2 : out STD_LOGIC;
    LMB_Ready_2 : in STD_LOGIC;
    LMB_Wait_2 : in STD_LOGIC;
    LMB_CE_2 : in STD_LOGIC;
    LMB_UE_2 : in STD_LOGIC;
    LMB_Byte_Enable_2 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_3 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_3 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_3 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_3 : out STD_LOGIC;
    LMB_Read_Strobe_3 : out STD_LOGIC;
    LMB_Write_Strobe_3 : out STD_LOGIC;
    LMB_Ready_3 : in STD_LOGIC;
    LMB_Wait_3 : in STD_LOGIC;
    LMB_CE_3 : in STD_LOGIC;
    LMB_UE_3 : in STD_LOGIC;
    LMB_Byte_Enable_3 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_4 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_4 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_4 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_4 : out STD_LOGIC;
    LMB_Read_Strobe_4 : out STD_LOGIC;
    LMB_Write_Strobe_4 : out STD_LOGIC;
    LMB_Ready_4 : in STD_LOGIC;
    LMB_Wait_4 : in STD_LOGIC;
    LMB_CE_4 : in STD_LOGIC;
    LMB_UE_4 : in STD_LOGIC;
    LMB_Byte_Enable_4 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_5 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_5 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_5 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_5 : out STD_LOGIC;
    LMB_Read_Strobe_5 : out STD_LOGIC;
    LMB_Write_Strobe_5 : out STD_LOGIC;
    LMB_Ready_5 : in STD_LOGIC;
    LMB_Wait_5 : in STD_LOGIC;
    LMB_CE_5 : in STD_LOGIC;
    LMB_UE_5 : in STD_LOGIC;
    LMB_Byte_Enable_5 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_6 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_6 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_6 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_6 : out STD_LOGIC;
    LMB_Read_Strobe_6 : out STD_LOGIC;
    LMB_Write_Strobe_6 : out STD_LOGIC;
    LMB_Ready_6 : in STD_LOGIC;
    LMB_Wait_6 : in STD_LOGIC;
    LMB_CE_6 : in STD_LOGIC;
    LMB_UE_6 : in STD_LOGIC;
    LMB_Byte_Enable_6 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_7 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_7 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_7 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_7 : out STD_LOGIC;
    LMB_Read_Strobe_7 : out STD_LOGIC;
    LMB_Write_Strobe_7 : out STD_LOGIC;
    LMB_Ready_7 : in STD_LOGIC;
    LMB_Wait_7 : in STD_LOGIC;
    LMB_CE_7 : in STD_LOGIC;
    LMB_UE_7 : in STD_LOGIC;
    LMB_Byte_Enable_7 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_8 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_8 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_8 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_8 : out STD_LOGIC;
    LMB_Read_Strobe_8 : out STD_LOGIC;
    LMB_Write_Strobe_8 : out STD_LOGIC;
    LMB_Ready_8 : in STD_LOGIC;
    LMB_Wait_8 : in STD_LOGIC;
    LMB_CE_8 : in STD_LOGIC;
    LMB_UE_8 : in STD_LOGIC;
    LMB_Byte_Enable_8 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_9 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_9 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_9 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_9 : out STD_LOGIC;
    LMB_Read_Strobe_9 : out STD_LOGIC;
    LMB_Write_Strobe_9 : out STD_LOGIC;
    LMB_Ready_9 : in STD_LOGIC;
    LMB_Wait_9 : in STD_LOGIC;
    LMB_CE_9 : in STD_LOGIC;
    LMB_UE_9 : in STD_LOGIC;
    LMB_Byte_Enable_9 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_10 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_10 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_10 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_10 : out STD_LOGIC;
    LMB_Read_Strobe_10 : out STD_LOGIC;
    LMB_Write_Strobe_10 : out STD_LOGIC;
    LMB_Ready_10 : in STD_LOGIC;
    LMB_Wait_10 : in STD_LOGIC;
    LMB_CE_10 : in STD_LOGIC;
    LMB_UE_10 : in STD_LOGIC;
    LMB_Byte_Enable_10 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_11 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_11 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_11 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_11 : out STD_LOGIC;
    LMB_Read_Strobe_11 : out STD_LOGIC;
    LMB_Write_Strobe_11 : out STD_LOGIC;
    LMB_Ready_11 : in STD_LOGIC;
    LMB_Wait_11 : in STD_LOGIC;
    LMB_CE_11 : in STD_LOGIC;
    LMB_UE_11 : in STD_LOGIC;
    LMB_Byte_Enable_11 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_12 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_12 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_12 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_12 : out STD_LOGIC;
    LMB_Read_Strobe_12 : out STD_LOGIC;
    LMB_Write_Strobe_12 : out STD_LOGIC;
    LMB_Ready_12 : in STD_LOGIC;
    LMB_Wait_12 : in STD_LOGIC;
    LMB_CE_12 : in STD_LOGIC;
    LMB_UE_12 : in STD_LOGIC;
    LMB_Byte_Enable_12 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_13 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_13 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_13 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_13 : out STD_LOGIC;
    LMB_Read_Strobe_13 : out STD_LOGIC;
    LMB_Write_Strobe_13 : out STD_LOGIC;
    LMB_Ready_13 : in STD_LOGIC;
    LMB_Wait_13 : in STD_LOGIC;
    LMB_CE_13 : in STD_LOGIC;
    LMB_UE_13 : in STD_LOGIC;
    LMB_Byte_Enable_13 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_14 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_14 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_14 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_14 : out STD_LOGIC;
    LMB_Read_Strobe_14 : out STD_LOGIC;
    LMB_Write_Strobe_14 : out STD_LOGIC;
    LMB_Ready_14 : in STD_LOGIC;
    LMB_Wait_14 : in STD_LOGIC;
    LMB_CE_14 : in STD_LOGIC;
    LMB_UE_14 : in STD_LOGIC;
    LMB_Byte_Enable_14 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_15 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_15 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_15 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_15 : out STD_LOGIC;
    LMB_Read_Strobe_15 : out STD_LOGIC;
    LMB_Write_Strobe_15 : out STD_LOGIC;
    LMB_Ready_15 : in STD_LOGIC;
    LMB_Wait_15 : in STD_LOGIC;
    LMB_CE_15 : in STD_LOGIC;
    LMB_UE_15 : in STD_LOGIC;
    LMB_Byte_Enable_15 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_16 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_16 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_16 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_16 : out STD_LOGIC;
    LMB_Read_Strobe_16 : out STD_LOGIC;
    LMB_Write_Strobe_16 : out STD_LOGIC;
    LMB_Ready_16 : in STD_LOGIC;
    LMB_Wait_16 : in STD_LOGIC;
    LMB_CE_16 : in STD_LOGIC;
    LMB_UE_16 : in STD_LOGIC;
    LMB_Byte_Enable_16 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_17 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_17 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_17 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_17 : out STD_LOGIC;
    LMB_Read_Strobe_17 : out STD_LOGIC;
    LMB_Write_Strobe_17 : out STD_LOGIC;
    LMB_Ready_17 : in STD_LOGIC;
    LMB_Wait_17 : in STD_LOGIC;
    LMB_CE_17 : in STD_LOGIC;
    LMB_UE_17 : in STD_LOGIC;
    LMB_Byte_Enable_17 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_18 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_18 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_18 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_18 : out STD_LOGIC;
    LMB_Read_Strobe_18 : out STD_LOGIC;
    LMB_Write_Strobe_18 : out STD_LOGIC;
    LMB_Ready_18 : in STD_LOGIC;
    LMB_Wait_18 : in STD_LOGIC;
    LMB_CE_18 : in STD_LOGIC;
    LMB_UE_18 : in STD_LOGIC;
    LMB_Byte_Enable_18 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_19 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_19 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_19 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_19 : out STD_LOGIC;
    LMB_Read_Strobe_19 : out STD_LOGIC;
    LMB_Write_Strobe_19 : out STD_LOGIC;
    LMB_Ready_19 : in STD_LOGIC;
    LMB_Wait_19 : in STD_LOGIC;
    LMB_CE_19 : in STD_LOGIC;
    LMB_UE_19 : in STD_LOGIC;
    LMB_Byte_Enable_19 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_20 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_20 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_20 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_20 : out STD_LOGIC;
    LMB_Read_Strobe_20 : out STD_LOGIC;
    LMB_Write_Strobe_20 : out STD_LOGIC;
    LMB_Ready_20 : in STD_LOGIC;
    LMB_Wait_20 : in STD_LOGIC;
    LMB_CE_20 : in STD_LOGIC;
    LMB_UE_20 : in STD_LOGIC;
    LMB_Byte_Enable_20 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_21 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_21 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_21 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_21 : out STD_LOGIC;
    LMB_Read_Strobe_21 : out STD_LOGIC;
    LMB_Write_Strobe_21 : out STD_LOGIC;
    LMB_Ready_21 : in STD_LOGIC;
    LMB_Wait_21 : in STD_LOGIC;
    LMB_CE_21 : in STD_LOGIC;
    LMB_UE_21 : in STD_LOGIC;
    LMB_Byte_Enable_21 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_22 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_22 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_22 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_22 : out STD_LOGIC;
    LMB_Read_Strobe_22 : out STD_LOGIC;
    LMB_Write_Strobe_22 : out STD_LOGIC;
    LMB_Ready_22 : in STD_LOGIC;
    LMB_Wait_22 : in STD_LOGIC;
    LMB_CE_22 : in STD_LOGIC;
    LMB_UE_22 : in STD_LOGIC;
    LMB_Byte_Enable_22 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_23 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_23 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_23 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_23 : out STD_LOGIC;
    LMB_Read_Strobe_23 : out STD_LOGIC;
    LMB_Write_Strobe_23 : out STD_LOGIC;
    LMB_Ready_23 : in STD_LOGIC;
    LMB_Wait_23 : in STD_LOGIC;
    LMB_CE_23 : in STD_LOGIC;
    LMB_UE_23 : in STD_LOGIC;
    LMB_Byte_Enable_23 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_24 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_24 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_24 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_24 : out STD_LOGIC;
    LMB_Read_Strobe_24 : out STD_LOGIC;
    LMB_Write_Strobe_24 : out STD_LOGIC;
    LMB_Ready_24 : in STD_LOGIC;
    LMB_Wait_24 : in STD_LOGIC;
    LMB_CE_24 : in STD_LOGIC;
    LMB_UE_24 : in STD_LOGIC;
    LMB_Byte_Enable_24 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_25 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_25 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_25 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_25 : out STD_LOGIC;
    LMB_Read_Strobe_25 : out STD_LOGIC;
    LMB_Write_Strobe_25 : out STD_LOGIC;
    LMB_Ready_25 : in STD_LOGIC;
    LMB_Wait_25 : in STD_LOGIC;
    LMB_CE_25 : in STD_LOGIC;
    LMB_UE_25 : in STD_LOGIC;
    LMB_Byte_Enable_25 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_26 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_26 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_26 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_26 : out STD_LOGIC;
    LMB_Read_Strobe_26 : out STD_LOGIC;
    LMB_Write_Strobe_26 : out STD_LOGIC;
    LMB_Ready_26 : in STD_LOGIC;
    LMB_Wait_26 : in STD_LOGIC;
    LMB_CE_26 : in STD_LOGIC;
    LMB_UE_26 : in STD_LOGIC;
    LMB_Byte_Enable_26 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_27 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_27 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_27 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_27 : out STD_LOGIC;
    LMB_Read_Strobe_27 : out STD_LOGIC;
    LMB_Write_Strobe_27 : out STD_LOGIC;
    LMB_Ready_27 : in STD_LOGIC;
    LMB_Wait_27 : in STD_LOGIC;
    LMB_CE_27 : in STD_LOGIC;
    LMB_UE_27 : in STD_LOGIC;
    LMB_Byte_Enable_27 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_28 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_28 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_28 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_28 : out STD_LOGIC;
    LMB_Read_Strobe_28 : out STD_LOGIC;
    LMB_Write_Strobe_28 : out STD_LOGIC;
    LMB_Ready_28 : in STD_LOGIC;
    LMB_Wait_28 : in STD_LOGIC;
    LMB_CE_28 : in STD_LOGIC;
    LMB_UE_28 : in STD_LOGIC;
    LMB_Byte_Enable_28 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_29 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_29 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_29 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_29 : out STD_LOGIC;
    LMB_Read_Strobe_29 : out STD_LOGIC;
    LMB_Write_Strobe_29 : out STD_LOGIC;
    LMB_Ready_29 : in STD_LOGIC;
    LMB_Wait_29 : in STD_LOGIC;
    LMB_CE_29 : in STD_LOGIC;
    LMB_UE_29 : in STD_LOGIC;
    LMB_Byte_Enable_29 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_30 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_30 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_30 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_30 : out STD_LOGIC;
    LMB_Read_Strobe_30 : out STD_LOGIC;
    LMB_Write_Strobe_30 : out STD_LOGIC;
    LMB_Ready_30 : in STD_LOGIC;
    LMB_Wait_30 : in STD_LOGIC;
    LMB_CE_30 : in STD_LOGIC;
    LMB_UE_30 : in STD_LOGIC;
    LMB_Byte_Enable_30 : out STD_LOGIC_VECTOR ( 0 to 3 );
    LMB_Data_Addr_31 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Read_31 : in STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Data_Write_31 : out STD_LOGIC_VECTOR ( 0 to 31 );
    LMB_Addr_Strobe_31 : out STD_LOGIC;
    LMB_Read_Strobe_31 : out STD_LOGIC;
    LMB_Write_Strobe_31 : out STD_LOGIC;
    LMB_Ready_31 : in STD_LOGIC;
    LMB_Wait_31 : in STD_LOGIC;
    LMB_CE_31 : in STD_LOGIC;
    LMB_UE_31 : in STD_LOGIC;
    LMB_Byte_Enable_31 : out STD_LOGIC_VECTOR ( 0 to 3 );
    M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXIS_TID : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M_AXIS_TREADY : in STD_LOGIC;
    M_AXIS_TVALID : out STD_LOGIC;
    TRACE_CLK_OUT : out STD_LOGIC;
    TRACE_CLK : in STD_LOGIC;
    TRACE_CTL : out STD_LOGIC;
    TRACE_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_Disable_0 : out STD_LOGIC;
    Dbg_Clk_0 : out STD_LOGIC;
    Dbg_TDI_0 : out STD_LOGIC;
    Dbg_TDO_0 : in STD_LOGIC;
    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_0 : out STD_LOGIC;
    Dbg_Shift_0 : out STD_LOGIC;
    Dbg_Update_0 : out STD_LOGIC;
    Dbg_Rst_0 : out STD_LOGIC;
    Dbg_Trig_In_0 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_0 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_0 : out STD_LOGIC;
    Dbg_TrData_0 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_0 : out STD_LOGIC;
    Dbg_TrValid_0 : in STD_LOGIC;
    Dbg_AWADDR_0 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_0 : out STD_LOGIC;
    Dbg_AWREADY_0 : in STD_LOGIC;
    Dbg_WDATA_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_0 : out STD_LOGIC;
    Dbg_WREADY_0 : in STD_LOGIC;
    Dbg_BRESP_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_0 : in STD_LOGIC;
    Dbg_BREADY_0 : out STD_LOGIC;
    Dbg_ARADDR_0 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_0 : out STD_LOGIC;
    Dbg_ARREADY_0 : in STD_LOGIC;
    Dbg_RDATA_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_0 : in STD_LOGIC;
    Dbg_RREADY_0 : out STD_LOGIC;
    Dbg_Disable_1 : out STD_LOGIC;
    Dbg_Clk_1 : out STD_LOGIC;
    Dbg_TDI_1 : out STD_LOGIC;
    Dbg_TDO_1 : in STD_LOGIC;
    Dbg_Reg_En_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_1 : out STD_LOGIC;
    Dbg_Shift_1 : out STD_LOGIC;
    Dbg_Update_1 : out STD_LOGIC;
    Dbg_Rst_1 : out STD_LOGIC;
    Dbg_Trig_In_1 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_1 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_1 : out STD_LOGIC;
    Dbg_TrData_1 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_1 : out STD_LOGIC;
    Dbg_TrValid_1 : in STD_LOGIC;
    Dbg_AWADDR_1 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_1 : out STD_LOGIC;
    Dbg_AWREADY_1 : in STD_LOGIC;
    Dbg_WDATA_1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_1 : out STD_LOGIC;
    Dbg_WREADY_1 : in STD_LOGIC;
    Dbg_BRESP_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_1 : in STD_LOGIC;
    Dbg_BREADY_1 : out STD_LOGIC;
    Dbg_ARADDR_1 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_1 : out STD_LOGIC;
    Dbg_ARREADY_1 : in STD_LOGIC;
    Dbg_RDATA_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_1 : in STD_LOGIC;
    Dbg_RREADY_1 : out STD_LOGIC;
    Dbg_Disable_2 : out STD_LOGIC;
    Dbg_Clk_2 : out STD_LOGIC;
    Dbg_TDI_2 : out STD_LOGIC;
    Dbg_TDO_2 : in STD_LOGIC;
    Dbg_Reg_En_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_2 : out STD_LOGIC;
    Dbg_Shift_2 : out STD_LOGIC;
    Dbg_Update_2 : out STD_LOGIC;
    Dbg_Rst_2 : out STD_LOGIC;
    Dbg_Trig_In_2 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_2 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_2 : out STD_LOGIC;
    Dbg_TrData_2 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_2 : out STD_LOGIC;
    Dbg_TrValid_2 : in STD_LOGIC;
    Dbg_AWADDR_2 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_2 : out STD_LOGIC;
    Dbg_AWREADY_2 : in STD_LOGIC;
    Dbg_WDATA_2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_2 : out STD_LOGIC;
    Dbg_WREADY_2 : in STD_LOGIC;
    Dbg_BRESP_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_2 : in STD_LOGIC;
    Dbg_BREADY_2 : out STD_LOGIC;
    Dbg_ARADDR_2 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_2 : out STD_LOGIC;
    Dbg_ARREADY_2 : in STD_LOGIC;
    Dbg_RDATA_2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_2 : in STD_LOGIC;
    Dbg_RREADY_2 : out STD_LOGIC;
    Dbg_Disable_3 : out STD_LOGIC;
    Dbg_Clk_3 : out STD_LOGIC;
    Dbg_TDI_3 : out STD_LOGIC;
    Dbg_TDO_3 : in STD_LOGIC;
    Dbg_Reg_En_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_3 : out STD_LOGIC;
    Dbg_Shift_3 : out STD_LOGIC;
    Dbg_Update_3 : out STD_LOGIC;
    Dbg_Rst_3 : out STD_LOGIC;
    Dbg_Trig_In_3 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_3 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_3 : out STD_LOGIC;
    Dbg_TrData_3 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_3 : out STD_LOGIC;
    Dbg_TrValid_3 : in STD_LOGIC;
    Dbg_AWADDR_3 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_3 : out STD_LOGIC;
    Dbg_AWREADY_3 : in STD_LOGIC;
    Dbg_WDATA_3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_3 : out STD_LOGIC;
    Dbg_WREADY_3 : in STD_LOGIC;
    Dbg_BRESP_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_3 : in STD_LOGIC;
    Dbg_BREADY_3 : out STD_LOGIC;
    Dbg_ARADDR_3 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_3 : out STD_LOGIC;
    Dbg_ARREADY_3 : in STD_LOGIC;
    Dbg_RDATA_3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_3 : in STD_LOGIC;
    Dbg_RREADY_3 : out STD_LOGIC;
    Dbg_Disable_4 : out STD_LOGIC;
    Dbg_Clk_4 : out STD_LOGIC;
    Dbg_TDI_4 : out STD_LOGIC;
    Dbg_TDO_4 : in STD_LOGIC;
    Dbg_Reg_En_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_4 : out STD_LOGIC;
    Dbg_Shift_4 : out STD_LOGIC;
    Dbg_Update_4 : out STD_LOGIC;
    Dbg_Rst_4 : out STD_LOGIC;
    Dbg_Trig_In_4 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_4 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_4 : out STD_LOGIC;
    Dbg_TrData_4 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_4 : out STD_LOGIC;
    Dbg_TrValid_4 : in STD_LOGIC;
    Dbg_AWADDR_4 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_4 : out STD_LOGIC;
    Dbg_AWREADY_4 : in STD_LOGIC;
    Dbg_WDATA_4 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_4 : out STD_LOGIC;
    Dbg_WREADY_4 : in STD_LOGIC;
    Dbg_BRESP_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_4 : in STD_LOGIC;
    Dbg_BREADY_4 : out STD_LOGIC;
    Dbg_ARADDR_4 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_4 : out STD_LOGIC;
    Dbg_ARREADY_4 : in STD_LOGIC;
    Dbg_RDATA_4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_4 : in STD_LOGIC;
    Dbg_RREADY_4 : out STD_LOGIC;
    Dbg_Disable_5 : out STD_LOGIC;
    Dbg_Clk_5 : out STD_LOGIC;
    Dbg_TDI_5 : out STD_LOGIC;
    Dbg_TDO_5 : in STD_LOGIC;
    Dbg_Reg_En_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_5 : out STD_LOGIC;
    Dbg_Shift_5 : out STD_LOGIC;
    Dbg_Update_5 : out STD_LOGIC;
    Dbg_Rst_5 : out STD_LOGIC;
    Dbg_Trig_In_5 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_5 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_5 : out STD_LOGIC;
    Dbg_TrData_5 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_5 : out STD_LOGIC;
    Dbg_TrValid_5 : in STD_LOGIC;
    Dbg_AWADDR_5 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_5 : out STD_LOGIC;
    Dbg_AWREADY_5 : in STD_LOGIC;
    Dbg_WDATA_5 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_5 : out STD_LOGIC;
    Dbg_WREADY_5 : in STD_LOGIC;
    Dbg_BRESP_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_5 : in STD_LOGIC;
    Dbg_BREADY_5 : out STD_LOGIC;
    Dbg_ARADDR_5 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_5 : out STD_LOGIC;
    Dbg_ARREADY_5 : in STD_LOGIC;
    Dbg_RDATA_5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_5 : in STD_LOGIC;
    Dbg_RREADY_5 : out STD_LOGIC;
    Dbg_Disable_6 : out STD_LOGIC;
    Dbg_Clk_6 : out STD_LOGIC;
    Dbg_TDI_6 : out STD_LOGIC;
    Dbg_TDO_6 : in STD_LOGIC;
    Dbg_Reg_En_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_6 : out STD_LOGIC;
    Dbg_Shift_6 : out STD_LOGIC;
    Dbg_Update_6 : out STD_LOGIC;
    Dbg_Rst_6 : out STD_LOGIC;
    Dbg_Trig_In_6 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_6 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_6 : out STD_LOGIC;
    Dbg_TrData_6 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_6 : out STD_LOGIC;
    Dbg_TrValid_6 : in STD_LOGIC;
    Dbg_AWADDR_6 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_6 : out STD_LOGIC;
    Dbg_AWREADY_6 : in STD_LOGIC;
    Dbg_WDATA_6 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_6 : out STD_LOGIC;
    Dbg_WREADY_6 : in STD_LOGIC;
    Dbg_BRESP_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_6 : in STD_LOGIC;
    Dbg_BREADY_6 : out STD_LOGIC;
    Dbg_ARADDR_6 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_6 : out STD_LOGIC;
    Dbg_ARREADY_6 : in STD_LOGIC;
    Dbg_RDATA_6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_6 : in STD_LOGIC;
    Dbg_RREADY_6 : out STD_LOGIC;
    Dbg_Disable_7 : out STD_LOGIC;
    Dbg_Clk_7 : out STD_LOGIC;
    Dbg_TDI_7 : out STD_LOGIC;
    Dbg_TDO_7 : in STD_LOGIC;
    Dbg_Reg_En_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_7 : out STD_LOGIC;
    Dbg_Shift_7 : out STD_LOGIC;
    Dbg_Update_7 : out STD_LOGIC;
    Dbg_Rst_7 : out STD_LOGIC;
    Dbg_Trig_In_7 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_7 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_7 : out STD_LOGIC;
    Dbg_TrData_7 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_7 : out STD_LOGIC;
    Dbg_TrValid_7 : in STD_LOGIC;
    Dbg_AWADDR_7 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_7 : out STD_LOGIC;
    Dbg_AWREADY_7 : in STD_LOGIC;
    Dbg_WDATA_7 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_7 : out STD_LOGIC;
    Dbg_WREADY_7 : in STD_LOGIC;
    Dbg_BRESP_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_7 : in STD_LOGIC;
    Dbg_BREADY_7 : out STD_LOGIC;
    Dbg_ARADDR_7 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_7 : out STD_LOGIC;
    Dbg_ARREADY_7 : in STD_LOGIC;
    Dbg_RDATA_7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_7 : in STD_LOGIC;
    Dbg_RREADY_7 : out STD_LOGIC;
    Dbg_Disable_8 : out STD_LOGIC;
    Dbg_Clk_8 : out STD_LOGIC;
    Dbg_TDI_8 : out STD_LOGIC;
    Dbg_TDO_8 : in STD_LOGIC;
    Dbg_Reg_En_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_8 : out STD_LOGIC;
    Dbg_Shift_8 : out STD_LOGIC;
    Dbg_Update_8 : out STD_LOGIC;
    Dbg_Rst_8 : out STD_LOGIC;
    Dbg_Trig_In_8 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_8 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_8 : out STD_LOGIC;
    Dbg_TrData_8 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_8 : out STD_LOGIC;
    Dbg_TrValid_8 : in STD_LOGIC;
    Dbg_AWADDR_8 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_8 : out STD_LOGIC;
    Dbg_AWREADY_8 : in STD_LOGIC;
    Dbg_WDATA_8 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_8 : out STD_LOGIC;
    Dbg_WREADY_8 : in STD_LOGIC;
    Dbg_BRESP_8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_8 : in STD_LOGIC;
    Dbg_BREADY_8 : out STD_LOGIC;
    Dbg_ARADDR_8 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_8 : out STD_LOGIC;
    Dbg_ARREADY_8 : in STD_LOGIC;
    Dbg_RDATA_8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_8 : in STD_LOGIC;
    Dbg_RREADY_8 : out STD_LOGIC;
    Dbg_Disable_9 : out STD_LOGIC;
    Dbg_Clk_9 : out STD_LOGIC;
    Dbg_TDI_9 : out STD_LOGIC;
    Dbg_TDO_9 : in STD_LOGIC;
    Dbg_Reg_En_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_9 : out STD_LOGIC;
    Dbg_Shift_9 : out STD_LOGIC;
    Dbg_Update_9 : out STD_LOGIC;
    Dbg_Rst_9 : out STD_LOGIC;
    Dbg_Trig_In_9 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_9 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_9 : out STD_LOGIC;
    Dbg_TrData_9 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_9 : out STD_LOGIC;
    Dbg_TrValid_9 : in STD_LOGIC;
    Dbg_AWADDR_9 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_9 : out STD_LOGIC;
    Dbg_AWREADY_9 : in STD_LOGIC;
    Dbg_WDATA_9 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_9 : out STD_LOGIC;
    Dbg_WREADY_9 : in STD_LOGIC;
    Dbg_BRESP_9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_9 : in STD_LOGIC;
    Dbg_BREADY_9 : out STD_LOGIC;
    Dbg_ARADDR_9 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_9 : out STD_LOGIC;
    Dbg_ARREADY_9 : in STD_LOGIC;
    Dbg_RDATA_9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_9 : in STD_LOGIC;
    Dbg_RREADY_9 : out STD_LOGIC;
    Dbg_Disable_10 : out STD_LOGIC;
    Dbg_Clk_10 : out STD_LOGIC;
    Dbg_TDI_10 : out STD_LOGIC;
    Dbg_TDO_10 : in STD_LOGIC;
    Dbg_Reg_En_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_10 : out STD_LOGIC;
    Dbg_Shift_10 : out STD_LOGIC;
    Dbg_Update_10 : out STD_LOGIC;
    Dbg_Rst_10 : out STD_LOGIC;
    Dbg_Trig_In_10 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_10 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_10 : out STD_LOGIC;
    Dbg_TrData_10 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_10 : out STD_LOGIC;
    Dbg_TrValid_10 : in STD_LOGIC;
    Dbg_AWADDR_10 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_10 : out STD_LOGIC;
    Dbg_AWREADY_10 : in STD_LOGIC;
    Dbg_WDATA_10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_10 : out STD_LOGIC;
    Dbg_WREADY_10 : in STD_LOGIC;
    Dbg_BRESP_10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_10 : in STD_LOGIC;
    Dbg_BREADY_10 : out STD_LOGIC;
    Dbg_ARADDR_10 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_10 : out STD_LOGIC;
    Dbg_ARREADY_10 : in STD_LOGIC;
    Dbg_RDATA_10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_10 : in STD_LOGIC;
    Dbg_RREADY_10 : out STD_LOGIC;
    Dbg_Disable_11 : out STD_LOGIC;
    Dbg_Clk_11 : out STD_LOGIC;
    Dbg_TDI_11 : out STD_LOGIC;
    Dbg_TDO_11 : in STD_LOGIC;
    Dbg_Reg_En_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_11 : out STD_LOGIC;
    Dbg_Shift_11 : out STD_LOGIC;
    Dbg_Update_11 : out STD_LOGIC;
    Dbg_Rst_11 : out STD_LOGIC;
    Dbg_Trig_In_11 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_11 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_11 : out STD_LOGIC;
    Dbg_TrData_11 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_11 : out STD_LOGIC;
    Dbg_TrValid_11 : in STD_LOGIC;
    Dbg_AWADDR_11 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_11 : out STD_LOGIC;
    Dbg_AWREADY_11 : in STD_LOGIC;
    Dbg_WDATA_11 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_11 : out STD_LOGIC;
    Dbg_WREADY_11 : in STD_LOGIC;
    Dbg_BRESP_11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_11 : in STD_LOGIC;
    Dbg_BREADY_11 : out STD_LOGIC;
    Dbg_ARADDR_11 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_11 : out STD_LOGIC;
    Dbg_ARREADY_11 : in STD_LOGIC;
    Dbg_RDATA_11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_11 : in STD_LOGIC;
    Dbg_RREADY_11 : out STD_LOGIC;
    Dbg_Disable_12 : out STD_LOGIC;
    Dbg_Clk_12 : out STD_LOGIC;
    Dbg_TDI_12 : out STD_LOGIC;
    Dbg_TDO_12 : in STD_LOGIC;
    Dbg_Reg_En_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_12 : out STD_LOGIC;
    Dbg_Shift_12 : out STD_LOGIC;
    Dbg_Update_12 : out STD_LOGIC;
    Dbg_Rst_12 : out STD_LOGIC;
    Dbg_Trig_In_12 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_12 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_12 : out STD_LOGIC;
    Dbg_TrData_12 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_12 : out STD_LOGIC;
    Dbg_TrValid_12 : in STD_LOGIC;
    Dbg_AWADDR_12 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_12 : out STD_LOGIC;
    Dbg_AWREADY_12 : in STD_LOGIC;
    Dbg_WDATA_12 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_12 : out STD_LOGIC;
    Dbg_WREADY_12 : in STD_LOGIC;
    Dbg_BRESP_12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_12 : in STD_LOGIC;
    Dbg_BREADY_12 : out STD_LOGIC;
    Dbg_ARADDR_12 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_12 : out STD_LOGIC;
    Dbg_ARREADY_12 : in STD_LOGIC;
    Dbg_RDATA_12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_12 : in STD_LOGIC;
    Dbg_RREADY_12 : out STD_LOGIC;
    Dbg_Disable_13 : out STD_LOGIC;
    Dbg_Clk_13 : out STD_LOGIC;
    Dbg_TDI_13 : out STD_LOGIC;
    Dbg_TDO_13 : in STD_LOGIC;
    Dbg_Reg_En_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_13 : out STD_LOGIC;
    Dbg_Shift_13 : out STD_LOGIC;
    Dbg_Update_13 : out STD_LOGIC;
    Dbg_Rst_13 : out STD_LOGIC;
    Dbg_Trig_In_13 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_13 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_13 : out STD_LOGIC;
    Dbg_TrData_13 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_13 : out STD_LOGIC;
    Dbg_TrValid_13 : in STD_LOGIC;
    Dbg_AWADDR_13 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_13 : out STD_LOGIC;
    Dbg_AWREADY_13 : in STD_LOGIC;
    Dbg_WDATA_13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_13 : out STD_LOGIC;
    Dbg_WREADY_13 : in STD_LOGIC;
    Dbg_BRESP_13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_13 : in STD_LOGIC;
    Dbg_BREADY_13 : out STD_LOGIC;
    Dbg_ARADDR_13 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_13 : out STD_LOGIC;
    Dbg_ARREADY_13 : in STD_LOGIC;
    Dbg_RDATA_13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_13 : in STD_LOGIC;
    Dbg_RREADY_13 : out STD_LOGIC;
    Dbg_Disable_14 : out STD_LOGIC;
    Dbg_Clk_14 : out STD_LOGIC;
    Dbg_TDI_14 : out STD_LOGIC;
    Dbg_TDO_14 : in STD_LOGIC;
    Dbg_Reg_En_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_14 : out STD_LOGIC;
    Dbg_Shift_14 : out STD_LOGIC;
    Dbg_Update_14 : out STD_LOGIC;
    Dbg_Rst_14 : out STD_LOGIC;
    Dbg_Trig_In_14 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_14 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_14 : out STD_LOGIC;
    Dbg_TrData_14 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_14 : out STD_LOGIC;
    Dbg_TrValid_14 : in STD_LOGIC;
    Dbg_AWADDR_14 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_14 : out STD_LOGIC;
    Dbg_AWREADY_14 : in STD_LOGIC;
    Dbg_WDATA_14 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_14 : out STD_LOGIC;
    Dbg_WREADY_14 : in STD_LOGIC;
    Dbg_BRESP_14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_14 : in STD_LOGIC;
    Dbg_BREADY_14 : out STD_LOGIC;
    Dbg_ARADDR_14 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_14 : out STD_LOGIC;
    Dbg_ARREADY_14 : in STD_LOGIC;
    Dbg_RDATA_14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_14 : in STD_LOGIC;
    Dbg_RREADY_14 : out STD_LOGIC;
    Dbg_Disable_15 : out STD_LOGIC;
    Dbg_Clk_15 : out STD_LOGIC;
    Dbg_TDI_15 : out STD_LOGIC;
    Dbg_TDO_15 : in STD_LOGIC;
    Dbg_Reg_En_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_15 : out STD_LOGIC;
    Dbg_Shift_15 : out STD_LOGIC;
    Dbg_Update_15 : out STD_LOGIC;
    Dbg_Rst_15 : out STD_LOGIC;
    Dbg_Trig_In_15 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_15 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_15 : out STD_LOGIC;
    Dbg_TrData_15 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_15 : out STD_LOGIC;
    Dbg_TrValid_15 : in STD_LOGIC;
    Dbg_AWADDR_15 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_15 : out STD_LOGIC;
    Dbg_AWREADY_15 : in STD_LOGIC;
    Dbg_WDATA_15 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_15 : out STD_LOGIC;
    Dbg_WREADY_15 : in STD_LOGIC;
    Dbg_BRESP_15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_15 : in STD_LOGIC;
    Dbg_BREADY_15 : out STD_LOGIC;
    Dbg_ARADDR_15 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_15 : out STD_LOGIC;
    Dbg_ARREADY_15 : in STD_LOGIC;
    Dbg_RDATA_15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_15 : in STD_LOGIC;
    Dbg_RREADY_15 : out STD_LOGIC;
    Dbg_Disable_16 : out STD_LOGIC;
    Dbg_Clk_16 : out STD_LOGIC;
    Dbg_TDI_16 : out STD_LOGIC;
    Dbg_TDO_16 : in STD_LOGIC;
    Dbg_Reg_En_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_16 : out STD_LOGIC;
    Dbg_Shift_16 : out STD_LOGIC;
    Dbg_Update_16 : out STD_LOGIC;
    Dbg_Rst_16 : out STD_LOGIC;
    Dbg_Trig_In_16 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_16 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_16 : out STD_LOGIC;
    Dbg_TrData_16 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_16 : out STD_LOGIC;
    Dbg_TrValid_16 : in STD_LOGIC;
    Dbg_AWADDR_16 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_16 : out STD_LOGIC;
    Dbg_AWREADY_16 : in STD_LOGIC;
    Dbg_WDATA_16 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_16 : out STD_LOGIC;
    Dbg_WREADY_16 : in STD_LOGIC;
    Dbg_BRESP_16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_16 : in STD_LOGIC;
    Dbg_BREADY_16 : out STD_LOGIC;
    Dbg_ARADDR_16 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_16 : out STD_LOGIC;
    Dbg_ARREADY_16 : in STD_LOGIC;
    Dbg_RDATA_16 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_16 : in STD_LOGIC;
    Dbg_RREADY_16 : out STD_LOGIC;
    Dbg_Disable_17 : out STD_LOGIC;
    Dbg_Clk_17 : out STD_LOGIC;
    Dbg_TDI_17 : out STD_LOGIC;
    Dbg_TDO_17 : in STD_LOGIC;
    Dbg_Reg_En_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_17 : out STD_LOGIC;
    Dbg_Shift_17 : out STD_LOGIC;
    Dbg_Update_17 : out STD_LOGIC;
    Dbg_Rst_17 : out STD_LOGIC;
    Dbg_Trig_In_17 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_17 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_17 : out STD_LOGIC;
    Dbg_TrData_17 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_17 : out STD_LOGIC;
    Dbg_TrValid_17 : in STD_LOGIC;
    Dbg_AWADDR_17 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_17 : out STD_LOGIC;
    Dbg_AWREADY_17 : in STD_LOGIC;
    Dbg_WDATA_17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_17 : out STD_LOGIC;
    Dbg_WREADY_17 : in STD_LOGIC;
    Dbg_BRESP_17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_17 : in STD_LOGIC;
    Dbg_BREADY_17 : out STD_LOGIC;
    Dbg_ARADDR_17 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_17 : out STD_LOGIC;
    Dbg_ARREADY_17 : in STD_LOGIC;
    Dbg_RDATA_17 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_17 : in STD_LOGIC;
    Dbg_RREADY_17 : out STD_LOGIC;
    Dbg_Disable_18 : out STD_LOGIC;
    Dbg_Clk_18 : out STD_LOGIC;
    Dbg_TDI_18 : out STD_LOGIC;
    Dbg_TDO_18 : in STD_LOGIC;
    Dbg_Reg_En_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_18 : out STD_LOGIC;
    Dbg_Shift_18 : out STD_LOGIC;
    Dbg_Update_18 : out STD_LOGIC;
    Dbg_Rst_18 : out STD_LOGIC;
    Dbg_Trig_In_18 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_18 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_18 : out STD_LOGIC;
    Dbg_TrData_18 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_18 : out STD_LOGIC;
    Dbg_TrValid_18 : in STD_LOGIC;
    Dbg_AWADDR_18 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_18 : out STD_LOGIC;
    Dbg_AWREADY_18 : in STD_LOGIC;
    Dbg_WDATA_18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_18 : out STD_LOGIC;
    Dbg_WREADY_18 : in STD_LOGIC;
    Dbg_BRESP_18 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_18 : in STD_LOGIC;
    Dbg_BREADY_18 : out STD_LOGIC;
    Dbg_ARADDR_18 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_18 : out STD_LOGIC;
    Dbg_ARREADY_18 : in STD_LOGIC;
    Dbg_RDATA_18 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_18 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_18 : in STD_LOGIC;
    Dbg_RREADY_18 : out STD_LOGIC;
    Dbg_Disable_19 : out STD_LOGIC;
    Dbg_Clk_19 : out STD_LOGIC;
    Dbg_TDI_19 : out STD_LOGIC;
    Dbg_TDO_19 : in STD_LOGIC;
    Dbg_Reg_En_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_19 : out STD_LOGIC;
    Dbg_Shift_19 : out STD_LOGIC;
    Dbg_Update_19 : out STD_LOGIC;
    Dbg_Rst_19 : out STD_LOGIC;
    Dbg_Trig_In_19 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_19 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_19 : out STD_LOGIC;
    Dbg_TrData_19 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_19 : out STD_LOGIC;
    Dbg_TrValid_19 : in STD_LOGIC;
    Dbg_AWADDR_19 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_19 : out STD_LOGIC;
    Dbg_AWREADY_19 : in STD_LOGIC;
    Dbg_WDATA_19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_19 : out STD_LOGIC;
    Dbg_WREADY_19 : in STD_LOGIC;
    Dbg_BRESP_19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_19 : in STD_LOGIC;
    Dbg_BREADY_19 : out STD_LOGIC;
    Dbg_ARADDR_19 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_19 : out STD_LOGIC;
    Dbg_ARREADY_19 : in STD_LOGIC;
    Dbg_RDATA_19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_19 : in STD_LOGIC;
    Dbg_RREADY_19 : out STD_LOGIC;
    Dbg_Disable_20 : out STD_LOGIC;
    Dbg_Clk_20 : out STD_LOGIC;
    Dbg_TDI_20 : out STD_LOGIC;
    Dbg_TDO_20 : in STD_LOGIC;
    Dbg_Reg_En_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_20 : out STD_LOGIC;
    Dbg_Shift_20 : out STD_LOGIC;
    Dbg_Update_20 : out STD_LOGIC;
    Dbg_Rst_20 : out STD_LOGIC;
    Dbg_Trig_In_20 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_20 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_20 : out STD_LOGIC;
    Dbg_TrData_20 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_20 : out STD_LOGIC;
    Dbg_TrValid_20 : in STD_LOGIC;
    Dbg_AWADDR_20 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_20 : out STD_LOGIC;
    Dbg_AWREADY_20 : in STD_LOGIC;
    Dbg_WDATA_20 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_20 : out STD_LOGIC;
    Dbg_WREADY_20 : in STD_LOGIC;
    Dbg_BRESP_20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_20 : in STD_LOGIC;
    Dbg_BREADY_20 : out STD_LOGIC;
    Dbg_ARADDR_20 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_20 : out STD_LOGIC;
    Dbg_ARREADY_20 : in STD_LOGIC;
    Dbg_RDATA_20 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_20 : in STD_LOGIC;
    Dbg_RREADY_20 : out STD_LOGIC;
    Dbg_Disable_21 : out STD_LOGIC;
    Dbg_Clk_21 : out STD_LOGIC;
    Dbg_TDI_21 : out STD_LOGIC;
    Dbg_TDO_21 : in STD_LOGIC;
    Dbg_Reg_En_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_21 : out STD_LOGIC;
    Dbg_Shift_21 : out STD_LOGIC;
    Dbg_Update_21 : out STD_LOGIC;
    Dbg_Rst_21 : out STD_LOGIC;
    Dbg_Trig_In_21 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_21 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_21 : out STD_LOGIC;
    Dbg_TrData_21 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_21 : out STD_LOGIC;
    Dbg_TrValid_21 : in STD_LOGIC;
    Dbg_AWADDR_21 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_21 : out STD_LOGIC;
    Dbg_AWREADY_21 : in STD_LOGIC;
    Dbg_WDATA_21 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_21 : out STD_LOGIC;
    Dbg_WREADY_21 : in STD_LOGIC;
    Dbg_BRESP_21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_21 : in STD_LOGIC;
    Dbg_BREADY_21 : out STD_LOGIC;
    Dbg_ARADDR_21 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_21 : out STD_LOGIC;
    Dbg_ARREADY_21 : in STD_LOGIC;
    Dbg_RDATA_21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_21 : in STD_LOGIC;
    Dbg_RREADY_21 : out STD_LOGIC;
    Dbg_Disable_22 : out STD_LOGIC;
    Dbg_Clk_22 : out STD_LOGIC;
    Dbg_TDI_22 : out STD_LOGIC;
    Dbg_TDO_22 : in STD_LOGIC;
    Dbg_Reg_En_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_22 : out STD_LOGIC;
    Dbg_Shift_22 : out STD_LOGIC;
    Dbg_Update_22 : out STD_LOGIC;
    Dbg_Rst_22 : out STD_LOGIC;
    Dbg_Trig_In_22 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_22 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_22 : out STD_LOGIC;
    Dbg_TrData_22 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_22 : out STD_LOGIC;
    Dbg_TrValid_22 : in STD_LOGIC;
    Dbg_AWADDR_22 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_22 : out STD_LOGIC;
    Dbg_AWREADY_22 : in STD_LOGIC;
    Dbg_WDATA_22 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_22 : out STD_LOGIC;
    Dbg_WREADY_22 : in STD_LOGIC;
    Dbg_BRESP_22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_22 : in STD_LOGIC;
    Dbg_BREADY_22 : out STD_LOGIC;
    Dbg_ARADDR_22 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_22 : out STD_LOGIC;
    Dbg_ARREADY_22 : in STD_LOGIC;
    Dbg_RDATA_22 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_22 : in STD_LOGIC;
    Dbg_RREADY_22 : out STD_LOGIC;
    Dbg_Disable_23 : out STD_LOGIC;
    Dbg_Clk_23 : out STD_LOGIC;
    Dbg_TDI_23 : out STD_LOGIC;
    Dbg_TDO_23 : in STD_LOGIC;
    Dbg_Reg_En_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_23 : out STD_LOGIC;
    Dbg_Shift_23 : out STD_LOGIC;
    Dbg_Update_23 : out STD_LOGIC;
    Dbg_Rst_23 : out STD_LOGIC;
    Dbg_Trig_In_23 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_23 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_23 : out STD_LOGIC;
    Dbg_TrData_23 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_23 : out STD_LOGIC;
    Dbg_TrValid_23 : in STD_LOGIC;
    Dbg_AWADDR_23 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_23 : out STD_LOGIC;
    Dbg_AWREADY_23 : in STD_LOGIC;
    Dbg_WDATA_23 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_23 : out STD_LOGIC;
    Dbg_WREADY_23 : in STD_LOGIC;
    Dbg_BRESP_23 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_23 : in STD_LOGIC;
    Dbg_BREADY_23 : out STD_LOGIC;
    Dbg_ARADDR_23 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_23 : out STD_LOGIC;
    Dbg_ARREADY_23 : in STD_LOGIC;
    Dbg_RDATA_23 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_23 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_23 : in STD_LOGIC;
    Dbg_RREADY_23 : out STD_LOGIC;
    Dbg_Disable_24 : out STD_LOGIC;
    Dbg_Clk_24 : out STD_LOGIC;
    Dbg_TDI_24 : out STD_LOGIC;
    Dbg_TDO_24 : in STD_LOGIC;
    Dbg_Reg_En_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_24 : out STD_LOGIC;
    Dbg_Shift_24 : out STD_LOGIC;
    Dbg_Update_24 : out STD_LOGIC;
    Dbg_Rst_24 : out STD_LOGIC;
    Dbg_Trig_In_24 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_24 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_24 : out STD_LOGIC;
    Dbg_TrData_24 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_24 : out STD_LOGIC;
    Dbg_TrValid_24 : in STD_LOGIC;
    Dbg_AWADDR_24 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_24 : out STD_LOGIC;
    Dbg_AWREADY_24 : in STD_LOGIC;
    Dbg_WDATA_24 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_24 : out STD_LOGIC;
    Dbg_WREADY_24 : in STD_LOGIC;
    Dbg_BRESP_24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_24 : in STD_LOGIC;
    Dbg_BREADY_24 : out STD_LOGIC;
    Dbg_ARADDR_24 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_24 : out STD_LOGIC;
    Dbg_ARREADY_24 : in STD_LOGIC;
    Dbg_RDATA_24 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_24 : in STD_LOGIC;
    Dbg_RREADY_24 : out STD_LOGIC;
    Dbg_Disable_25 : out STD_LOGIC;
    Dbg_Clk_25 : out STD_LOGIC;
    Dbg_TDI_25 : out STD_LOGIC;
    Dbg_TDO_25 : in STD_LOGIC;
    Dbg_Reg_En_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_25 : out STD_LOGIC;
    Dbg_Shift_25 : out STD_LOGIC;
    Dbg_Update_25 : out STD_LOGIC;
    Dbg_Rst_25 : out STD_LOGIC;
    Dbg_Trig_In_25 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_25 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_25 : out STD_LOGIC;
    Dbg_TrData_25 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_25 : out STD_LOGIC;
    Dbg_TrValid_25 : in STD_LOGIC;
    Dbg_AWADDR_25 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_25 : out STD_LOGIC;
    Dbg_AWREADY_25 : in STD_LOGIC;
    Dbg_WDATA_25 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_25 : out STD_LOGIC;
    Dbg_WREADY_25 : in STD_LOGIC;
    Dbg_BRESP_25 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_25 : in STD_LOGIC;
    Dbg_BREADY_25 : out STD_LOGIC;
    Dbg_ARADDR_25 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_25 : out STD_LOGIC;
    Dbg_ARREADY_25 : in STD_LOGIC;
    Dbg_RDATA_25 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_25 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_25 : in STD_LOGIC;
    Dbg_RREADY_25 : out STD_LOGIC;
    Dbg_Disable_26 : out STD_LOGIC;
    Dbg_Clk_26 : out STD_LOGIC;
    Dbg_TDI_26 : out STD_LOGIC;
    Dbg_TDO_26 : in STD_LOGIC;
    Dbg_Reg_En_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_26 : out STD_LOGIC;
    Dbg_Shift_26 : out STD_LOGIC;
    Dbg_Update_26 : out STD_LOGIC;
    Dbg_Rst_26 : out STD_LOGIC;
    Dbg_Trig_In_26 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_26 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_26 : out STD_LOGIC;
    Dbg_TrData_26 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_26 : out STD_LOGIC;
    Dbg_TrValid_26 : in STD_LOGIC;
    Dbg_AWADDR_26 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_26 : out STD_LOGIC;
    Dbg_AWREADY_26 : in STD_LOGIC;
    Dbg_WDATA_26 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_26 : out STD_LOGIC;
    Dbg_WREADY_26 : in STD_LOGIC;
    Dbg_BRESP_26 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_26 : in STD_LOGIC;
    Dbg_BREADY_26 : out STD_LOGIC;
    Dbg_ARADDR_26 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_26 : out STD_LOGIC;
    Dbg_ARREADY_26 : in STD_LOGIC;
    Dbg_RDATA_26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_26 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_26 : in STD_LOGIC;
    Dbg_RREADY_26 : out STD_LOGIC;
    Dbg_Disable_27 : out STD_LOGIC;
    Dbg_Clk_27 : out STD_LOGIC;
    Dbg_TDI_27 : out STD_LOGIC;
    Dbg_TDO_27 : in STD_LOGIC;
    Dbg_Reg_En_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_27 : out STD_LOGIC;
    Dbg_Shift_27 : out STD_LOGIC;
    Dbg_Update_27 : out STD_LOGIC;
    Dbg_Rst_27 : out STD_LOGIC;
    Dbg_Trig_In_27 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_27 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_27 : out STD_LOGIC;
    Dbg_TrData_27 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_27 : out STD_LOGIC;
    Dbg_TrValid_27 : in STD_LOGIC;
    Dbg_AWADDR_27 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_27 : out STD_LOGIC;
    Dbg_AWREADY_27 : in STD_LOGIC;
    Dbg_WDATA_27 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_27 : out STD_LOGIC;
    Dbg_WREADY_27 : in STD_LOGIC;
    Dbg_BRESP_27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_27 : in STD_LOGIC;
    Dbg_BREADY_27 : out STD_LOGIC;
    Dbg_ARADDR_27 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_27 : out STD_LOGIC;
    Dbg_ARREADY_27 : in STD_LOGIC;
    Dbg_RDATA_27 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_27 : in STD_LOGIC;
    Dbg_RREADY_27 : out STD_LOGIC;
    Dbg_Disable_28 : out STD_LOGIC;
    Dbg_Clk_28 : out STD_LOGIC;
    Dbg_TDI_28 : out STD_LOGIC;
    Dbg_TDO_28 : in STD_LOGIC;
    Dbg_Reg_En_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_28 : out STD_LOGIC;
    Dbg_Shift_28 : out STD_LOGIC;
    Dbg_Update_28 : out STD_LOGIC;
    Dbg_Rst_28 : out STD_LOGIC;
    Dbg_Trig_In_28 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_28 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_28 : out STD_LOGIC;
    Dbg_TrData_28 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_28 : out STD_LOGIC;
    Dbg_TrValid_28 : in STD_LOGIC;
    Dbg_AWADDR_28 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_28 : out STD_LOGIC;
    Dbg_AWREADY_28 : in STD_LOGIC;
    Dbg_WDATA_28 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_28 : out STD_LOGIC;
    Dbg_WREADY_28 : in STD_LOGIC;
    Dbg_BRESP_28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_28 : in STD_LOGIC;
    Dbg_BREADY_28 : out STD_LOGIC;
    Dbg_ARADDR_28 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_28 : out STD_LOGIC;
    Dbg_ARREADY_28 : in STD_LOGIC;
    Dbg_RDATA_28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_28 : in STD_LOGIC;
    Dbg_RREADY_28 : out STD_LOGIC;
    Dbg_Disable_29 : out STD_LOGIC;
    Dbg_Clk_29 : out STD_LOGIC;
    Dbg_TDI_29 : out STD_LOGIC;
    Dbg_TDO_29 : in STD_LOGIC;
    Dbg_Reg_En_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_29 : out STD_LOGIC;
    Dbg_Shift_29 : out STD_LOGIC;
    Dbg_Update_29 : out STD_LOGIC;
    Dbg_Rst_29 : out STD_LOGIC;
    Dbg_Trig_In_29 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_29 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_29 : out STD_LOGIC;
    Dbg_TrData_29 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_29 : out STD_LOGIC;
    Dbg_TrValid_29 : in STD_LOGIC;
    Dbg_AWADDR_29 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_29 : out STD_LOGIC;
    Dbg_AWREADY_29 : in STD_LOGIC;
    Dbg_WDATA_29 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_29 : out STD_LOGIC;
    Dbg_WREADY_29 : in STD_LOGIC;
    Dbg_BRESP_29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_29 : in STD_LOGIC;
    Dbg_BREADY_29 : out STD_LOGIC;
    Dbg_ARADDR_29 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_29 : out STD_LOGIC;
    Dbg_ARREADY_29 : in STD_LOGIC;
    Dbg_RDATA_29 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_29 : in STD_LOGIC;
    Dbg_RREADY_29 : out STD_LOGIC;
    Dbg_Disable_30 : out STD_LOGIC;
    Dbg_Clk_30 : out STD_LOGIC;
    Dbg_TDI_30 : out STD_LOGIC;
    Dbg_TDO_30 : in STD_LOGIC;
    Dbg_Reg_En_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_30 : out STD_LOGIC;
    Dbg_Shift_30 : out STD_LOGIC;
    Dbg_Update_30 : out STD_LOGIC;
    Dbg_Rst_30 : out STD_LOGIC;
    Dbg_Trig_In_30 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_30 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_30 : out STD_LOGIC;
    Dbg_TrData_30 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_30 : out STD_LOGIC;
    Dbg_TrValid_30 : in STD_LOGIC;
    Dbg_AWADDR_30 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_30 : out STD_LOGIC;
    Dbg_AWREADY_30 : in STD_LOGIC;
    Dbg_WDATA_30 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_30 : out STD_LOGIC;
    Dbg_WREADY_30 : in STD_LOGIC;
    Dbg_BRESP_30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_30 : in STD_LOGIC;
    Dbg_BREADY_30 : out STD_LOGIC;
    Dbg_ARADDR_30 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_30 : out STD_LOGIC;
    Dbg_ARREADY_30 : in STD_LOGIC;
    Dbg_RDATA_30 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_30 : in STD_LOGIC;
    Dbg_RREADY_30 : out STD_LOGIC;
    Dbg_Disable_31 : out STD_LOGIC;
    Dbg_Clk_31 : out STD_LOGIC;
    Dbg_TDI_31 : out STD_LOGIC;
    Dbg_TDO_31 : in STD_LOGIC;
    Dbg_Reg_En_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_31 : out STD_LOGIC;
    Dbg_Shift_31 : out STD_LOGIC;
    Dbg_Update_31 : out STD_LOGIC;
    Dbg_Rst_31 : out STD_LOGIC;
    Dbg_Trig_In_31 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out_31 : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_TrClk_31 : out STD_LOGIC;
    Dbg_TrData_31 : in STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_TrReady_31 : out STD_LOGIC;
    Dbg_TrValid_31 : in STD_LOGIC;
    Dbg_AWADDR_31 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID_31 : out STD_LOGIC;
    Dbg_AWREADY_31 : in STD_LOGIC;
    Dbg_WDATA_31 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID_31 : out STD_LOGIC;
    Dbg_WREADY_31 : in STD_LOGIC;
    Dbg_BRESP_31 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID_31 : in STD_LOGIC;
    Dbg_BREADY_31 : out STD_LOGIC;
    Dbg_ARADDR_31 : out STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID_31 : out STD_LOGIC;
    Dbg_ARREADY_31 : in STD_LOGIC;
    Dbg_RDATA_31 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP_31 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID_31 : in STD_LOGIC;
    Dbg_RREADY_31 : out STD_LOGIC;
    bscan_ext_tdi : in STD_LOGIC;
    bscan_ext_reset : in STD_LOGIC;
    bscan_ext_shift : in STD_LOGIC;
    bscan_ext_update : in STD_LOGIC;
    bscan_ext_capture : in STD_LOGIC;
    bscan_ext_sel : in STD_LOGIC;
    bscan_ext_drck : in STD_LOGIC;
    bscan_ext_tdo : out STD_LOGIC;
    bscan_ext_tck : in STD_LOGIC;
    bscan_ext_tms : in STD_LOGIC;
    bscan_ext_bscanid_en : in STD_LOGIC;
    Ext_JTAG_DRCK : out STD_LOGIC;
    Ext_JTAG_RESET : out STD_LOGIC;
    Ext_JTAG_SEL : out STD_LOGIC;
    Ext_JTAG_CAPTURE : out STD_LOGIC;
    Ext_JTAG_SHIFT : out STD_LOGIC;
    Ext_JTAG_UPDATE : out STD_LOGIC;
    Ext_JTAG_TDI : out STD_LOGIC;
    Ext_JTAG_TDO : in STD_LOGIC
  );
  attribute C_ADDR_SIZE : integer;
  attribute C_ADDR_SIZE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_AVOID_PRIMITIVES : integer;
  attribute C_AVOID_PRIMITIVES of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_BSCANID : integer;
  attribute C_BSCANID of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_DATA_SIZE : integer;
  attribute C_DATA_SIZE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_DBG_MEM_ACCESS : integer;
  attribute C_DBG_MEM_ACCESS of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_DBG_REG_ACCESS : integer;
  attribute C_DBG_REG_ACCESS of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_DEBUG_INTERFACE : integer;
  attribute C_DEBUG_INTERFACE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_DEVICE : string;
  attribute C_DEVICE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is "xcsu35p";
  attribute C_DTM_IDCODE : integer;
  attribute C_DTM_IDCODE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 147;
  attribute C_EXT_TRIG_RESET_VALUE : string;
  attribute C_EXT_TRIG_RESET_VALUE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is "20'b11110001001000110100";
  attribute C_FAMILY : string;
  attribute C_FAMILY of scu35_io_design_mdm_1_0_MDM_RISCV : entity is "spartanuplus";
  attribute C_INTERCONNECT : integer;
  attribute C_INTERCONNECT of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 2;
  attribute C_JTAG_CHAIN : integer;
  attribute C_JTAG_CHAIN of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 2;
  attribute C_LMB_PROTOCOL : integer;
  attribute C_LMB_PROTOCOL of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_MB_DBG_PORTS : integer;
  attribute C_MB_DBG_PORTS of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 1;
  attribute C_M_AXIS_DATA_WIDTH : integer;
  attribute C_M_AXIS_DATA_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_M_AXIS_ID_WIDTH : integer;
  attribute C_M_AXIS_ID_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 7;
  attribute C_M_AXI_ADDR_WIDTH : integer;
  attribute C_M_AXI_ADDR_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_M_AXI_DATA_WIDTH : integer;
  attribute C_M_AXI_DATA_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_M_AXI_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_THREAD_ID_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 1;
  attribute C_S_AXI_ACLK_FREQ_HZ : integer;
  attribute C_S_AXI_ACLK_FREQ_HZ of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 100000000;
  attribute C_S_AXI_ADDR_WIDTH : integer;
  attribute C_S_AXI_ADDR_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 4;
  attribute C_S_AXI_DATA_WIDTH : integer;
  attribute C_S_AXI_DATA_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_TRACE_ASYNC_RESET : integer;
  attribute C_TRACE_ASYNC_RESET of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_TRACE_CLK_FREQ_HZ : integer;
  attribute C_TRACE_CLK_FREQ_HZ of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 200000000;
  attribute C_TRACE_CLK_OUT_PHASE : integer;
  attribute C_TRACE_CLK_OUT_PHASE of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 90;
  attribute C_TRACE_DATA_WIDTH : integer;
  attribute C_TRACE_DATA_WIDTH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 32;
  attribute C_TRACE_ID : integer;
  attribute C_TRACE_ID of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 110;
  attribute C_TRACE_OUTPUT : integer;
  attribute C_TRACE_OUTPUT of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_TRACE_PROTOCOL : integer;
  attribute C_TRACE_PROTOCOL of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 1;
  attribute C_USE_BSCAN : integer;
  attribute C_USE_BSCAN of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_USE_BSCAN_SWITCH : integer;
  attribute C_USE_BSCAN_SWITCH of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_USE_CONFIG_RESET : integer;
  attribute C_USE_CONFIG_RESET of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_USE_CROSS_TRIGGER : integer;
  attribute C_USE_CROSS_TRIGGER of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute C_USE_JTAG_BSCAN : integer;
  attribute C_USE_JTAG_BSCAN of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 1;
  attribute C_USE_UART : integer;
  attribute C_USE_UART of scu35_io_design_mdm_1_0_MDM_RISCV : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of scu35_io_design_mdm_1_0_MDM_RISCV : entity is "MDM_RISCV";
  attribute bscan_debug_core : string;
  attribute bscan_debug_core of scu35_io_design_mdm_1_0_MDM_RISCV : entity is "FALSE";
  attribute dont_touch : string;
  attribute dont_touch of scu35_io_design_mdm_1_0_MDM_RISCV : entity is "false";
end scu35_io_design_mdm_1_0_MDM_RISCV;

architecture STRUCTURE of scu35_io_design_mdm_1_0_MDM_RISCV is
  signal \<const0>\ : STD_LOGIC;
  signal \^dbg_capture_0\ : STD_LOGIC;
  signal \^dbg_tdi_0\ : STD_LOGIC;
  signal \Internal_BSCANID.bscanid_done\ : STD_LOGIC;
  signal \Internal_BSCANID.bscanid_sel\ : STD_LOGIC;
  signal \JTAG_CONTROL_I/Test_Access_Port.ir\ : STD_LOGIC_VECTOR ( 4 to 4 );
  signal JTAG_TDO : STD_LOGIC;
  signal MDM_Core_I1_n_7 : STD_LOGIC;
  signal TDI : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_0\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_1\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_10\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_11\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_12\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_13\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_14\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_4\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_5\ : STD_LOGIC;
  signal \Use_E2.BSCAN_I_n_8\ : STD_LOGIC;
  signal \Use_E2.LUT1_I_n_0\ : STD_LOGIC;
  signal \Use_E2.LUT1_I_n_1\ : STD_LOGIC;
  signal \Use_E2.LUT1_I_n_4\ : STD_LOGIC;
  signal \Use_E2.LUT1_I_n_5\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bit_cnt\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \Use_JTAG_BSCAN.bit_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bit_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bit_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \Use_JTAG_BSCAN.bscanid\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \Use_JTAG_BSCAN.bscanid__0\ : STD_LOGIC_VECTOR ( 27 downto 1 );
  signal \Use_JTAG_BSCAN.bscanid_reg[12]_Use_JTAG_BSCAN.bscanid_reg_r_6_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg[28]_Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg[2]_Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_gate__0_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_gate__1_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_gate_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_0_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_1_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_3_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_4_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_6_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.bscanid_reg_r_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.id_flag\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.mode_reg__0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \Use_JTAG_BSCAN.tap_cnt_ok\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tck_int\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tms_ok\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tms_ok_reg_n_0\ : STD_LOGIC;
  signal \Use_JTAG_BSCAN.tms_reg_reg_n_0\ : STD_LOGIC;
  signal jtag_tms : STD_LOGIC;
  signal plusOp : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal tck : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[0]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[1]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[2]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[3]_i_1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[4]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[6]_i_1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[7]_i_2\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \Use_JTAG_BSCAN.bit_cnt[7]_i_3\ : label is "soft_lutpair73";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5\ : label is "U0/\Use_JTAG_BSCAN.bscanid_reg ";
  attribute srl_name : string;
  attribute srl_name of \Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5\ : label is "U0/\Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5 ";
  attribute srl_bus_name of \Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1\ : label is "U0/\Use_JTAG_BSCAN.bscanid_reg ";
  attribute srl_name of \Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1\ : label is "U0/\Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1 ";
  attribute srl_bus_name of \Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4\ : label is "U0/\Use_JTAG_BSCAN.bscanid_reg ";
  attribute srl_name of \Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4\ : label is "U0/\Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4 ";
  attribute bscan_debug_interface : string;
  attribute bscan_debug_interface of bscan_ext_capture : signal is "xilinx.com:interface:bscan:1.0 BSCAN CAPTURE";
  attribute dont_touch of bscan_ext_capture : signal is "false";
  attribute bscan_debug_interface of bscan_ext_drck : signal is "xilinx.com:interface:bscan:1.0 BSCAN DRCK";
  attribute dont_touch of bscan_ext_drck : signal is "false";
  attribute bscan_debug_interface of bscan_ext_reset : signal is "xilinx.com:interface:bscan:1.0 BSCAN RESET";
  attribute dont_touch of bscan_ext_reset : signal is "false";
  attribute bscan_debug_interface of bscan_ext_sel : signal is "xilinx.com:interface:bscan:1.0 BSCAN SEL";
  attribute dont_touch of bscan_ext_sel : signal is "false";
  attribute bscan_debug_interface of bscan_ext_shift : signal is "xilinx.com:interface:bscan:1.0 BSCAN SHIFT";
  attribute dont_touch of bscan_ext_shift : signal is "false";
  attribute bscan_debug_interface of bscan_ext_tck : signal is "xilinx.com:interface:bscan:1.0 BSCAN TCK";
  attribute dont_touch of bscan_ext_tck : signal is "false";
  attribute bscan_debug_interface of bscan_ext_tdi : signal is "xilinx.com:interface:bscan:1.0 BSCAN TDI";
  attribute dont_touch of bscan_ext_tdi : signal is "false";
  attribute bscan_debug_interface of bscan_ext_tdo : signal is "xilinx.com:interface:bscan:1.0 BSCAN TDO";
  attribute dont_touch of bscan_ext_tdo : signal is "false";
  attribute bscan_debug_interface of bscan_ext_tms : signal is "xilinx.com:interface:bscan:1.0 BSCAN TMS";
  attribute dont_touch of bscan_ext_tms : signal is "false";
  attribute bscan_debug_interface of bscan_ext_update : signal is "xilinx.com:interface:bscan:1.0 BSCAN UPDATE";
  attribute dont_touch of bscan_ext_update : signal is "false";
begin
  Dbg_ARADDR_0(14) <= \<const0>\;
  Dbg_ARADDR_0(13) <= \<const0>\;
  Dbg_ARADDR_0(12) <= \<const0>\;
  Dbg_ARADDR_0(11) <= \<const0>\;
  Dbg_ARADDR_0(10) <= \<const0>\;
  Dbg_ARADDR_0(9) <= \<const0>\;
  Dbg_ARADDR_0(8) <= \<const0>\;
  Dbg_ARADDR_0(7) <= \<const0>\;
  Dbg_ARADDR_0(6) <= \<const0>\;
  Dbg_ARADDR_0(5) <= \<const0>\;
  Dbg_ARADDR_0(4) <= \<const0>\;
  Dbg_ARADDR_0(3) <= \<const0>\;
  Dbg_ARADDR_0(2) <= \<const0>\;
  Dbg_ARADDR_1(14) <= \<const0>\;
  Dbg_ARADDR_1(13) <= \<const0>\;
  Dbg_ARADDR_1(12) <= \<const0>\;
  Dbg_ARADDR_1(11) <= \<const0>\;
  Dbg_ARADDR_1(10) <= \<const0>\;
  Dbg_ARADDR_1(9) <= \<const0>\;
  Dbg_ARADDR_1(8) <= \<const0>\;
  Dbg_ARADDR_1(7) <= \<const0>\;
  Dbg_ARADDR_1(6) <= \<const0>\;
  Dbg_ARADDR_1(5) <= \<const0>\;
  Dbg_ARADDR_1(4) <= \<const0>\;
  Dbg_ARADDR_1(3) <= \<const0>\;
  Dbg_ARADDR_1(2) <= \<const0>\;
  Dbg_ARADDR_10(14) <= \<const0>\;
  Dbg_ARADDR_10(13) <= \<const0>\;
  Dbg_ARADDR_10(12) <= \<const0>\;
  Dbg_ARADDR_10(11) <= \<const0>\;
  Dbg_ARADDR_10(10) <= \<const0>\;
  Dbg_ARADDR_10(9) <= \<const0>\;
  Dbg_ARADDR_10(8) <= \<const0>\;
  Dbg_ARADDR_10(7) <= \<const0>\;
  Dbg_ARADDR_10(6) <= \<const0>\;
  Dbg_ARADDR_10(5) <= \<const0>\;
  Dbg_ARADDR_10(4) <= \<const0>\;
  Dbg_ARADDR_10(3) <= \<const0>\;
  Dbg_ARADDR_10(2) <= \<const0>\;
  Dbg_ARADDR_11(14) <= \<const0>\;
  Dbg_ARADDR_11(13) <= \<const0>\;
  Dbg_ARADDR_11(12) <= \<const0>\;
  Dbg_ARADDR_11(11) <= \<const0>\;
  Dbg_ARADDR_11(10) <= \<const0>\;
  Dbg_ARADDR_11(9) <= \<const0>\;
  Dbg_ARADDR_11(8) <= \<const0>\;
  Dbg_ARADDR_11(7) <= \<const0>\;
  Dbg_ARADDR_11(6) <= \<const0>\;
  Dbg_ARADDR_11(5) <= \<const0>\;
  Dbg_ARADDR_11(4) <= \<const0>\;
  Dbg_ARADDR_11(3) <= \<const0>\;
  Dbg_ARADDR_11(2) <= \<const0>\;
  Dbg_ARADDR_12(14) <= \<const0>\;
  Dbg_ARADDR_12(13) <= \<const0>\;
  Dbg_ARADDR_12(12) <= \<const0>\;
  Dbg_ARADDR_12(11) <= \<const0>\;
  Dbg_ARADDR_12(10) <= \<const0>\;
  Dbg_ARADDR_12(9) <= \<const0>\;
  Dbg_ARADDR_12(8) <= \<const0>\;
  Dbg_ARADDR_12(7) <= \<const0>\;
  Dbg_ARADDR_12(6) <= \<const0>\;
  Dbg_ARADDR_12(5) <= \<const0>\;
  Dbg_ARADDR_12(4) <= \<const0>\;
  Dbg_ARADDR_12(3) <= \<const0>\;
  Dbg_ARADDR_12(2) <= \<const0>\;
  Dbg_ARADDR_13(14) <= \<const0>\;
  Dbg_ARADDR_13(13) <= \<const0>\;
  Dbg_ARADDR_13(12) <= \<const0>\;
  Dbg_ARADDR_13(11) <= \<const0>\;
  Dbg_ARADDR_13(10) <= \<const0>\;
  Dbg_ARADDR_13(9) <= \<const0>\;
  Dbg_ARADDR_13(8) <= \<const0>\;
  Dbg_ARADDR_13(7) <= \<const0>\;
  Dbg_ARADDR_13(6) <= \<const0>\;
  Dbg_ARADDR_13(5) <= \<const0>\;
  Dbg_ARADDR_13(4) <= \<const0>\;
  Dbg_ARADDR_13(3) <= \<const0>\;
  Dbg_ARADDR_13(2) <= \<const0>\;
  Dbg_ARADDR_14(14) <= \<const0>\;
  Dbg_ARADDR_14(13) <= \<const0>\;
  Dbg_ARADDR_14(12) <= \<const0>\;
  Dbg_ARADDR_14(11) <= \<const0>\;
  Dbg_ARADDR_14(10) <= \<const0>\;
  Dbg_ARADDR_14(9) <= \<const0>\;
  Dbg_ARADDR_14(8) <= \<const0>\;
  Dbg_ARADDR_14(7) <= \<const0>\;
  Dbg_ARADDR_14(6) <= \<const0>\;
  Dbg_ARADDR_14(5) <= \<const0>\;
  Dbg_ARADDR_14(4) <= \<const0>\;
  Dbg_ARADDR_14(3) <= \<const0>\;
  Dbg_ARADDR_14(2) <= \<const0>\;
  Dbg_ARADDR_15(14) <= \<const0>\;
  Dbg_ARADDR_15(13) <= \<const0>\;
  Dbg_ARADDR_15(12) <= \<const0>\;
  Dbg_ARADDR_15(11) <= \<const0>\;
  Dbg_ARADDR_15(10) <= \<const0>\;
  Dbg_ARADDR_15(9) <= \<const0>\;
  Dbg_ARADDR_15(8) <= \<const0>\;
  Dbg_ARADDR_15(7) <= \<const0>\;
  Dbg_ARADDR_15(6) <= \<const0>\;
  Dbg_ARADDR_15(5) <= \<const0>\;
  Dbg_ARADDR_15(4) <= \<const0>\;
  Dbg_ARADDR_15(3) <= \<const0>\;
  Dbg_ARADDR_15(2) <= \<const0>\;
  Dbg_ARADDR_16(14) <= \<const0>\;
  Dbg_ARADDR_16(13) <= \<const0>\;
  Dbg_ARADDR_16(12) <= \<const0>\;
  Dbg_ARADDR_16(11) <= \<const0>\;
  Dbg_ARADDR_16(10) <= \<const0>\;
  Dbg_ARADDR_16(9) <= \<const0>\;
  Dbg_ARADDR_16(8) <= \<const0>\;
  Dbg_ARADDR_16(7) <= \<const0>\;
  Dbg_ARADDR_16(6) <= \<const0>\;
  Dbg_ARADDR_16(5) <= \<const0>\;
  Dbg_ARADDR_16(4) <= \<const0>\;
  Dbg_ARADDR_16(3) <= \<const0>\;
  Dbg_ARADDR_16(2) <= \<const0>\;
  Dbg_ARADDR_17(14) <= \<const0>\;
  Dbg_ARADDR_17(13) <= \<const0>\;
  Dbg_ARADDR_17(12) <= \<const0>\;
  Dbg_ARADDR_17(11) <= \<const0>\;
  Dbg_ARADDR_17(10) <= \<const0>\;
  Dbg_ARADDR_17(9) <= \<const0>\;
  Dbg_ARADDR_17(8) <= \<const0>\;
  Dbg_ARADDR_17(7) <= \<const0>\;
  Dbg_ARADDR_17(6) <= \<const0>\;
  Dbg_ARADDR_17(5) <= \<const0>\;
  Dbg_ARADDR_17(4) <= \<const0>\;
  Dbg_ARADDR_17(3) <= \<const0>\;
  Dbg_ARADDR_17(2) <= \<const0>\;
  Dbg_ARADDR_18(14) <= \<const0>\;
  Dbg_ARADDR_18(13) <= \<const0>\;
  Dbg_ARADDR_18(12) <= \<const0>\;
  Dbg_ARADDR_18(11) <= \<const0>\;
  Dbg_ARADDR_18(10) <= \<const0>\;
  Dbg_ARADDR_18(9) <= \<const0>\;
  Dbg_ARADDR_18(8) <= \<const0>\;
  Dbg_ARADDR_18(7) <= \<const0>\;
  Dbg_ARADDR_18(6) <= \<const0>\;
  Dbg_ARADDR_18(5) <= \<const0>\;
  Dbg_ARADDR_18(4) <= \<const0>\;
  Dbg_ARADDR_18(3) <= \<const0>\;
  Dbg_ARADDR_18(2) <= \<const0>\;
  Dbg_ARADDR_19(14) <= \<const0>\;
  Dbg_ARADDR_19(13) <= \<const0>\;
  Dbg_ARADDR_19(12) <= \<const0>\;
  Dbg_ARADDR_19(11) <= \<const0>\;
  Dbg_ARADDR_19(10) <= \<const0>\;
  Dbg_ARADDR_19(9) <= \<const0>\;
  Dbg_ARADDR_19(8) <= \<const0>\;
  Dbg_ARADDR_19(7) <= \<const0>\;
  Dbg_ARADDR_19(6) <= \<const0>\;
  Dbg_ARADDR_19(5) <= \<const0>\;
  Dbg_ARADDR_19(4) <= \<const0>\;
  Dbg_ARADDR_19(3) <= \<const0>\;
  Dbg_ARADDR_19(2) <= \<const0>\;
  Dbg_ARADDR_2(14) <= \<const0>\;
  Dbg_ARADDR_2(13) <= \<const0>\;
  Dbg_ARADDR_2(12) <= \<const0>\;
  Dbg_ARADDR_2(11) <= \<const0>\;
  Dbg_ARADDR_2(10) <= \<const0>\;
  Dbg_ARADDR_2(9) <= \<const0>\;
  Dbg_ARADDR_2(8) <= \<const0>\;
  Dbg_ARADDR_2(7) <= \<const0>\;
  Dbg_ARADDR_2(6) <= \<const0>\;
  Dbg_ARADDR_2(5) <= \<const0>\;
  Dbg_ARADDR_2(4) <= \<const0>\;
  Dbg_ARADDR_2(3) <= \<const0>\;
  Dbg_ARADDR_2(2) <= \<const0>\;
  Dbg_ARADDR_20(14) <= \<const0>\;
  Dbg_ARADDR_20(13) <= \<const0>\;
  Dbg_ARADDR_20(12) <= \<const0>\;
  Dbg_ARADDR_20(11) <= \<const0>\;
  Dbg_ARADDR_20(10) <= \<const0>\;
  Dbg_ARADDR_20(9) <= \<const0>\;
  Dbg_ARADDR_20(8) <= \<const0>\;
  Dbg_ARADDR_20(7) <= \<const0>\;
  Dbg_ARADDR_20(6) <= \<const0>\;
  Dbg_ARADDR_20(5) <= \<const0>\;
  Dbg_ARADDR_20(4) <= \<const0>\;
  Dbg_ARADDR_20(3) <= \<const0>\;
  Dbg_ARADDR_20(2) <= \<const0>\;
  Dbg_ARADDR_21(14) <= \<const0>\;
  Dbg_ARADDR_21(13) <= \<const0>\;
  Dbg_ARADDR_21(12) <= \<const0>\;
  Dbg_ARADDR_21(11) <= \<const0>\;
  Dbg_ARADDR_21(10) <= \<const0>\;
  Dbg_ARADDR_21(9) <= \<const0>\;
  Dbg_ARADDR_21(8) <= \<const0>\;
  Dbg_ARADDR_21(7) <= \<const0>\;
  Dbg_ARADDR_21(6) <= \<const0>\;
  Dbg_ARADDR_21(5) <= \<const0>\;
  Dbg_ARADDR_21(4) <= \<const0>\;
  Dbg_ARADDR_21(3) <= \<const0>\;
  Dbg_ARADDR_21(2) <= \<const0>\;
  Dbg_ARADDR_22(14) <= \<const0>\;
  Dbg_ARADDR_22(13) <= \<const0>\;
  Dbg_ARADDR_22(12) <= \<const0>\;
  Dbg_ARADDR_22(11) <= \<const0>\;
  Dbg_ARADDR_22(10) <= \<const0>\;
  Dbg_ARADDR_22(9) <= \<const0>\;
  Dbg_ARADDR_22(8) <= \<const0>\;
  Dbg_ARADDR_22(7) <= \<const0>\;
  Dbg_ARADDR_22(6) <= \<const0>\;
  Dbg_ARADDR_22(5) <= \<const0>\;
  Dbg_ARADDR_22(4) <= \<const0>\;
  Dbg_ARADDR_22(3) <= \<const0>\;
  Dbg_ARADDR_22(2) <= \<const0>\;
  Dbg_ARADDR_23(14) <= \<const0>\;
  Dbg_ARADDR_23(13) <= \<const0>\;
  Dbg_ARADDR_23(12) <= \<const0>\;
  Dbg_ARADDR_23(11) <= \<const0>\;
  Dbg_ARADDR_23(10) <= \<const0>\;
  Dbg_ARADDR_23(9) <= \<const0>\;
  Dbg_ARADDR_23(8) <= \<const0>\;
  Dbg_ARADDR_23(7) <= \<const0>\;
  Dbg_ARADDR_23(6) <= \<const0>\;
  Dbg_ARADDR_23(5) <= \<const0>\;
  Dbg_ARADDR_23(4) <= \<const0>\;
  Dbg_ARADDR_23(3) <= \<const0>\;
  Dbg_ARADDR_23(2) <= \<const0>\;
  Dbg_ARADDR_24(14) <= \<const0>\;
  Dbg_ARADDR_24(13) <= \<const0>\;
  Dbg_ARADDR_24(12) <= \<const0>\;
  Dbg_ARADDR_24(11) <= \<const0>\;
  Dbg_ARADDR_24(10) <= \<const0>\;
  Dbg_ARADDR_24(9) <= \<const0>\;
  Dbg_ARADDR_24(8) <= \<const0>\;
  Dbg_ARADDR_24(7) <= \<const0>\;
  Dbg_ARADDR_24(6) <= \<const0>\;
  Dbg_ARADDR_24(5) <= \<const0>\;
  Dbg_ARADDR_24(4) <= \<const0>\;
  Dbg_ARADDR_24(3) <= \<const0>\;
  Dbg_ARADDR_24(2) <= \<const0>\;
  Dbg_ARADDR_25(14) <= \<const0>\;
  Dbg_ARADDR_25(13) <= \<const0>\;
  Dbg_ARADDR_25(12) <= \<const0>\;
  Dbg_ARADDR_25(11) <= \<const0>\;
  Dbg_ARADDR_25(10) <= \<const0>\;
  Dbg_ARADDR_25(9) <= \<const0>\;
  Dbg_ARADDR_25(8) <= \<const0>\;
  Dbg_ARADDR_25(7) <= \<const0>\;
  Dbg_ARADDR_25(6) <= \<const0>\;
  Dbg_ARADDR_25(5) <= \<const0>\;
  Dbg_ARADDR_25(4) <= \<const0>\;
  Dbg_ARADDR_25(3) <= \<const0>\;
  Dbg_ARADDR_25(2) <= \<const0>\;
  Dbg_ARADDR_26(14) <= \<const0>\;
  Dbg_ARADDR_26(13) <= \<const0>\;
  Dbg_ARADDR_26(12) <= \<const0>\;
  Dbg_ARADDR_26(11) <= \<const0>\;
  Dbg_ARADDR_26(10) <= \<const0>\;
  Dbg_ARADDR_26(9) <= \<const0>\;
  Dbg_ARADDR_26(8) <= \<const0>\;
  Dbg_ARADDR_26(7) <= \<const0>\;
  Dbg_ARADDR_26(6) <= \<const0>\;
  Dbg_ARADDR_26(5) <= \<const0>\;
  Dbg_ARADDR_26(4) <= \<const0>\;
  Dbg_ARADDR_26(3) <= \<const0>\;
  Dbg_ARADDR_26(2) <= \<const0>\;
  Dbg_ARADDR_27(14) <= \<const0>\;
  Dbg_ARADDR_27(13) <= \<const0>\;
  Dbg_ARADDR_27(12) <= \<const0>\;
  Dbg_ARADDR_27(11) <= \<const0>\;
  Dbg_ARADDR_27(10) <= \<const0>\;
  Dbg_ARADDR_27(9) <= \<const0>\;
  Dbg_ARADDR_27(8) <= \<const0>\;
  Dbg_ARADDR_27(7) <= \<const0>\;
  Dbg_ARADDR_27(6) <= \<const0>\;
  Dbg_ARADDR_27(5) <= \<const0>\;
  Dbg_ARADDR_27(4) <= \<const0>\;
  Dbg_ARADDR_27(3) <= \<const0>\;
  Dbg_ARADDR_27(2) <= \<const0>\;
  Dbg_ARADDR_28(14) <= \<const0>\;
  Dbg_ARADDR_28(13) <= \<const0>\;
  Dbg_ARADDR_28(12) <= \<const0>\;
  Dbg_ARADDR_28(11) <= \<const0>\;
  Dbg_ARADDR_28(10) <= \<const0>\;
  Dbg_ARADDR_28(9) <= \<const0>\;
  Dbg_ARADDR_28(8) <= \<const0>\;
  Dbg_ARADDR_28(7) <= \<const0>\;
  Dbg_ARADDR_28(6) <= \<const0>\;
  Dbg_ARADDR_28(5) <= \<const0>\;
  Dbg_ARADDR_28(4) <= \<const0>\;
  Dbg_ARADDR_28(3) <= \<const0>\;
  Dbg_ARADDR_28(2) <= \<const0>\;
  Dbg_ARADDR_29(14) <= \<const0>\;
  Dbg_ARADDR_29(13) <= \<const0>\;
  Dbg_ARADDR_29(12) <= \<const0>\;
  Dbg_ARADDR_29(11) <= \<const0>\;
  Dbg_ARADDR_29(10) <= \<const0>\;
  Dbg_ARADDR_29(9) <= \<const0>\;
  Dbg_ARADDR_29(8) <= \<const0>\;
  Dbg_ARADDR_29(7) <= \<const0>\;
  Dbg_ARADDR_29(6) <= \<const0>\;
  Dbg_ARADDR_29(5) <= \<const0>\;
  Dbg_ARADDR_29(4) <= \<const0>\;
  Dbg_ARADDR_29(3) <= \<const0>\;
  Dbg_ARADDR_29(2) <= \<const0>\;
  Dbg_ARADDR_3(14) <= \<const0>\;
  Dbg_ARADDR_3(13) <= \<const0>\;
  Dbg_ARADDR_3(12) <= \<const0>\;
  Dbg_ARADDR_3(11) <= \<const0>\;
  Dbg_ARADDR_3(10) <= \<const0>\;
  Dbg_ARADDR_3(9) <= \<const0>\;
  Dbg_ARADDR_3(8) <= \<const0>\;
  Dbg_ARADDR_3(7) <= \<const0>\;
  Dbg_ARADDR_3(6) <= \<const0>\;
  Dbg_ARADDR_3(5) <= \<const0>\;
  Dbg_ARADDR_3(4) <= \<const0>\;
  Dbg_ARADDR_3(3) <= \<const0>\;
  Dbg_ARADDR_3(2) <= \<const0>\;
  Dbg_ARADDR_30(14) <= \<const0>\;
  Dbg_ARADDR_30(13) <= \<const0>\;
  Dbg_ARADDR_30(12) <= \<const0>\;
  Dbg_ARADDR_30(11) <= \<const0>\;
  Dbg_ARADDR_30(10) <= \<const0>\;
  Dbg_ARADDR_30(9) <= \<const0>\;
  Dbg_ARADDR_30(8) <= \<const0>\;
  Dbg_ARADDR_30(7) <= \<const0>\;
  Dbg_ARADDR_30(6) <= \<const0>\;
  Dbg_ARADDR_30(5) <= \<const0>\;
  Dbg_ARADDR_30(4) <= \<const0>\;
  Dbg_ARADDR_30(3) <= \<const0>\;
  Dbg_ARADDR_30(2) <= \<const0>\;
  Dbg_ARADDR_31(14) <= \<const0>\;
  Dbg_ARADDR_31(13) <= \<const0>\;
  Dbg_ARADDR_31(12) <= \<const0>\;
  Dbg_ARADDR_31(11) <= \<const0>\;
  Dbg_ARADDR_31(10) <= \<const0>\;
  Dbg_ARADDR_31(9) <= \<const0>\;
  Dbg_ARADDR_31(8) <= \<const0>\;
  Dbg_ARADDR_31(7) <= \<const0>\;
  Dbg_ARADDR_31(6) <= \<const0>\;
  Dbg_ARADDR_31(5) <= \<const0>\;
  Dbg_ARADDR_31(4) <= \<const0>\;
  Dbg_ARADDR_31(3) <= \<const0>\;
  Dbg_ARADDR_31(2) <= \<const0>\;
  Dbg_ARADDR_4(14) <= \<const0>\;
  Dbg_ARADDR_4(13) <= \<const0>\;
  Dbg_ARADDR_4(12) <= \<const0>\;
  Dbg_ARADDR_4(11) <= \<const0>\;
  Dbg_ARADDR_4(10) <= \<const0>\;
  Dbg_ARADDR_4(9) <= \<const0>\;
  Dbg_ARADDR_4(8) <= \<const0>\;
  Dbg_ARADDR_4(7) <= \<const0>\;
  Dbg_ARADDR_4(6) <= \<const0>\;
  Dbg_ARADDR_4(5) <= \<const0>\;
  Dbg_ARADDR_4(4) <= \<const0>\;
  Dbg_ARADDR_4(3) <= \<const0>\;
  Dbg_ARADDR_4(2) <= \<const0>\;
  Dbg_ARADDR_5(14) <= \<const0>\;
  Dbg_ARADDR_5(13) <= \<const0>\;
  Dbg_ARADDR_5(12) <= \<const0>\;
  Dbg_ARADDR_5(11) <= \<const0>\;
  Dbg_ARADDR_5(10) <= \<const0>\;
  Dbg_ARADDR_5(9) <= \<const0>\;
  Dbg_ARADDR_5(8) <= \<const0>\;
  Dbg_ARADDR_5(7) <= \<const0>\;
  Dbg_ARADDR_5(6) <= \<const0>\;
  Dbg_ARADDR_5(5) <= \<const0>\;
  Dbg_ARADDR_5(4) <= \<const0>\;
  Dbg_ARADDR_5(3) <= \<const0>\;
  Dbg_ARADDR_5(2) <= \<const0>\;
  Dbg_ARADDR_6(14) <= \<const0>\;
  Dbg_ARADDR_6(13) <= \<const0>\;
  Dbg_ARADDR_6(12) <= \<const0>\;
  Dbg_ARADDR_6(11) <= \<const0>\;
  Dbg_ARADDR_6(10) <= \<const0>\;
  Dbg_ARADDR_6(9) <= \<const0>\;
  Dbg_ARADDR_6(8) <= \<const0>\;
  Dbg_ARADDR_6(7) <= \<const0>\;
  Dbg_ARADDR_6(6) <= \<const0>\;
  Dbg_ARADDR_6(5) <= \<const0>\;
  Dbg_ARADDR_6(4) <= \<const0>\;
  Dbg_ARADDR_6(3) <= \<const0>\;
  Dbg_ARADDR_6(2) <= \<const0>\;
  Dbg_ARADDR_7(14) <= \<const0>\;
  Dbg_ARADDR_7(13) <= \<const0>\;
  Dbg_ARADDR_7(12) <= \<const0>\;
  Dbg_ARADDR_7(11) <= \<const0>\;
  Dbg_ARADDR_7(10) <= \<const0>\;
  Dbg_ARADDR_7(9) <= \<const0>\;
  Dbg_ARADDR_7(8) <= \<const0>\;
  Dbg_ARADDR_7(7) <= \<const0>\;
  Dbg_ARADDR_7(6) <= \<const0>\;
  Dbg_ARADDR_7(5) <= \<const0>\;
  Dbg_ARADDR_7(4) <= \<const0>\;
  Dbg_ARADDR_7(3) <= \<const0>\;
  Dbg_ARADDR_7(2) <= \<const0>\;
  Dbg_ARADDR_8(14) <= \<const0>\;
  Dbg_ARADDR_8(13) <= \<const0>\;
  Dbg_ARADDR_8(12) <= \<const0>\;
  Dbg_ARADDR_8(11) <= \<const0>\;
  Dbg_ARADDR_8(10) <= \<const0>\;
  Dbg_ARADDR_8(9) <= \<const0>\;
  Dbg_ARADDR_8(8) <= \<const0>\;
  Dbg_ARADDR_8(7) <= \<const0>\;
  Dbg_ARADDR_8(6) <= \<const0>\;
  Dbg_ARADDR_8(5) <= \<const0>\;
  Dbg_ARADDR_8(4) <= \<const0>\;
  Dbg_ARADDR_8(3) <= \<const0>\;
  Dbg_ARADDR_8(2) <= \<const0>\;
  Dbg_ARADDR_9(14) <= \<const0>\;
  Dbg_ARADDR_9(13) <= \<const0>\;
  Dbg_ARADDR_9(12) <= \<const0>\;
  Dbg_ARADDR_9(11) <= \<const0>\;
  Dbg_ARADDR_9(10) <= \<const0>\;
  Dbg_ARADDR_9(9) <= \<const0>\;
  Dbg_ARADDR_9(8) <= \<const0>\;
  Dbg_ARADDR_9(7) <= \<const0>\;
  Dbg_ARADDR_9(6) <= \<const0>\;
  Dbg_ARADDR_9(5) <= \<const0>\;
  Dbg_ARADDR_9(4) <= \<const0>\;
  Dbg_ARADDR_9(3) <= \<const0>\;
  Dbg_ARADDR_9(2) <= \<const0>\;
  Dbg_ARVALID_0 <= \<const0>\;
  Dbg_ARVALID_1 <= \<const0>\;
  Dbg_ARVALID_10 <= \<const0>\;
  Dbg_ARVALID_11 <= \<const0>\;
  Dbg_ARVALID_12 <= \<const0>\;
  Dbg_ARVALID_13 <= \<const0>\;
  Dbg_ARVALID_14 <= \<const0>\;
  Dbg_ARVALID_15 <= \<const0>\;
  Dbg_ARVALID_16 <= \<const0>\;
  Dbg_ARVALID_17 <= \<const0>\;
  Dbg_ARVALID_18 <= \<const0>\;
  Dbg_ARVALID_19 <= \<const0>\;
  Dbg_ARVALID_2 <= \<const0>\;
  Dbg_ARVALID_20 <= \<const0>\;
  Dbg_ARVALID_21 <= \<const0>\;
  Dbg_ARVALID_22 <= \<const0>\;
  Dbg_ARVALID_23 <= \<const0>\;
  Dbg_ARVALID_24 <= \<const0>\;
  Dbg_ARVALID_25 <= \<const0>\;
  Dbg_ARVALID_26 <= \<const0>\;
  Dbg_ARVALID_27 <= \<const0>\;
  Dbg_ARVALID_28 <= \<const0>\;
  Dbg_ARVALID_29 <= \<const0>\;
  Dbg_ARVALID_3 <= \<const0>\;
  Dbg_ARVALID_30 <= \<const0>\;
  Dbg_ARVALID_31 <= \<const0>\;
  Dbg_ARVALID_4 <= \<const0>\;
  Dbg_ARVALID_5 <= \<const0>\;
  Dbg_ARVALID_6 <= \<const0>\;
  Dbg_ARVALID_7 <= \<const0>\;
  Dbg_ARVALID_8 <= \<const0>\;
  Dbg_ARVALID_9 <= \<const0>\;
  Dbg_AWADDR_0(14) <= \<const0>\;
  Dbg_AWADDR_0(13) <= \<const0>\;
  Dbg_AWADDR_0(12) <= \<const0>\;
  Dbg_AWADDR_0(11) <= \<const0>\;
  Dbg_AWADDR_0(10) <= \<const0>\;
  Dbg_AWADDR_0(9) <= \<const0>\;
  Dbg_AWADDR_0(8) <= \<const0>\;
  Dbg_AWADDR_0(7) <= \<const0>\;
  Dbg_AWADDR_0(6) <= \<const0>\;
  Dbg_AWADDR_0(5) <= \<const0>\;
  Dbg_AWADDR_0(4) <= \<const0>\;
  Dbg_AWADDR_0(3) <= \<const0>\;
  Dbg_AWADDR_0(2) <= \<const0>\;
  Dbg_AWADDR_1(14) <= \<const0>\;
  Dbg_AWADDR_1(13) <= \<const0>\;
  Dbg_AWADDR_1(12) <= \<const0>\;
  Dbg_AWADDR_1(11) <= \<const0>\;
  Dbg_AWADDR_1(10) <= \<const0>\;
  Dbg_AWADDR_1(9) <= \<const0>\;
  Dbg_AWADDR_1(8) <= \<const0>\;
  Dbg_AWADDR_1(7) <= \<const0>\;
  Dbg_AWADDR_1(6) <= \<const0>\;
  Dbg_AWADDR_1(5) <= \<const0>\;
  Dbg_AWADDR_1(4) <= \<const0>\;
  Dbg_AWADDR_1(3) <= \<const0>\;
  Dbg_AWADDR_1(2) <= \<const0>\;
  Dbg_AWADDR_10(14) <= \<const0>\;
  Dbg_AWADDR_10(13) <= \<const0>\;
  Dbg_AWADDR_10(12) <= \<const0>\;
  Dbg_AWADDR_10(11) <= \<const0>\;
  Dbg_AWADDR_10(10) <= \<const0>\;
  Dbg_AWADDR_10(9) <= \<const0>\;
  Dbg_AWADDR_10(8) <= \<const0>\;
  Dbg_AWADDR_10(7) <= \<const0>\;
  Dbg_AWADDR_10(6) <= \<const0>\;
  Dbg_AWADDR_10(5) <= \<const0>\;
  Dbg_AWADDR_10(4) <= \<const0>\;
  Dbg_AWADDR_10(3) <= \<const0>\;
  Dbg_AWADDR_10(2) <= \<const0>\;
  Dbg_AWADDR_11(14) <= \<const0>\;
  Dbg_AWADDR_11(13) <= \<const0>\;
  Dbg_AWADDR_11(12) <= \<const0>\;
  Dbg_AWADDR_11(11) <= \<const0>\;
  Dbg_AWADDR_11(10) <= \<const0>\;
  Dbg_AWADDR_11(9) <= \<const0>\;
  Dbg_AWADDR_11(8) <= \<const0>\;
  Dbg_AWADDR_11(7) <= \<const0>\;
  Dbg_AWADDR_11(6) <= \<const0>\;
  Dbg_AWADDR_11(5) <= \<const0>\;
  Dbg_AWADDR_11(4) <= \<const0>\;
  Dbg_AWADDR_11(3) <= \<const0>\;
  Dbg_AWADDR_11(2) <= \<const0>\;
  Dbg_AWADDR_12(14) <= \<const0>\;
  Dbg_AWADDR_12(13) <= \<const0>\;
  Dbg_AWADDR_12(12) <= \<const0>\;
  Dbg_AWADDR_12(11) <= \<const0>\;
  Dbg_AWADDR_12(10) <= \<const0>\;
  Dbg_AWADDR_12(9) <= \<const0>\;
  Dbg_AWADDR_12(8) <= \<const0>\;
  Dbg_AWADDR_12(7) <= \<const0>\;
  Dbg_AWADDR_12(6) <= \<const0>\;
  Dbg_AWADDR_12(5) <= \<const0>\;
  Dbg_AWADDR_12(4) <= \<const0>\;
  Dbg_AWADDR_12(3) <= \<const0>\;
  Dbg_AWADDR_12(2) <= \<const0>\;
  Dbg_AWADDR_13(14) <= \<const0>\;
  Dbg_AWADDR_13(13) <= \<const0>\;
  Dbg_AWADDR_13(12) <= \<const0>\;
  Dbg_AWADDR_13(11) <= \<const0>\;
  Dbg_AWADDR_13(10) <= \<const0>\;
  Dbg_AWADDR_13(9) <= \<const0>\;
  Dbg_AWADDR_13(8) <= \<const0>\;
  Dbg_AWADDR_13(7) <= \<const0>\;
  Dbg_AWADDR_13(6) <= \<const0>\;
  Dbg_AWADDR_13(5) <= \<const0>\;
  Dbg_AWADDR_13(4) <= \<const0>\;
  Dbg_AWADDR_13(3) <= \<const0>\;
  Dbg_AWADDR_13(2) <= \<const0>\;
  Dbg_AWADDR_14(14) <= \<const0>\;
  Dbg_AWADDR_14(13) <= \<const0>\;
  Dbg_AWADDR_14(12) <= \<const0>\;
  Dbg_AWADDR_14(11) <= \<const0>\;
  Dbg_AWADDR_14(10) <= \<const0>\;
  Dbg_AWADDR_14(9) <= \<const0>\;
  Dbg_AWADDR_14(8) <= \<const0>\;
  Dbg_AWADDR_14(7) <= \<const0>\;
  Dbg_AWADDR_14(6) <= \<const0>\;
  Dbg_AWADDR_14(5) <= \<const0>\;
  Dbg_AWADDR_14(4) <= \<const0>\;
  Dbg_AWADDR_14(3) <= \<const0>\;
  Dbg_AWADDR_14(2) <= \<const0>\;
  Dbg_AWADDR_15(14) <= \<const0>\;
  Dbg_AWADDR_15(13) <= \<const0>\;
  Dbg_AWADDR_15(12) <= \<const0>\;
  Dbg_AWADDR_15(11) <= \<const0>\;
  Dbg_AWADDR_15(10) <= \<const0>\;
  Dbg_AWADDR_15(9) <= \<const0>\;
  Dbg_AWADDR_15(8) <= \<const0>\;
  Dbg_AWADDR_15(7) <= \<const0>\;
  Dbg_AWADDR_15(6) <= \<const0>\;
  Dbg_AWADDR_15(5) <= \<const0>\;
  Dbg_AWADDR_15(4) <= \<const0>\;
  Dbg_AWADDR_15(3) <= \<const0>\;
  Dbg_AWADDR_15(2) <= \<const0>\;
  Dbg_AWADDR_16(14) <= \<const0>\;
  Dbg_AWADDR_16(13) <= \<const0>\;
  Dbg_AWADDR_16(12) <= \<const0>\;
  Dbg_AWADDR_16(11) <= \<const0>\;
  Dbg_AWADDR_16(10) <= \<const0>\;
  Dbg_AWADDR_16(9) <= \<const0>\;
  Dbg_AWADDR_16(8) <= \<const0>\;
  Dbg_AWADDR_16(7) <= \<const0>\;
  Dbg_AWADDR_16(6) <= \<const0>\;
  Dbg_AWADDR_16(5) <= \<const0>\;
  Dbg_AWADDR_16(4) <= \<const0>\;
  Dbg_AWADDR_16(3) <= \<const0>\;
  Dbg_AWADDR_16(2) <= \<const0>\;
  Dbg_AWADDR_17(14) <= \<const0>\;
  Dbg_AWADDR_17(13) <= \<const0>\;
  Dbg_AWADDR_17(12) <= \<const0>\;
  Dbg_AWADDR_17(11) <= \<const0>\;
  Dbg_AWADDR_17(10) <= \<const0>\;
  Dbg_AWADDR_17(9) <= \<const0>\;
  Dbg_AWADDR_17(8) <= \<const0>\;
  Dbg_AWADDR_17(7) <= \<const0>\;
  Dbg_AWADDR_17(6) <= \<const0>\;
  Dbg_AWADDR_17(5) <= \<const0>\;
  Dbg_AWADDR_17(4) <= \<const0>\;
  Dbg_AWADDR_17(3) <= \<const0>\;
  Dbg_AWADDR_17(2) <= \<const0>\;
  Dbg_AWADDR_18(14) <= \<const0>\;
  Dbg_AWADDR_18(13) <= \<const0>\;
  Dbg_AWADDR_18(12) <= \<const0>\;
  Dbg_AWADDR_18(11) <= \<const0>\;
  Dbg_AWADDR_18(10) <= \<const0>\;
  Dbg_AWADDR_18(9) <= \<const0>\;
  Dbg_AWADDR_18(8) <= \<const0>\;
  Dbg_AWADDR_18(7) <= \<const0>\;
  Dbg_AWADDR_18(6) <= \<const0>\;
  Dbg_AWADDR_18(5) <= \<const0>\;
  Dbg_AWADDR_18(4) <= \<const0>\;
  Dbg_AWADDR_18(3) <= \<const0>\;
  Dbg_AWADDR_18(2) <= \<const0>\;
  Dbg_AWADDR_19(14) <= \<const0>\;
  Dbg_AWADDR_19(13) <= \<const0>\;
  Dbg_AWADDR_19(12) <= \<const0>\;
  Dbg_AWADDR_19(11) <= \<const0>\;
  Dbg_AWADDR_19(10) <= \<const0>\;
  Dbg_AWADDR_19(9) <= \<const0>\;
  Dbg_AWADDR_19(8) <= \<const0>\;
  Dbg_AWADDR_19(7) <= \<const0>\;
  Dbg_AWADDR_19(6) <= \<const0>\;
  Dbg_AWADDR_19(5) <= \<const0>\;
  Dbg_AWADDR_19(4) <= \<const0>\;
  Dbg_AWADDR_19(3) <= \<const0>\;
  Dbg_AWADDR_19(2) <= \<const0>\;
  Dbg_AWADDR_2(14) <= \<const0>\;
  Dbg_AWADDR_2(13) <= \<const0>\;
  Dbg_AWADDR_2(12) <= \<const0>\;
  Dbg_AWADDR_2(11) <= \<const0>\;
  Dbg_AWADDR_2(10) <= \<const0>\;
  Dbg_AWADDR_2(9) <= \<const0>\;
  Dbg_AWADDR_2(8) <= \<const0>\;
  Dbg_AWADDR_2(7) <= \<const0>\;
  Dbg_AWADDR_2(6) <= \<const0>\;
  Dbg_AWADDR_2(5) <= \<const0>\;
  Dbg_AWADDR_2(4) <= \<const0>\;
  Dbg_AWADDR_2(3) <= \<const0>\;
  Dbg_AWADDR_2(2) <= \<const0>\;
  Dbg_AWADDR_20(14) <= \<const0>\;
  Dbg_AWADDR_20(13) <= \<const0>\;
  Dbg_AWADDR_20(12) <= \<const0>\;
  Dbg_AWADDR_20(11) <= \<const0>\;
  Dbg_AWADDR_20(10) <= \<const0>\;
  Dbg_AWADDR_20(9) <= \<const0>\;
  Dbg_AWADDR_20(8) <= \<const0>\;
  Dbg_AWADDR_20(7) <= \<const0>\;
  Dbg_AWADDR_20(6) <= \<const0>\;
  Dbg_AWADDR_20(5) <= \<const0>\;
  Dbg_AWADDR_20(4) <= \<const0>\;
  Dbg_AWADDR_20(3) <= \<const0>\;
  Dbg_AWADDR_20(2) <= \<const0>\;
  Dbg_AWADDR_21(14) <= \<const0>\;
  Dbg_AWADDR_21(13) <= \<const0>\;
  Dbg_AWADDR_21(12) <= \<const0>\;
  Dbg_AWADDR_21(11) <= \<const0>\;
  Dbg_AWADDR_21(10) <= \<const0>\;
  Dbg_AWADDR_21(9) <= \<const0>\;
  Dbg_AWADDR_21(8) <= \<const0>\;
  Dbg_AWADDR_21(7) <= \<const0>\;
  Dbg_AWADDR_21(6) <= \<const0>\;
  Dbg_AWADDR_21(5) <= \<const0>\;
  Dbg_AWADDR_21(4) <= \<const0>\;
  Dbg_AWADDR_21(3) <= \<const0>\;
  Dbg_AWADDR_21(2) <= \<const0>\;
  Dbg_AWADDR_22(14) <= \<const0>\;
  Dbg_AWADDR_22(13) <= \<const0>\;
  Dbg_AWADDR_22(12) <= \<const0>\;
  Dbg_AWADDR_22(11) <= \<const0>\;
  Dbg_AWADDR_22(10) <= \<const0>\;
  Dbg_AWADDR_22(9) <= \<const0>\;
  Dbg_AWADDR_22(8) <= \<const0>\;
  Dbg_AWADDR_22(7) <= \<const0>\;
  Dbg_AWADDR_22(6) <= \<const0>\;
  Dbg_AWADDR_22(5) <= \<const0>\;
  Dbg_AWADDR_22(4) <= \<const0>\;
  Dbg_AWADDR_22(3) <= \<const0>\;
  Dbg_AWADDR_22(2) <= \<const0>\;
  Dbg_AWADDR_23(14) <= \<const0>\;
  Dbg_AWADDR_23(13) <= \<const0>\;
  Dbg_AWADDR_23(12) <= \<const0>\;
  Dbg_AWADDR_23(11) <= \<const0>\;
  Dbg_AWADDR_23(10) <= \<const0>\;
  Dbg_AWADDR_23(9) <= \<const0>\;
  Dbg_AWADDR_23(8) <= \<const0>\;
  Dbg_AWADDR_23(7) <= \<const0>\;
  Dbg_AWADDR_23(6) <= \<const0>\;
  Dbg_AWADDR_23(5) <= \<const0>\;
  Dbg_AWADDR_23(4) <= \<const0>\;
  Dbg_AWADDR_23(3) <= \<const0>\;
  Dbg_AWADDR_23(2) <= \<const0>\;
  Dbg_AWADDR_24(14) <= \<const0>\;
  Dbg_AWADDR_24(13) <= \<const0>\;
  Dbg_AWADDR_24(12) <= \<const0>\;
  Dbg_AWADDR_24(11) <= \<const0>\;
  Dbg_AWADDR_24(10) <= \<const0>\;
  Dbg_AWADDR_24(9) <= \<const0>\;
  Dbg_AWADDR_24(8) <= \<const0>\;
  Dbg_AWADDR_24(7) <= \<const0>\;
  Dbg_AWADDR_24(6) <= \<const0>\;
  Dbg_AWADDR_24(5) <= \<const0>\;
  Dbg_AWADDR_24(4) <= \<const0>\;
  Dbg_AWADDR_24(3) <= \<const0>\;
  Dbg_AWADDR_24(2) <= \<const0>\;
  Dbg_AWADDR_25(14) <= \<const0>\;
  Dbg_AWADDR_25(13) <= \<const0>\;
  Dbg_AWADDR_25(12) <= \<const0>\;
  Dbg_AWADDR_25(11) <= \<const0>\;
  Dbg_AWADDR_25(10) <= \<const0>\;
  Dbg_AWADDR_25(9) <= \<const0>\;
  Dbg_AWADDR_25(8) <= \<const0>\;
  Dbg_AWADDR_25(7) <= \<const0>\;
  Dbg_AWADDR_25(6) <= \<const0>\;
  Dbg_AWADDR_25(5) <= \<const0>\;
  Dbg_AWADDR_25(4) <= \<const0>\;
  Dbg_AWADDR_25(3) <= \<const0>\;
  Dbg_AWADDR_25(2) <= \<const0>\;
  Dbg_AWADDR_26(14) <= \<const0>\;
  Dbg_AWADDR_26(13) <= \<const0>\;
  Dbg_AWADDR_26(12) <= \<const0>\;
  Dbg_AWADDR_26(11) <= \<const0>\;
  Dbg_AWADDR_26(10) <= \<const0>\;
  Dbg_AWADDR_26(9) <= \<const0>\;
  Dbg_AWADDR_26(8) <= \<const0>\;
  Dbg_AWADDR_26(7) <= \<const0>\;
  Dbg_AWADDR_26(6) <= \<const0>\;
  Dbg_AWADDR_26(5) <= \<const0>\;
  Dbg_AWADDR_26(4) <= \<const0>\;
  Dbg_AWADDR_26(3) <= \<const0>\;
  Dbg_AWADDR_26(2) <= \<const0>\;
  Dbg_AWADDR_27(14) <= \<const0>\;
  Dbg_AWADDR_27(13) <= \<const0>\;
  Dbg_AWADDR_27(12) <= \<const0>\;
  Dbg_AWADDR_27(11) <= \<const0>\;
  Dbg_AWADDR_27(10) <= \<const0>\;
  Dbg_AWADDR_27(9) <= \<const0>\;
  Dbg_AWADDR_27(8) <= \<const0>\;
  Dbg_AWADDR_27(7) <= \<const0>\;
  Dbg_AWADDR_27(6) <= \<const0>\;
  Dbg_AWADDR_27(5) <= \<const0>\;
  Dbg_AWADDR_27(4) <= \<const0>\;
  Dbg_AWADDR_27(3) <= \<const0>\;
  Dbg_AWADDR_27(2) <= \<const0>\;
  Dbg_AWADDR_28(14) <= \<const0>\;
  Dbg_AWADDR_28(13) <= \<const0>\;
  Dbg_AWADDR_28(12) <= \<const0>\;
  Dbg_AWADDR_28(11) <= \<const0>\;
  Dbg_AWADDR_28(10) <= \<const0>\;
  Dbg_AWADDR_28(9) <= \<const0>\;
  Dbg_AWADDR_28(8) <= \<const0>\;
  Dbg_AWADDR_28(7) <= \<const0>\;
  Dbg_AWADDR_28(6) <= \<const0>\;
  Dbg_AWADDR_28(5) <= \<const0>\;
  Dbg_AWADDR_28(4) <= \<const0>\;
  Dbg_AWADDR_28(3) <= \<const0>\;
  Dbg_AWADDR_28(2) <= \<const0>\;
  Dbg_AWADDR_29(14) <= \<const0>\;
  Dbg_AWADDR_29(13) <= \<const0>\;
  Dbg_AWADDR_29(12) <= \<const0>\;
  Dbg_AWADDR_29(11) <= \<const0>\;
  Dbg_AWADDR_29(10) <= \<const0>\;
  Dbg_AWADDR_29(9) <= \<const0>\;
  Dbg_AWADDR_29(8) <= \<const0>\;
  Dbg_AWADDR_29(7) <= \<const0>\;
  Dbg_AWADDR_29(6) <= \<const0>\;
  Dbg_AWADDR_29(5) <= \<const0>\;
  Dbg_AWADDR_29(4) <= \<const0>\;
  Dbg_AWADDR_29(3) <= \<const0>\;
  Dbg_AWADDR_29(2) <= \<const0>\;
  Dbg_AWADDR_3(14) <= \<const0>\;
  Dbg_AWADDR_3(13) <= \<const0>\;
  Dbg_AWADDR_3(12) <= \<const0>\;
  Dbg_AWADDR_3(11) <= \<const0>\;
  Dbg_AWADDR_3(10) <= \<const0>\;
  Dbg_AWADDR_3(9) <= \<const0>\;
  Dbg_AWADDR_3(8) <= \<const0>\;
  Dbg_AWADDR_3(7) <= \<const0>\;
  Dbg_AWADDR_3(6) <= \<const0>\;
  Dbg_AWADDR_3(5) <= \<const0>\;
  Dbg_AWADDR_3(4) <= \<const0>\;
  Dbg_AWADDR_3(3) <= \<const0>\;
  Dbg_AWADDR_3(2) <= \<const0>\;
  Dbg_AWADDR_30(14) <= \<const0>\;
  Dbg_AWADDR_30(13) <= \<const0>\;
  Dbg_AWADDR_30(12) <= \<const0>\;
  Dbg_AWADDR_30(11) <= \<const0>\;
  Dbg_AWADDR_30(10) <= \<const0>\;
  Dbg_AWADDR_30(9) <= \<const0>\;
  Dbg_AWADDR_30(8) <= \<const0>\;
  Dbg_AWADDR_30(7) <= \<const0>\;
  Dbg_AWADDR_30(6) <= \<const0>\;
  Dbg_AWADDR_30(5) <= \<const0>\;
  Dbg_AWADDR_30(4) <= \<const0>\;
  Dbg_AWADDR_30(3) <= \<const0>\;
  Dbg_AWADDR_30(2) <= \<const0>\;
  Dbg_AWADDR_31(14) <= \<const0>\;
  Dbg_AWADDR_31(13) <= \<const0>\;
  Dbg_AWADDR_31(12) <= \<const0>\;
  Dbg_AWADDR_31(11) <= \<const0>\;
  Dbg_AWADDR_31(10) <= \<const0>\;
  Dbg_AWADDR_31(9) <= \<const0>\;
  Dbg_AWADDR_31(8) <= \<const0>\;
  Dbg_AWADDR_31(7) <= \<const0>\;
  Dbg_AWADDR_31(6) <= \<const0>\;
  Dbg_AWADDR_31(5) <= \<const0>\;
  Dbg_AWADDR_31(4) <= \<const0>\;
  Dbg_AWADDR_31(3) <= \<const0>\;
  Dbg_AWADDR_31(2) <= \<const0>\;
  Dbg_AWADDR_4(14) <= \<const0>\;
  Dbg_AWADDR_4(13) <= \<const0>\;
  Dbg_AWADDR_4(12) <= \<const0>\;
  Dbg_AWADDR_4(11) <= \<const0>\;
  Dbg_AWADDR_4(10) <= \<const0>\;
  Dbg_AWADDR_4(9) <= \<const0>\;
  Dbg_AWADDR_4(8) <= \<const0>\;
  Dbg_AWADDR_4(7) <= \<const0>\;
  Dbg_AWADDR_4(6) <= \<const0>\;
  Dbg_AWADDR_4(5) <= \<const0>\;
  Dbg_AWADDR_4(4) <= \<const0>\;
  Dbg_AWADDR_4(3) <= \<const0>\;
  Dbg_AWADDR_4(2) <= \<const0>\;
  Dbg_AWADDR_5(14) <= \<const0>\;
  Dbg_AWADDR_5(13) <= \<const0>\;
  Dbg_AWADDR_5(12) <= \<const0>\;
  Dbg_AWADDR_5(11) <= \<const0>\;
  Dbg_AWADDR_5(10) <= \<const0>\;
  Dbg_AWADDR_5(9) <= \<const0>\;
  Dbg_AWADDR_5(8) <= \<const0>\;
  Dbg_AWADDR_5(7) <= \<const0>\;
  Dbg_AWADDR_5(6) <= \<const0>\;
  Dbg_AWADDR_5(5) <= \<const0>\;
  Dbg_AWADDR_5(4) <= \<const0>\;
  Dbg_AWADDR_5(3) <= \<const0>\;
  Dbg_AWADDR_5(2) <= \<const0>\;
  Dbg_AWADDR_6(14) <= \<const0>\;
  Dbg_AWADDR_6(13) <= \<const0>\;
  Dbg_AWADDR_6(12) <= \<const0>\;
  Dbg_AWADDR_6(11) <= \<const0>\;
  Dbg_AWADDR_6(10) <= \<const0>\;
  Dbg_AWADDR_6(9) <= \<const0>\;
  Dbg_AWADDR_6(8) <= \<const0>\;
  Dbg_AWADDR_6(7) <= \<const0>\;
  Dbg_AWADDR_6(6) <= \<const0>\;
  Dbg_AWADDR_6(5) <= \<const0>\;
  Dbg_AWADDR_6(4) <= \<const0>\;
  Dbg_AWADDR_6(3) <= \<const0>\;
  Dbg_AWADDR_6(2) <= \<const0>\;
  Dbg_AWADDR_7(14) <= \<const0>\;
  Dbg_AWADDR_7(13) <= \<const0>\;
  Dbg_AWADDR_7(12) <= \<const0>\;
  Dbg_AWADDR_7(11) <= \<const0>\;
  Dbg_AWADDR_7(10) <= \<const0>\;
  Dbg_AWADDR_7(9) <= \<const0>\;
  Dbg_AWADDR_7(8) <= \<const0>\;
  Dbg_AWADDR_7(7) <= \<const0>\;
  Dbg_AWADDR_7(6) <= \<const0>\;
  Dbg_AWADDR_7(5) <= \<const0>\;
  Dbg_AWADDR_7(4) <= \<const0>\;
  Dbg_AWADDR_7(3) <= \<const0>\;
  Dbg_AWADDR_7(2) <= \<const0>\;
  Dbg_AWADDR_8(14) <= \<const0>\;
  Dbg_AWADDR_8(13) <= \<const0>\;
  Dbg_AWADDR_8(12) <= \<const0>\;
  Dbg_AWADDR_8(11) <= \<const0>\;
  Dbg_AWADDR_8(10) <= \<const0>\;
  Dbg_AWADDR_8(9) <= \<const0>\;
  Dbg_AWADDR_8(8) <= \<const0>\;
  Dbg_AWADDR_8(7) <= \<const0>\;
  Dbg_AWADDR_8(6) <= \<const0>\;
  Dbg_AWADDR_8(5) <= \<const0>\;
  Dbg_AWADDR_8(4) <= \<const0>\;
  Dbg_AWADDR_8(3) <= \<const0>\;
  Dbg_AWADDR_8(2) <= \<const0>\;
  Dbg_AWADDR_9(14) <= \<const0>\;
  Dbg_AWADDR_9(13) <= \<const0>\;
  Dbg_AWADDR_9(12) <= \<const0>\;
  Dbg_AWADDR_9(11) <= \<const0>\;
  Dbg_AWADDR_9(10) <= \<const0>\;
  Dbg_AWADDR_9(9) <= \<const0>\;
  Dbg_AWADDR_9(8) <= \<const0>\;
  Dbg_AWADDR_9(7) <= \<const0>\;
  Dbg_AWADDR_9(6) <= \<const0>\;
  Dbg_AWADDR_9(5) <= \<const0>\;
  Dbg_AWADDR_9(4) <= \<const0>\;
  Dbg_AWADDR_9(3) <= \<const0>\;
  Dbg_AWADDR_9(2) <= \<const0>\;
  Dbg_AWVALID_0 <= \<const0>\;
  Dbg_AWVALID_1 <= \<const0>\;
  Dbg_AWVALID_10 <= \<const0>\;
  Dbg_AWVALID_11 <= \<const0>\;
  Dbg_AWVALID_12 <= \<const0>\;
  Dbg_AWVALID_13 <= \<const0>\;
  Dbg_AWVALID_14 <= \<const0>\;
  Dbg_AWVALID_15 <= \<const0>\;
  Dbg_AWVALID_16 <= \<const0>\;
  Dbg_AWVALID_17 <= \<const0>\;
  Dbg_AWVALID_18 <= \<const0>\;
  Dbg_AWVALID_19 <= \<const0>\;
  Dbg_AWVALID_2 <= \<const0>\;
  Dbg_AWVALID_20 <= \<const0>\;
  Dbg_AWVALID_21 <= \<const0>\;
  Dbg_AWVALID_22 <= \<const0>\;
  Dbg_AWVALID_23 <= \<const0>\;
  Dbg_AWVALID_24 <= \<const0>\;
  Dbg_AWVALID_25 <= \<const0>\;
  Dbg_AWVALID_26 <= \<const0>\;
  Dbg_AWVALID_27 <= \<const0>\;
  Dbg_AWVALID_28 <= \<const0>\;
  Dbg_AWVALID_29 <= \<const0>\;
  Dbg_AWVALID_3 <= \<const0>\;
  Dbg_AWVALID_30 <= \<const0>\;
  Dbg_AWVALID_31 <= \<const0>\;
  Dbg_AWVALID_4 <= \<const0>\;
  Dbg_AWVALID_5 <= \<const0>\;
  Dbg_AWVALID_6 <= \<const0>\;
  Dbg_AWVALID_7 <= \<const0>\;
  Dbg_AWVALID_8 <= \<const0>\;
  Dbg_AWVALID_9 <= \<const0>\;
  Dbg_BREADY_0 <= \<const0>\;
  Dbg_BREADY_1 <= \<const0>\;
  Dbg_BREADY_10 <= \<const0>\;
  Dbg_BREADY_11 <= \<const0>\;
  Dbg_BREADY_12 <= \<const0>\;
  Dbg_BREADY_13 <= \<const0>\;
  Dbg_BREADY_14 <= \<const0>\;
  Dbg_BREADY_15 <= \<const0>\;
  Dbg_BREADY_16 <= \<const0>\;
  Dbg_BREADY_17 <= \<const0>\;
  Dbg_BREADY_18 <= \<const0>\;
  Dbg_BREADY_19 <= \<const0>\;
  Dbg_BREADY_2 <= \<const0>\;
  Dbg_BREADY_20 <= \<const0>\;
  Dbg_BREADY_21 <= \<const0>\;
  Dbg_BREADY_22 <= \<const0>\;
  Dbg_BREADY_23 <= \<const0>\;
  Dbg_BREADY_24 <= \<const0>\;
  Dbg_BREADY_25 <= \<const0>\;
  Dbg_BREADY_26 <= \<const0>\;
  Dbg_BREADY_27 <= \<const0>\;
  Dbg_BREADY_28 <= \<const0>\;
  Dbg_BREADY_29 <= \<const0>\;
  Dbg_BREADY_3 <= \<const0>\;
  Dbg_BREADY_30 <= \<const0>\;
  Dbg_BREADY_31 <= \<const0>\;
  Dbg_BREADY_4 <= \<const0>\;
  Dbg_BREADY_5 <= \<const0>\;
  Dbg_BREADY_6 <= \<const0>\;
  Dbg_BREADY_7 <= \<const0>\;
  Dbg_BREADY_8 <= \<const0>\;
  Dbg_BREADY_9 <= \<const0>\;
  Dbg_Capture_0 <= \^dbg_capture_0\;
  Dbg_Capture_1 <= \<const0>\;
  Dbg_Capture_10 <= \<const0>\;
  Dbg_Capture_11 <= \<const0>\;
  Dbg_Capture_12 <= \<const0>\;
  Dbg_Capture_13 <= \<const0>\;
  Dbg_Capture_14 <= \<const0>\;
  Dbg_Capture_15 <= \<const0>\;
  Dbg_Capture_16 <= \<const0>\;
  Dbg_Capture_17 <= \<const0>\;
  Dbg_Capture_18 <= \<const0>\;
  Dbg_Capture_19 <= \<const0>\;
  Dbg_Capture_2 <= \<const0>\;
  Dbg_Capture_20 <= \<const0>\;
  Dbg_Capture_21 <= \<const0>\;
  Dbg_Capture_22 <= \<const0>\;
  Dbg_Capture_23 <= \<const0>\;
  Dbg_Capture_24 <= \<const0>\;
  Dbg_Capture_25 <= \<const0>\;
  Dbg_Capture_26 <= \<const0>\;
  Dbg_Capture_27 <= \<const0>\;
  Dbg_Capture_28 <= \<const0>\;
  Dbg_Capture_29 <= \<const0>\;
  Dbg_Capture_3 <= \<const0>\;
  Dbg_Capture_30 <= \<const0>\;
  Dbg_Capture_31 <= \<const0>\;
  Dbg_Capture_4 <= \<const0>\;
  Dbg_Capture_5 <= \<const0>\;
  Dbg_Capture_6 <= \<const0>\;
  Dbg_Capture_7 <= \<const0>\;
  Dbg_Capture_8 <= \<const0>\;
  Dbg_Capture_9 <= \<const0>\;
  Dbg_Clk_1 <= \<const0>\;
  Dbg_Clk_10 <= \<const0>\;
  Dbg_Clk_11 <= \<const0>\;
  Dbg_Clk_12 <= \<const0>\;
  Dbg_Clk_13 <= \<const0>\;
  Dbg_Clk_14 <= \<const0>\;
  Dbg_Clk_15 <= \<const0>\;
  Dbg_Clk_16 <= \<const0>\;
  Dbg_Clk_17 <= \<const0>\;
  Dbg_Clk_18 <= \<const0>\;
  Dbg_Clk_19 <= \<const0>\;
  Dbg_Clk_2 <= \<const0>\;
  Dbg_Clk_20 <= \<const0>\;
  Dbg_Clk_21 <= \<const0>\;
  Dbg_Clk_22 <= \<const0>\;
  Dbg_Clk_23 <= \<const0>\;
  Dbg_Clk_24 <= \<const0>\;
  Dbg_Clk_25 <= \<const0>\;
  Dbg_Clk_26 <= \<const0>\;
  Dbg_Clk_27 <= \<const0>\;
  Dbg_Clk_28 <= \<const0>\;
  Dbg_Clk_29 <= \<const0>\;
  Dbg_Clk_3 <= \<const0>\;
  Dbg_Clk_30 <= \<const0>\;
  Dbg_Clk_31 <= \<const0>\;
  Dbg_Clk_4 <= \<const0>\;
  Dbg_Clk_5 <= \<const0>\;
  Dbg_Clk_6 <= \<const0>\;
  Dbg_Clk_7 <= \<const0>\;
  Dbg_Clk_8 <= \<const0>\;
  Dbg_Clk_9 <= \<const0>\;
  Dbg_Disable_0 <= \<const0>\;
  Dbg_Disable_1 <= \<const0>\;
  Dbg_Disable_10 <= \<const0>\;
  Dbg_Disable_11 <= \<const0>\;
  Dbg_Disable_12 <= \<const0>\;
  Dbg_Disable_13 <= \<const0>\;
  Dbg_Disable_14 <= \<const0>\;
  Dbg_Disable_15 <= \<const0>\;
  Dbg_Disable_16 <= \<const0>\;
  Dbg_Disable_17 <= \<const0>\;
  Dbg_Disable_18 <= \<const0>\;
  Dbg_Disable_19 <= \<const0>\;
  Dbg_Disable_2 <= \<const0>\;
  Dbg_Disable_20 <= \<const0>\;
  Dbg_Disable_21 <= \<const0>\;
  Dbg_Disable_22 <= \<const0>\;
  Dbg_Disable_23 <= \<const0>\;
  Dbg_Disable_24 <= \<const0>\;
  Dbg_Disable_25 <= \<const0>\;
  Dbg_Disable_26 <= \<const0>\;
  Dbg_Disable_27 <= \<const0>\;
  Dbg_Disable_28 <= \<const0>\;
  Dbg_Disable_29 <= \<const0>\;
  Dbg_Disable_3 <= \<const0>\;
  Dbg_Disable_30 <= \<const0>\;
  Dbg_Disable_31 <= \<const0>\;
  Dbg_Disable_4 <= \<const0>\;
  Dbg_Disable_5 <= \<const0>\;
  Dbg_Disable_6 <= \<const0>\;
  Dbg_Disable_7 <= \<const0>\;
  Dbg_Disable_8 <= \<const0>\;
  Dbg_Disable_9 <= \<const0>\;
  Dbg_RREADY_0 <= \<const0>\;
  Dbg_RREADY_1 <= \<const0>\;
  Dbg_RREADY_10 <= \<const0>\;
  Dbg_RREADY_11 <= \<const0>\;
  Dbg_RREADY_12 <= \<const0>\;
  Dbg_RREADY_13 <= \<const0>\;
  Dbg_RREADY_14 <= \<const0>\;
  Dbg_RREADY_15 <= \<const0>\;
  Dbg_RREADY_16 <= \<const0>\;
  Dbg_RREADY_17 <= \<const0>\;
  Dbg_RREADY_18 <= \<const0>\;
  Dbg_RREADY_19 <= \<const0>\;
  Dbg_RREADY_2 <= \<const0>\;
  Dbg_RREADY_20 <= \<const0>\;
  Dbg_RREADY_21 <= \<const0>\;
  Dbg_RREADY_22 <= \<const0>\;
  Dbg_RREADY_23 <= \<const0>\;
  Dbg_RREADY_24 <= \<const0>\;
  Dbg_RREADY_25 <= \<const0>\;
  Dbg_RREADY_26 <= \<const0>\;
  Dbg_RREADY_27 <= \<const0>\;
  Dbg_RREADY_28 <= \<const0>\;
  Dbg_RREADY_29 <= \<const0>\;
  Dbg_RREADY_3 <= \<const0>\;
  Dbg_RREADY_30 <= \<const0>\;
  Dbg_RREADY_31 <= \<const0>\;
  Dbg_RREADY_4 <= \<const0>\;
  Dbg_RREADY_5 <= \<const0>\;
  Dbg_RREADY_6 <= \<const0>\;
  Dbg_RREADY_7 <= \<const0>\;
  Dbg_RREADY_8 <= \<const0>\;
  Dbg_RREADY_9 <= \<const0>\;
  Dbg_Reg_En_1(0) <= \<const0>\;
  Dbg_Reg_En_1(1) <= \<const0>\;
  Dbg_Reg_En_1(2) <= \<const0>\;
  Dbg_Reg_En_1(3) <= \<const0>\;
  Dbg_Reg_En_1(4) <= \<const0>\;
  Dbg_Reg_En_1(5) <= \<const0>\;
  Dbg_Reg_En_1(6) <= \<const0>\;
  Dbg_Reg_En_1(7) <= \<const0>\;
  Dbg_Reg_En_10(0) <= \<const0>\;
  Dbg_Reg_En_10(1) <= \<const0>\;
  Dbg_Reg_En_10(2) <= \<const0>\;
  Dbg_Reg_En_10(3) <= \<const0>\;
  Dbg_Reg_En_10(4) <= \<const0>\;
  Dbg_Reg_En_10(5) <= \<const0>\;
  Dbg_Reg_En_10(6) <= \<const0>\;
  Dbg_Reg_En_10(7) <= \<const0>\;
  Dbg_Reg_En_11(0) <= \<const0>\;
  Dbg_Reg_En_11(1) <= \<const0>\;
  Dbg_Reg_En_11(2) <= \<const0>\;
  Dbg_Reg_En_11(3) <= \<const0>\;
  Dbg_Reg_En_11(4) <= \<const0>\;
  Dbg_Reg_En_11(5) <= \<const0>\;
  Dbg_Reg_En_11(6) <= \<const0>\;
  Dbg_Reg_En_11(7) <= \<const0>\;
  Dbg_Reg_En_12(0) <= \<const0>\;
  Dbg_Reg_En_12(1) <= \<const0>\;
  Dbg_Reg_En_12(2) <= \<const0>\;
  Dbg_Reg_En_12(3) <= \<const0>\;
  Dbg_Reg_En_12(4) <= \<const0>\;
  Dbg_Reg_En_12(5) <= \<const0>\;
  Dbg_Reg_En_12(6) <= \<const0>\;
  Dbg_Reg_En_12(7) <= \<const0>\;
  Dbg_Reg_En_13(0) <= \<const0>\;
  Dbg_Reg_En_13(1) <= \<const0>\;
  Dbg_Reg_En_13(2) <= \<const0>\;
  Dbg_Reg_En_13(3) <= \<const0>\;
  Dbg_Reg_En_13(4) <= \<const0>\;
  Dbg_Reg_En_13(5) <= \<const0>\;
  Dbg_Reg_En_13(6) <= \<const0>\;
  Dbg_Reg_En_13(7) <= \<const0>\;
  Dbg_Reg_En_14(0) <= \<const0>\;
  Dbg_Reg_En_14(1) <= \<const0>\;
  Dbg_Reg_En_14(2) <= \<const0>\;
  Dbg_Reg_En_14(3) <= \<const0>\;
  Dbg_Reg_En_14(4) <= \<const0>\;
  Dbg_Reg_En_14(5) <= \<const0>\;
  Dbg_Reg_En_14(6) <= \<const0>\;
  Dbg_Reg_En_14(7) <= \<const0>\;
  Dbg_Reg_En_15(0) <= \<const0>\;
  Dbg_Reg_En_15(1) <= \<const0>\;
  Dbg_Reg_En_15(2) <= \<const0>\;
  Dbg_Reg_En_15(3) <= \<const0>\;
  Dbg_Reg_En_15(4) <= \<const0>\;
  Dbg_Reg_En_15(5) <= \<const0>\;
  Dbg_Reg_En_15(6) <= \<const0>\;
  Dbg_Reg_En_15(7) <= \<const0>\;
  Dbg_Reg_En_16(0) <= \<const0>\;
  Dbg_Reg_En_16(1) <= \<const0>\;
  Dbg_Reg_En_16(2) <= \<const0>\;
  Dbg_Reg_En_16(3) <= \<const0>\;
  Dbg_Reg_En_16(4) <= \<const0>\;
  Dbg_Reg_En_16(5) <= \<const0>\;
  Dbg_Reg_En_16(6) <= \<const0>\;
  Dbg_Reg_En_16(7) <= \<const0>\;
  Dbg_Reg_En_17(0) <= \<const0>\;
  Dbg_Reg_En_17(1) <= \<const0>\;
  Dbg_Reg_En_17(2) <= \<const0>\;
  Dbg_Reg_En_17(3) <= \<const0>\;
  Dbg_Reg_En_17(4) <= \<const0>\;
  Dbg_Reg_En_17(5) <= \<const0>\;
  Dbg_Reg_En_17(6) <= \<const0>\;
  Dbg_Reg_En_17(7) <= \<const0>\;
  Dbg_Reg_En_18(0) <= \<const0>\;
  Dbg_Reg_En_18(1) <= \<const0>\;
  Dbg_Reg_En_18(2) <= \<const0>\;
  Dbg_Reg_En_18(3) <= \<const0>\;
  Dbg_Reg_En_18(4) <= \<const0>\;
  Dbg_Reg_En_18(5) <= \<const0>\;
  Dbg_Reg_En_18(6) <= \<const0>\;
  Dbg_Reg_En_18(7) <= \<const0>\;
  Dbg_Reg_En_19(0) <= \<const0>\;
  Dbg_Reg_En_19(1) <= \<const0>\;
  Dbg_Reg_En_19(2) <= \<const0>\;
  Dbg_Reg_En_19(3) <= \<const0>\;
  Dbg_Reg_En_19(4) <= \<const0>\;
  Dbg_Reg_En_19(5) <= \<const0>\;
  Dbg_Reg_En_19(6) <= \<const0>\;
  Dbg_Reg_En_19(7) <= \<const0>\;
  Dbg_Reg_En_2(0) <= \<const0>\;
  Dbg_Reg_En_2(1) <= \<const0>\;
  Dbg_Reg_En_2(2) <= \<const0>\;
  Dbg_Reg_En_2(3) <= \<const0>\;
  Dbg_Reg_En_2(4) <= \<const0>\;
  Dbg_Reg_En_2(5) <= \<const0>\;
  Dbg_Reg_En_2(6) <= \<const0>\;
  Dbg_Reg_En_2(7) <= \<const0>\;
  Dbg_Reg_En_20(0) <= \<const0>\;
  Dbg_Reg_En_20(1) <= \<const0>\;
  Dbg_Reg_En_20(2) <= \<const0>\;
  Dbg_Reg_En_20(3) <= \<const0>\;
  Dbg_Reg_En_20(4) <= \<const0>\;
  Dbg_Reg_En_20(5) <= \<const0>\;
  Dbg_Reg_En_20(6) <= \<const0>\;
  Dbg_Reg_En_20(7) <= \<const0>\;
  Dbg_Reg_En_21(0) <= \<const0>\;
  Dbg_Reg_En_21(1) <= \<const0>\;
  Dbg_Reg_En_21(2) <= \<const0>\;
  Dbg_Reg_En_21(3) <= \<const0>\;
  Dbg_Reg_En_21(4) <= \<const0>\;
  Dbg_Reg_En_21(5) <= \<const0>\;
  Dbg_Reg_En_21(6) <= \<const0>\;
  Dbg_Reg_En_21(7) <= \<const0>\;
  Dbg_Reg_En_22(0) <= \<const0>\;
  Dbg_Reg_En_22(1) <= \<const0>\;
  Dbg_Reg_En_22(2) <= \<const0>\;
  Dbg_Reg_En_22(3) <= \<const0>\;
  Dbg_Reg_En_22(4) <= \<const0>\;
  Dbg_Reg_En_22(5) <= \<const0>\;
  Dbg_Reg_En_22(6) <= \<const0>\;
  Dbg_Reg_En_22(7) <= \<const0>\;
  Dbg_Reg_En_23(0) <= \<const0>\;
  Dbg_Reg_En_23(1) <= \<const0>\;
  Dbg_Reg_En_23(2) <= \<const0>\;
  Dbg_Reg_En_23(3) <= \<const0>\;
  Dbg_Reg_En_23(4) <= \<const0>\;
  Dbg_Reg_En_23(5) <= \<const0>\;
  Dbg_Reg_En_23(6) <= \<const0>\;
  Dbg_Reg_En_23(7) <= \<const0>\;
  Dbg_Reg_En_24(0) <= \<const0>\;
  Dbg_Reg_En_24(1) <= \<const0>\;
  Dbg_Reg_En_24(2) <= \<const0>\;
  Dbg_Reg_En_24(3) <= \<const0>\;
  Dbg_Reg_En_24(4) <= \<const0>\;
  Dbg_Reg_En_24(5) <= \<const0>\;
  Dbg_Reg_En_24(6) <= \<const0>\;
  Dbg_Reg_En_24(7) <= \<const0>\;
  Dbg_Reg_En_25(0) <= \<const0>\;
  Dbg_Reg_En_25(1) <= \<const0>\;
  Dbg_Reg_En_25(2) <= \<const0>\;
  Dbg_Reg_En_25(3) <= \<const0>\;
  Dbg_Reg_En_25(4) <= \<const0>\;
  Dbg_Reg_En_25(5) <= \<const0>\;
  Dbg_Reg_En_25(6) <= \<const0>\;
  Dbg_Reg_En_25(7) <= \<const0>\;
  Dbg_Reg_En_26(0) <= \<const0>\;
  Dbg_Reg_En_26(1) <= \<const0>\;
  Dbg_Reg_En_26(2) <= \<const0>\;
  Dbg_Reg_En_26(3) <= \<const0>\;
  Dbg_Reg_En_26(4) <= \<const0>\;
  Dbg_Reg_En_26(5) <= \<const0>\;
  Dbg_Reg_En_26(6) <= \<const0>\;
  Dbg_Reg_En_26(7) <= \<const0>\;
  Dbg_Reg_En_27(0) <= \<const0>\;
  Dbg_Reg_En_27(1) <= \<const0>\;
  Dbg_Reg_En_27(2) <= \<const0>\;
  Dbg_Reg_En_27(3) <= \<const0>\;
  Dbg_Reg_En_27(4) <= \<const0>\;
  Dbg_Reg_En_27(5) <= \<const0>\;
  Dbg_Reg_En_27(6) <= \<const0>\;
  Dbg_Reg_En_27(7) <= \<const0>\;
  Dbg_Reg_En_28(0) <= \<const0>\;
  Dbg_Reg_En_28(1) <= \<const0>\;
  Dbg_Reg_En_28(2) <= \<const0>\;
  Dbg_Reg_En_28(3) <= \<const0>\;
  Dbg_Reg_En_28(4) <= \<const0>\;
  Dbg_Reg_En_28(5) <= \<const0>\;
  Dbg_Reg_En_28(6) <= \<const0>\;
  Dbg_Reg_En_28(7) <= \<const0>\;
  Dbg_Reg_En_29(0) <= \<const0>\;
  Dbg_Reg_En_29(1) <= \<const0>\;
  Dbg_Reg_En_29(2) <= \<const0>\;
  Dbg_Reg_En_29(3) <= \<const0>\;
  Dbg_Reg_En_29(4) <= \<const0>\;
  Dbg_Reg_En_29(5) <= \<const0>\;
  Dbg_Reg_En_29(6) <= \<const0>\;
  Dbg_Reg_En_29(7) <= \<const0>\;
  Dbg_Reg_En_3(0) <= \<const0>\;
  Dbg_Reg_En_3(1) <= \<const0>\;
  Dbg_Reg_En_3(2) <= \<const0>\;
  Dbg_Reg_En_3(3) <= \<const0>\;
  Dbg_Reg_En_3(4) <= \<const0>\;
  Dbg_Reg_En_3(5) <= \<const0>\;
  Dbg_Reg_En_3(6) <= \<const0>\;
  Dbg_Reg_En_3(7) <= \<const0>\;
  Dbg_Reg_En_30(0) <= \<const0>\;
  Dbg_Reg_En_30(1) <= \<const0>\;
  Dbg_Reg_En_30(2) <= \<const0>\;
  Dbg_Reg_En_30(3) <= \<const0>\;
  Dbg_Reg_En_30(4) <= \<const0>\;
  Dbg_Reg_En_30(5) <= \<const0>\;
  Dbg_Reg_En_30(6) <= \<const0>\;
  Dbg_Reg_En_30(7) <= \<const0>\;
  Dbg_Reg_En_31(0) <= \<const0>\;
  Dbg_Reg_En_31(1) <= \<const0>\;
  Dbg_Reg_En_31(2) <= \<const0>\;
  Dbg_Reg_En_31(3) <= \<const0>\;
  Dbg_Reg_En_31(4) <= \<const0>\;
  Dbg_Reg_En_31(5) <= \<const0>\;
  Dbg_Reg_En_31(6) <= \<const0>\;
  Dbg_Reg_En_31(7) <= \<const0>\;
  Dbg_Reg_En_4(0) <= \<const0>\;
  Dbg_Reg_En_4(1) <= \<const0>\;
  Dbg_Reg_En_4(2) <= \<const0>\;
  Dbg_Reg_En_4(3) <= \<const0>\;
  Dbg_Reg_En_4(4) <= \<const0>\;
  Dbg_Reg_En_4(5) <= \<const0>\;
  Dbg_Reg_En_4(6) <= \<const0>\;
  Dbg_Reg_En_4(7) <= \<const0>\;
  Dbg_Reg_En_5(0) <= \<const0>\;
  Dbg_Reg_En_5(1) <= \<const0>\;
  Dbg_Reg_En_5(2) <= \<const0>\;
  Dbg_Reg_En_5(3) <= \<const0>\;
  Dbg_Reg_En_5(4) <= \<const0>\;
  Dbg_Reg_En_5(5) <= \<const0>\;
  Dbg_Reg_En_5(6) <= \<const0>\;
  Dbg_Reg_En_5(7) <= \<const0>\;
  Dbg_Reg_En_6(0) <= \<const0>\;
  Dbg_Reg_En_6(1) <= \<const0>\;
  Dbg_Reg_En_6(2) <= \<const0>\;
  Dbg_Reg_En_6(3) <= \<const0>\;
  Dbg_Reg_En_6(4) <= \<const0>\;
  Dbg_Reg_En_6(5) <= \<const0>\;
  Dbg_Reg_En_6(6) <= \<const0>\;
  Dbg_Reg_En_6(7) <= \<const0>\;
  Dbg_Reg_En_7(0) <= \<const0>\;
  Dbg_Reg_En_7(1) <= \<const0>\;
  Dbg_Reg_En_7(2) <= \<const0>\;
  Dbg_Reg_En_7(3) <= \<const0>\;
  Dbg_Reg_En_7(4) <= \<const0>\;
  Dbg_Reg_En_7(5) <= \<const0>\;
  Dbg_Reg_En_7(6) <= \<const0>\;
  Dbg_Reg_En_7(7) <= \<const0>\;
  Dbg_Reg_En_8(0) <= \<const0>\;
  Dbg_Reg_En_8(1) <= \<const0>\;
  Dbg_Reg_En_8(2) <= \<const0>\;
  Dbg_Reg_En_8(3) <= \<const0>\;
  Dbg_Reg_En_8(4) <= \<const0>\;
  Dbg_Reg_En_8(5) <= \<const0>\;
  Dbg_Reg_En_8(6) <= \<const0>\;
  Dbg_Reg_En_8(7) <= \<const0>\;
  Dbg_Reg_En_9(0) <= \<const0>\;
  Dbg_Reg_En_9(1) <= \<const0>\;
  Dbg_Reg_En_9(2) <= \<const0>\;
  Dbg_Reg_En_9(3) <= \<const0>\;
  Dbg_Reg_En_9(4) <= \<const0>\;
  Dbg_Reg_En_9(5) <= \<const0>\;
  Dbg_Reg_En_9(6) <= \<const0>\;
  Dbg_Reg_En_9(7) <= \<const0>\;
  Dbg_Rst_1 <= \<const0>\;
  Dbg_Rst_10 <= \<const0>\;
  Dbg_Rst_11 <= \<const0>\;
  Dbg_Rst_12 <= \<const0>\;
  Dbg_Rst_13 <= \<const0>\;
  Dbg_Rst_14 <= \<const0>\;
  Dbg_Rst_15 <= \<const0>\;
  Dbg_Rst_16 <= \<const0>\;
  Dbg_Rst_17 <= \<const0>\;
  Dbg_Rst_18 <= \<const0>\;
  Dbg_Rst_19 <= \<const0>\;
  Dbg_Rst_2 <= \<const0>\;
  Dbg_Rst_20 <= \<const0>\;
  Dbg_Rst_21 <= \<const0>\;
  Dbg_Rst_22 <= \<const0>\;
  Dbg_Rst_23 <= \<const0>\;
  Dbg_Rst_24 <= \<const0>\;
  Dbg_Rst_25 <= \<const0>\;
  Dbg_Rst_26 <= \<const0>\;
  Dbg_Rst_27 <= \<const0>\;
  Dbg_Rst_28 <= \<const0>\;
  Dbg_Rst_29 <= \<const0>\;
  Dbg_Rst_3 <= \<const0>\;
  Dbg_Rst_30 <= \<const0>\;
  Dbg_Rst_31 <= \<const0>\;
  Dbg_Rst_4 <= \<const0>\;
  Dbg_Rst_5 <= \<const0>\;
  Dbg_Rst_6 <= \<const0>\;
  Dbg_Rst_7 <= \<const0>\;
  Dbg_Rst_8 <= \<const0>\;
  Dbg_Rst_9 <= \<const0>\;
  Dbg_Shift_1 <= \<const0>\;
  Dbg_Shift_10 <= \<const0>\;
  Dbg_Shift_11 <= \<const0>\;
  Dbg_Shift_12 <= \<const0>\;
  Dbg_Shift_13 <= \<const0>\;
  Dbg_Shift_14 <= \<const0>\;
  Dbg_Shift_15 <= \<const0>\;
  Dbg_Shift_16 <= \<const0>\;
  Dbg_Shift_17 <= \<const0>\;
  Dbg_Shift_18 <= \<const0>\;
  Dbg_Shift_19 <= \<const0>\;
  Dbg_Shift_2 <= \<const0>\;
  Dbg_Shift_20 <= \<const0>\;
  Dbg_Shift_21 <= \<const0>\;
  Dbg_Shift_22 <= \<const0>\;
  Dbg_Shift_23 <= \<const0>\;
  Dbg_Shift_24 <= \<const0>\;
  Dbg_Shift_25 <= \<const0>\;
  Dbg_Shift_26 <= \<const0>\;
  Dbg_Shift_27 <= \<const0>\;
  Dbg_Shift_28 <= \<const0>\;
  Dbg_Shift_29 <= \<const0>\;
  Dbg_Shift_3 <= \<const0>\;
  Dbg_Shift_30 <= \<const0>\;
  Dbg_Shift_31 <= \<const0>\;
  Dbg_Shift_4 <= \<const0>\;
  Dbg_Shift_5 <= \<const0>\;
  Dbg_Shift_6 <= \<const0>\;
  Dbg_Shift_7 <= \<const0>\;
  Dbg_Shift_8 <= \<const0>\;
  Dbg_Shift_9 <= \<const0>\;
  Dbg_TDI_0 <= \^dbg_tdi_0\;
  Dbg_TDI_1 <= \^dbg_tdi_0\;
  Dbg_TDI_10 <= \^dbg_tdi_0\;
  Dbg_TDI_11 <= \^dbg_tdi_0\;
  Dbg_TDI_12 <= \^dbg_tdi_0\;
  Dbg_TDI_13 <= \^dbg_tdi_0\;
  Dbg_TDI_14 <= \^dbg_tdi_0\;
  Dbg_TDI_15 <= \^dbg_tdi_0\;
  Dbg_TDI_16 <= \^dbg_tdi_0\;
  Dbg_TDI_17 <= \^dbg_tdi_0\;
  Dbg_TDI_18 <= \^dbg_tdi_0\;
  Dbg_TDI_19 <= \^dbg_tdi_0\;
  Dbg_TDI_2 <= \^dbg_tdi_0\;
  Dbg_TDI_20 <= \^dbg_tdi_0\;
  Dbg_TDI_21 <= \^dbg_tdi_0\;
  Dbg_TDI_22 <= \^dbg_tdi_0\;
  Dbg_TDI_23 <= \^dbg_tdi_0\;
  Dbg_TDI_24 <= \^dbg_tdi_0\;
  Dbg_TDI_25 <= \^dbg_tdi_0\;
  Dbg_TDI_26 <= \^dbg_tdi_0\;
  Dbg_TDI_27 <= \^dbg_tdi_0\;
  Dbg_TDI_28 <= \^dbg_tdi_0\;
  Dbg_TDI_29 <= \^dbg_tdi_0\;
  Dbg_TDI_3 <= \^dbg_tdi_0\;
  Dbg_TDI_30 <= \^dbg_tdi_0\;
  Dbg_TDI_31 <= \^dbg_tdi_0\;
  Dbg_TDI_4 <= \^dbg_tdi_0\;
  Dbg_TDI_5 <= \^dbg_tdi_0\;
  Dbg_TDI_6 <= \^dbg_tdi_0\;
  Dbg_TDI_7 <= \^dbg_tdi_0\;
  Dbg_TDI_8 <= \^dbg_tdi_0\;
  Dbg_TDI_9 <= \^dbg_tdi_0\;
  Dbg_TrClk_0 <= \<const0>\;
  Dbg_TrClk_1 <= \<const0>\;
  Dbg_TrClk_10 <= \<const0>\;
  Dbg_TrClk_11 <= \<const0>\;
  Dbg_TrClk_12 <= \<const0>\;
  Dbg_TrClk_13 <= \<const0>\;
  Dbg_TrClk_14 <= \<const0>\;
  Dbg_TrClk_15 <= \<const0>\;
  Dbg_TrClk_16 <= \<const0>\;
  Dbg_TrClk_17 <= \<const0>\;
  Dbg_TrClk_18 <= \<const0>\;
  Dbg_TrClk_19 <= \<const0>\;
  Dbg_TrClk_2 <= \<const0>\;
  Dbg_TrClk_20 <= \<const0>\;
  Dbg_TrClk_21 <= \<const0>\;
  Dbg_TrClk_22 <= \<const0>\;
  Dbg_TrClk_23 <= \<const0>\;
  Dbg_TrClk_24 <= \<const0>\;
  Dbg_TrClk_25 <= \<const0>\;
  Dbg_TrClk_26 <= \<const0>\;
  Dbg_TrClk_27 <= \<const0>\;
  Dbg_TrClk_28 <= \<const0>\;
  Dbg_TrClk_29 <= \<const0>\;
  Dbg_TrClk_3 <= \<const0>\;
  Dbg_TrClk_30 <= \<const0>\;
  Dbg_TrClk_31 <= \<const0>\;
  Dbg_TrClk_4 <= \<const0>\;
  Dbg_TrClk_5 <= \<const0>\;
  Dbg_TrClk_6 <= \<const0>\;
  Dbg_TrClk_7 <= \<const0>\;
  Dbg_TrClk_8 <= \<const0>\;
  Dbg_TrClk_9 <= \<const0>\;
  Dbg_TrReady_0 <= \<const0>\;
  Dbg_TrReady_1 <= \<const0>\;
  Dbg_TrReady_10 <= \<const0>\;
  Dbg_TrReady_11 <= \<const0>\;
  Dbg_TrReady_12 <= \<const0>\;
  Dbg_TrReady_13 <= \<const0>\;
  Dbg_TrReady_14 <= \<const0>\;
  Dbg_TrReady_15 <= \<const0>\;
  Dbg_TrReady_16 <= \<const0>\;
  Dbg_TrReady_17 <= \<const0>\;
  Dbg_TrReady_18 <= \<const0>\;
  Dbg_TrReady_19 <= \<const0>\;
  Dbg_TrReady_2 <= \<const0>\;
  Dbg_TrReady_20 <= \<const0>\;
  Dbg_TrReady_21 <= \<const0>\;
  Dbg_TrReady_22 <= \<const0>\;
  Dbg_TrReady_23 <= \<const0>\;
  Dbg_TrReady_24 <= \<const0>\;
  Dbg_TrReady_25 <= \<const0>\;
  Dbg_TrReady_26 <= \<const0>\;
  Dbg_TrReady_27 <= \<const0>\;
  Dbg_TrReady_28 <= \<const0>\;
  Dbg_TrReady_29 <= \<const0>\;
  Dbg_TrReady_3 <= \<const0>\;
  Dbg_TrReady_30 <= \<const0>\;
  Dbg_TrReady_31 <= \<const0>\;
  Dbg_TrReady_4 <= \<const0>\;
  Dbg_TrReady_5 <= \<const0>\;
  Dbg_TrReady_6 <= \<const0>\;
  Dbg_TrReady_7 <= \<const0>\;
  Dbg_TrReady_8 <= \<const0>\;
  Dbg_TrReady_9 <= \<const0>\;
  Dbg_Trig_Ack_In_0(0) <= \<const0>\;
  Dbg_Trig_Ack_In_0(1) <= \<const0>\;
  Dbg_Trig_Ack_In_0(2) <= \<const0>\;
  Dbg_Trig_Ack_In_0(3) <= \<const0>\;
  Dbg_Trig_Ack_In_0(4) <= \<const0>\;
  Dbg_Trig_Ack_In_0(5) <= \<const0>\;
  Dbg_Trig_Ack_In_0(6) <= \<const0>\;
  Dbg_Trig_Ack_In_0(7) <= \<const0>\;
  Dbg_Trig_Ack_In_1(0) <= \<const0>\;
  Dbg_Trig_Ack_In_1(1) <= \<const0>\;
  Dbg_Trig_Ack_In_1(2) <= \<const0>\;
  Dbg_Trig_Ack_In_1(3) <= \<const0>\;
  Dbg_Trig_Ack_In_1(4) <= \<const0>\;
  Dbg_Trig_Ack_In_1(5) <= \<const0>\;
  Dbg_Trig_Ack_In_1(6) <= \<const0>\;
  Dbg_Trig_Ack_In_1(7) <= \<const0>\;
  Dbg_Trig_Ack_In_10(0) <= \<const0>\;
  Dbg_Trig_Ack_In_10(1) <= \<const0>\;
  Dbg_Trig_Ack_In_10(2) <= \<const0>\;
  Dbg_Trig_Ack_In_10(3) <= \<const0>\;
  Dbg_Trig_Ack_In_10(4) <= \<const0>\;
  Dbg_Trig_Ack_In_10(5) <= \<const0>\;
  Dbg_Trig_Ack_In_10(6) <= \<const0>\;
  Dbg_Trig_Ack_In_10(7) <= \<const0>\;
  Dbg_Trig_Ack_In_11(0) <= \<const0>\;
  Dbg_Trig_Ack_In_11(1) <= \<const0>\;
  Dbg_Trig_Ack_In_11(2) <= \<const0>\;
  Dbg_Trig_Ack_In_11(3) <= \<const0>\;
  Dbg_Trig_Ack_In_11(4) <= \<const0>\;
  Dbg_Trig_Ack_In_11(5) <= \<const0>\;
  Dbg_Trig_Ack_In_11(6) <= \<const0>\;
  Dbg_Trig_Ack_In_11(7) <= \<const0>\;
  Dbg_Trig_Ack_In_12(0) <= \<const0>\;
  Dbg_Trig_Ack_In_12(1) <= \<const0>\;
  Dbg_Trig_Ack_In_12(2) <= \<const0>\;
  Dbg_Trig_Ack_In_12(3) <= \<const0>\;
  Dbg_Trig_Ack_In_12(4) <= \<const0>\;
  Dbg_Trig_Ack_In_12(5) <= \<const0>\;
  Dbg_Trig_Ack_In_12(6) <= \<const0>\;
  Dbg_Trig_Ack_In_12(7) <= \<const0>\;
  Dbg_Trig_Ack_In_13(0) <= \<const0>\;
  Dbg_Trig_Ack_In_13(1) <= \<const0>\;
  Dbg_Trig_Ack_In_13(2) <= \<const0>\;
  Dbg_Trig_Ack_In_13(3) <= \<const0>\;
  Dbg_Trig_Ack_In_13(4) <= \<const0>\;
  Dbg_Trig_Ack_In_13(5) <= \<const0>\;
  Dbg_Trig_Ack_In_13(6) <= \<const0>\;
  Dbg_Trig_Ack_In_13(7) <= \<const0>\;
  Dbg_Trig_Ack_In_14(0) <= \<const0>\;
  Dbg_Trig_Ack_In_14(1) <= \<const0>\;
  Dbg_Trig_Ack_In_14(2) <= \<const0>\;
  Dbg_Trig_Ack_In_14(3) <= \<const0>\;
  Dbg_Trig_Ack_In_14(4) <= \<const0>\;
  Dbg_Trig_Ack_In_14(5) <= \<const0>\;
  Dbg_Trig_Ack_In_14(6) <= \<const0>\;
  Dbg_Trig_Ack_In_14(7) <= \<const0>\;
  Dbg_Trig_Ack_In_15(0) <= \<const0>\;
  Dbg_Trig_Ack_In_15(1) <= \<const0>\;
  Dbg_Trig_Ack_In_15(2) <= \<const0>\;
  Dbg_Trig_Ack_In_15(3) <= \<const0>\;
  Dbg_Trig_Ack_In_15(4) <= \<const0>\;
  Dbg_Trig_Ack_In_15(5) <= \<const0>\;
  Dbg_Trig_Ack_In_15(6) <= \<const0>\;
  Dbg_Trig_Ack_In_15(7) <= \<const0>\;
  Dbg_Trig_Ack_In_16(0) <= \<const0>\;
  Dbg_Trig_Ack_In_16(1) <= \<const0>\;
  Dbg_Trig_Ack_In_16(2) <= \<const0>\;
  Dbg_Trig_Ack_In_16(3) <= \<const0>\;
  Dbg_Trig_Ack_In_16(4) <= \<const0>\;
  Dbg_Trig_Ack_In_16(5) <= \<const0>\;
  Dbg_Trig_Ack_In_16(6) <= \<const0>\;
  Dbg_Trig_Ack_In_16(7) <= \<const0>\;
  Dbg_Trig_Ack_In_17(0) <= \<const0>\;
  Dbg_Trig_Ack_In_17(1) <= \<const0>\;
  Dbg_Trig_Ack_In_17(2) <= \<const0>\;
  Dbg_Trig_Ack_In_17(3) <= \<const0>\;
  Dbg_Trig_Ack_In_17(4) <= \<const0>\;
  Dbg_Trig_Ack_In_17(5) <= \<const0>\;
  Dbg_Trig_Ack_In_17(6) <= \<const0>\;
  Dbg_Trig_Ack_In_17(7) <= \<const0>\;
  Dbg_Trig_Ack_In_18(0) <= \<const0>\;
  Dbg_Trig_Ack_In_18(1) <= \<const0>\;
  Dbg_Trig_Ack_In_18(2) <= \<const0>\;
  Dbg_Trig_Ack_In_18(3) <= \<const0>\;
  Dbg_Trig_Ack_In_18(4) <= \<const0>\;
  Dbg_Trig_Ack_In_18(5) <= \<const0>\;
  Dbg_Trig_Ack_In_18(6) <= \<const0>\;
  Dbg_Trig_Ack_In_18(7) <= \<const0>\;
  Dbg_Trig_Ack_In_19(0) <= \<const0>\;
  Dbg_Trig_Ack_In_19(1) <= \<const0>\;
  Dbg_Trig_Ack_In_19(2) <= \<const0>\;
  Dbg_Trig_Ack_In_19(3) <= \<const0>\;
  Dbg_Trig_Ack_In_19(4) <= \<const0>\;
  Dbg_Trig_Ack_In_19(5) <= \<const0>\;
  Dbg_Trig_Ack_In_19(6) <= \<const0>\;
  Dbg_Trig_Ack_In_19(7) <= \<const0>\;
  Dbg_Trig_Ack_In_2(0) <= \<const0>\;
  Dbg_Trig_Ack_In_2(1) <= \<const0>\;
  Dbg_Trig_Ack_In_2(2) <= \<const0>\;
  Dbg_Trig_Ack_In_2(3) <= \<const0>\;
  Dbg_Trig_Ack_In_2(4) <= \<const0>\;
  Dbg_Trig_Ack_In_2(5) <= \<const0>\;
  Dbg_Trig_Ack_In_2(6) <= \<const0>\;
  Dbg_Trig_Ack_In_2(7) <= \<const0>\;
  Dbg_Trig_Ack_In_20(0) <= \<const0>\;
  Dbg_Trig_Ack_In_20(1) <= \<const0>\;
  Dbg_Trig_Ack_In_20(2) <= \<const0>\;
  Dbg_Trig_Ack_In_20(3) <= \<const0>\;
  Dbg_Trig_Ack_In_20(4) <= \<const0>\;
  Dbg_Trig_Ack_In_20(5) <= \<const0>\;
  Dbg_Trig_Ack_In_20(6) <= \<const0>\;
  Dbg_Trig_Ack_In_20(7) <= \<const0>\;
  Dbg_Trig_Ack_In_21(0) <= \<const0>\;
  Dbg_Trig_Ack_In_21(1) <= \<const0>\;
  Dbg_Trig_Ack_In_21(2) <= \<const0>\;
  Dbg_Trig_Ack_In_21(3) <= \<const0>\;
  Dbg_Trig_Ack_In_21(4) <= \<const0>\;
  Dbg_Trig_Ack_In_21(5) <= \<const0>\;
  Dbg_Trig_Ack_In_21(6) <= \<const0>\;
  Dbg_Trig_Ack_In_21(7) <= \<const0>\;
  Dbg_Trig_Ack_In_22(0) <= \<const0>\;
  Dbg_Trig_Ack_In_22(1) <= \<const0>\;
  Dbg_Trig_Ack_In_22(2) <= \<const0>\;
  Dbg_Trig_Ack_In_22(3) <= \<const0>\;
  Dbg_Trig_Ack_In_22(4) <= \<const0>\;
  Dbg_Trig_Ack_In_22(5) <= \<const0>\;
  Dbg_Trig_Ack_In_22(6) <= \<const0>\;
  Dbg_Trig_Ack_In_22(7) <= \<const0>\;
  Dbg_Trig_Ack_In_23(0) <= \<const0>\;
  Dbg_Trig_Ack_In_23(1) <= \<const0>\;
  Dbg_Trig_Ack_In_23(2) <= \<const0>\;
  Dbg_Trig_Ack_In_23(3) <= \<const0>\;
  Dbg_Trig_Ack_In_23(4) <= \<const0>\;
  Dbg_Trig_Ack_In_23(5) <= \<const0>\;
  Dbg_Trig_Ack_In_23(6) <= \<const0>\;
  Dbg_Trig_Ack_In_23(7) <= \<const0>\;
  Dbg_Trig_Ack_In_24(0) <= \<const0>\;
  Dbg_Trig_Ack_In_24(1) <= \<const0>\;
  Dbg_Trig_Ack_In_24(2) <= \<const0>\;
  Dbg_Trig_Ack_In_24(3) <= \<const0>\;
  Dbg_Trig_Ack_In_24(4) <= \<const0>\;
  Dbg_Trig_Ack_In_24(5) <= \<const0>\;
  Dbg_Trig_Ack_In_24(6) <= \<const0>\;
  Dbg_Trig_Ack_In_24(7) <= \<const0>\;
  Dbg_Trig_Ack_In_25(0) <= \<const0>\;
  Dbg_Trig_Ack_In_25(1) <= \<const0>\;
  Dbg_Trig_Ack_In_25(2) <= \<const0>\;
  Dbg_Trig_Ack_In_25(3) <= \<const0>\;
  Dbg_Trig_Ack_In_25(4) <= \<const0>\;
  Dbg_Trig_Ack_In_25(5) <= \<const0>\;
  Dbg_Trig_Ack_In_25(6) <= \<const0>\;
  Dbg_Trig_Ack_In_25(7) <= \<const0>\;
  Dbg_Trig_Ack_In_26(0) <= \<const0>\;
  Dbg_Trig_Ack_In_26(1) <= \<const0>\;
  Dbg_Trig_Ack_In_26(2) <= \<const0>\;
  Dbg_Trig_Ack_In_26(3) <= \<const0>\;
  Dbg_Trig_Ack_In_26(4) <= \<const0>\;
  Dbg_Trig_Ack_In_26(5) <= \<const0>\;
  Dbg_Trig_Ack_In_26(6) <= \<const0>\;
  Dbg_Trig_Ack_In_26(7) <= \<const0>\;
  Dbg_Trig_Ack_In_27(0) <= \<const0>\;
  Dbg_Trig_Ack_In_27(1) <= \<const0>\;
  Dbg_Trig_Ack_In_27(2) <= \<const0>\;
  Dbg_Trig_Ack_In_27(3) <= \<const0>\;
  Dbg_Trig_Ack_In_27(4) <= \<const0>\;
  Dbg_Trig_Ack_In_27(5) <= \<const0>\;
  Dbg_Trig_Ack_In_27(6) <= \<const0>\;
  Dbg_Trig_Ack_In_27(7) <= \<const0>\;
  Dbg_Trig_Ack_In_28(0) <= \<const0>\;
  Dbg_Trig_Ack_In_28(1) <= \<const0>\;
  Dbg_Trig_Ack_In_28(2) <= \<const0>\;
  Dbg_Trig_Ack_In_28(3) <= \<const0>\;
  Dbg_Trig_Ack_In_28(4) <= \<const0>\;
  Dbg_Trig_Ack_In_28(5) <= \<const0>\;
  Dbg_Trig_Ack_In_28(6) <= \<const0>\;
  Dbg_Trig_Ack_In_28(7) <= \<const0>\;
  Dbg_Trig_Ack_In_29(0) <= \<const0>\;
  Dbg_Trig_Ack_In_29(1) <= \<const0>\;
  Dbg_Trig_Ack_In_29(2) <= \<const0>\;
  Dbg_Trig_Ack_In_29(3) <= \<const0>\;
  Dbg_Trig_Ack_In_29(4) <= \<const0>\;
  Dbg_Trig_Ack_In_29(5) <= \<const0>\;
  Dbg_Trig_Ack_In_29(6) <= \<const0>\;
  Dbg_Trig_Ack_In_29(7) <= \<const0>\;
  Dbg_Trig_Ack_In_3(0) <= \<const0>\;
  Dbg_Trig_Ack_In_3(1) <= \<const0>\;
  Dbg_Trig_Ack_In_3(2) <= \<const0>\;
  Dbg_Trig_Ack_In_3(3) <= \<const0>\;
  Dbg_Trig_Ack_In_3(4) <= \<const0>\;
  Dbg_Trig_Ack_In_3(5) <= \<const0>\;
  Dbg_Trig_Ack_In_3(6) <= \<const0>\;
  Dbg_Trig_Ack_In_3(7) <= \<const0>\;
  Dbg_Trig_Ack_In_30(0) <= \<const0>\;
  Dbg_Trig_Ack_In_30(1) <= \<const0>\;
  Dbg_Trig_Ack_In_30(2) <= \<const0>\;
  Dbg_Trig_Ack_In_30(3) <= \<const0>\;
  Dbg_Trig_Ack_In_30(4) <= \<const0>\;
  Dbg_Trig_Ack_In_30(5) <= \<const0>\;
  Dbg_Trig_Ack_In_30(6) <= \<const0>\;
  Dbg_Trig_Ack_In_30(7) <= \<const0>\;
  Dbg_Trig_Ack_In_31(0) <= \<const0>\;
  Dbg_Trig_Ack_In_31(1) <= \<const0>\;
  Dbg_Trig_Ack_In_31(2) <= \<const0>\;
  Dbg_Trig_Ack_In_31(3) <= \<const0>\;
  Dbg_Trig_Ack_In_31(4) <= \<const0>\;
  Dbg_Trig_Ack_In_31(5) <= \<const0>\;
  Dbg_Trig_Ack_In_31(6) <= \<const0>\;
  Dbg_Trig_Ack_In_31(7) <= \<const0>\;
  Dbg_Trig_Ack_In_4(0) <= \<const0>\;
  Dbg_Trig_Ack_In_4(1) <= \<const0>\;
  Dbg_Trig_Ack_In_4(2) <= \<const0>\;
  Dbg_Trig_Ack_In_4(3) <= \<const0>\;
  Dbg_Trig_Ack_In_4(4) <= \<const0>\;
  Dbg_Trig_Ack_In_4(5) <= \<const0>\;
  Dbg_Trig_Ack_In_4(6) <= \<const0>\;
  Dbg_Trig_Ack_In_4(7) <= \<const0>\;
  Dbg_Trig_Ack_In_5(0) <= \<const0>\;
  Dbg_Trig_Ack_In_5(1) <= \<const0>\;
  Dbg_Trig_Ack_In_5(2) <= \<const0>\;
  Dbg_Trig_Ack_In_5(3) <= \<const0>\;
  Dbg_Trig_Ack_In_5(4) <= \<const0>\;
  Dbg_Trig_Ack_In_5(5) <= \<const0>\;
  Dbg_Trig_Ack_In_5(6) <= \<const0>\;
  Dbg_Trig_Ack_In_5(7) <= \<const0>\;
  Dbg_Trig_Ack_In_6(0) <= \<const0>\;
  Dbg_Trig_Ack_In_6(1) <= \<const0>\;
  Dbg_Trig_Ack_In_6(2) <= \<const0>\;
  Dbg_Trig_Ack_In_6(3) <= \<const0>\;
  Dbg_Trig_Ack_In_6(4) <= \<const0>\;
  Dbg_Trig_Ack_In_6(5) <= \<const0>\;
  Dbg_Trig_Ack_In_6(6) <= \<const0>\;
  Dbg_Trig_Ack_In_6(7) <= \<const0>\;
  Dbg_Trig_Ack_In_7(0) <= \<const0>\;
  Dbg_Trig_Ack_In_7(1) <= \<const0>\;
  Dbg_Trig_Ack_In_7(2) <= \<const0>\;
  Dbg_Trig_Ack_In_7(3) <= \<const0>\;
  Dbg_Trig_Ack_In_7(4) <= \<const0>\;
  Dbg_Trig_Ack_In_7(5) <= \<const0>\;
  Dbg_Trig_Ack_In_7(6) <= \<const0>\;
  Dbg_Trig_Ack_In_7(7) <= \<const0>\;
  Dbg_Trig_Ack_In_8(0) <= \<const0>\;
  Dbg_Trig_Ack_In_8(1) <= \<const0>\;
  Dbg_Trig_Ack_In_8(2) <= \<const0>\;
  Dbg_Trig_Ack_In_8(3) <= \<const0>\;
  Dbg_Trig_Ack_In_8(4) <= \<const0>\;
  Dbg_Trig_Ack_In_8(5) <= \<const0>\;
  Dbg_Trig_Ack_In_8(6) <= \<const0>\;
  Dbg_Trig_Ack_In_8(7) <= \<const0>\;
  Dbg_Trig_Ack_In_9(0) <= \<const0>\;
  Dbg_Trig_Ack_In_9(1) <= \<const0>\;
  Dbg_Trig_Ack_In_9(2) <= \<const0>\;
  Dbg_Trig_Ack_In_9(3) <= \<const0>\;
  Dbg_Trig_Ack_In_9(4) <= \<const0>\;
  Dbg_Trig_Ack_In_9(5) <= \<const0>\;
  Dbg_Trig_Ack_In_9(6) <= \<const0>\;
  Dbg_Trig_Ack_In_9(7) <= \<const0>\;
  Dbg_Trig_Out_0(0) <= \<const0>\;
  Dbg_Trig_Out_0(1) <= \<const0>\;
  Dbg_Trig_Out_0(2) <= \<const0>\;
  Dbg_Trig_Out_0(3) <= \<const0>\;
  Dbg_Trig_Out_0(4) <= \<const0>\;
  Dbg_Trig_Out_0(5) <= \<const0>\;
  Dbg_Trig_Out_0(6) <= \<const0>\;
  Dbg_Trig_Out_0(7) <= \<const0>\;
  Dbg_Trig_Out_1(0) <= \<const0>\;
  Dbg_Trig_Out_1(1) <= \<const0>\;
  Dbg_Trig_Out_1(2) <= \<const0>\;
  Dbg_Trig_Out_1(3) <= \<const0>\;
  Dbg_Trig_Out_1(4) <= \<const0>\;
  Dbg_Trig_Out_1(5) <= \<const0>\;
  Dbg_Trig_Out_1(6) <= \<const0>\;
  Dbg_Trig_Out_1(7) <= \<const0>\;
  Dbg_Trig_Out_10(0) <= \<const0>\;
  Dbg_Trig_Out_10(1) <= \<const0>\;
  Dbg_Trig_Out_10(2) <= \<const0>\;
  Dbg_Trig_Out_10(3) <= \<const0>\;
  Dbg_Trig_Out_10(4) <= \<const0>\;
  Dbg_Trig_Out_10(5) <= \<const0>\;
  Dbg_Trig_Out_10(6) <= \<const0>\;
  Dbg_Trig_Out_10(7) <= \<const0>\;
  Dbg_Trig_Out_11(0) <= \<const0>\;
  Dbg_Trig_Out_11(1) <= \<const0>\;
  Dbg_Trig_Out_11(2) <= \<const0>\;
  Dbg_Trig_Out_11(3) <= \<const0>\;
  Dbg_Trig_Out_11(4) <= \<const0>\;
  Dbg_Trig_Out_11(5) <= \<const0>\;
  Dbg_Trig_Out_11(6) <= \<const0>\;
  Dbg_Trig_Out_11(7) <= \<const0>\;
  Dbg_Trig_Out_12(0) <= \<const0>\;
  Dbg_Trig_Out_12(1) <= \<const0>\;
  Dbg_Trig_Out_12(2) <= \<const0>\;
  Dbg_Trig_Out_12(3) <= \<const0>\;
  Dbg_Trig_Out_12(4) <= \<const0>\;
  Dbg_Trig_Out_12(5) <= \<const0>\;
  Dbg_Trig_Out_12(6) <= \<const0>\;
  Dbg_Trig_Out_12(7) <= \<const0>\;
  Dbg_Trig_Out_13(0) <= \<const0>\;
  Dbg_Trig_Out_13(1) <= \<const0>\;
  Dbg_Trig_Out_13(2) <= \<const0>\;
  Dbg_Trig_Out_13(3) <= \<const0>\;
  Dbg_Trig_Out_13(4) <= \<const0>\;
  Dbg_Trig_Out_13(5) <= \<const0>\;
  Dbg_Trig_Out_13(6) <= \<const0>\;
  Dbg_Trig_Out_13(7) <= \<const0>\;
  Dbg_Trig_Out_14(0) <= \<const0>\;
  Dbg_Trig_Out_14(1) <= \<const0>\;
  Dbg_Trig_Out_14(2) <= \<const0>\;
  Dbg_Trig_Out_14(3) <= \<const0>\;
  Dbg_Trig_Out_14(4) <= \<const0>\;
  Dbg_Trig_Out_14(5) <= \<const0>\;
  Dbg_Trig_Out_14(6) <= \<const0>\;
  Dbg_Trig_Out_14(7) <= \<const0>\;
  Dbg_Trig_Out_15(0) <= \<const0>\;
  Dbg_Trig_Out_15(1) <= \<const0>\;
  Dbg_Trig_Out_15(2) <= \<const0>\;
  Dbg_Trig_Out_15(3) <= \<const0>\;
  Dbg_Trig_Out_15(4) <= \<const0>\;
  Dbg_Trig_Out_15(5) <= \<const0>\;
  Dbg_Trig_Out_15(6) <= \<const0>\;
  Dbg_Trig_Out_15(7) <= \<const0>\;
  Dbg_Trig_Out_16(0) <= \<const0>\;
  Dbg_Trig_Out_16(1) <= \<const0>\;
  Dbg_Trig_Out_16(2) <= \<const0>\;
  Dbg_Trig_Out_16(3) <= \<const0>\;
  Dbg_Trig_Out_16(4) <= \<const0>\;
  Dbg_Trig_Out_16(5) <= \<const0>\;
  Dbg_Trig_Out_16(6) <= \<const0>\;
  Dbg_Trig_Out_16(7) <= \<const0>\;
  Dbg_Trig_Out_17(0) <= \<const0>\;
  Dbg_Trig_Out_17(1) <= \<const0>\;
  Dbg_Trig_Out_17(2) <= \<const0>\;
  Dbg_Trig_Out_17(3) <= \<const0>\;
  Dbg_Trig_Out_17(4) <= \<const0>\;
  Dbg_Trig_Out_17(5) <= \<const0>\;
  Dbg_Trig_Out_17(6) <= \<const0>\;
  Dbg_Trig_Out_17(7) <= \<const0>\;
  Dbg_Trig_Out_18(0) <= \<const0>\;
  Dbg_Trig_Out_18(1) <= \<const0>\;
  Dbg_Trig_Out_18(2) <= \<const0>\;
  Dbg_Trig_Out_18(3) <= \<const0>\;
  Dbg_Trig_Out_18(4) <= \<const0>\;
  Dbg_Trig_Out_18(5) <= \<const0>\;
  Dbg_Trig_Out_18(6) <= \<const0>\;
  Dbg_Trig_Out_18(7) <= \<const0>\;
  Dbg_Trig_Out_19(0) <= \<const0>\;
  Dbg_Trig_Out_19(1) <= \<const0>\;
  Dbg_Trig_Out_19(2) <= \<const0>\;
  Dbg_Trig_Out_19(3) <= \<const0>\;
  Dbg_Trig_Out_19(4) <= \<const0>\;
  Dbg_Trig_Out_19(5) <= \<const0>\;
  Dbg_Trig_Out_19(6) <= \<const0>\;
  Dbg_Trig_Out_19(7) <= \<const0>\;
  Dbg_Trig_Out_2(0) <= \<const0>\;
  Dbg_Trig_Out_2(1) <= \<const0>\;
  Dbg_Trig_Out_2(2) <= \<const0>\;
  Dbg_Trig_Out_2(3) <= \<const0>\;
  Dbg_Trig_Out_2(4) <= \<const0>\;
  Dbg_Trig_Out_2(5) <= \<const0>\;
  Dbg_Trig_Out_2(6) <= \<const0>\;
  Dbg_Trig_Out_2(7) <= \<const0>\;
  Dbg_Trig_Out_20(0) <= \<const0>\;
  Dbg_Trig_Out_20(1) <= \<const0>\;
  Dbg_Trig_Out_20(2) <= \<const0>\;
  Dbg_Trig_Out_20(3) <= \<const0>\;
  Dbg_Trig_Out_20(4) <= \<const0>\;
  Dbg_Trig_Out_20(5) <= \<const0>\;
  Dbg_Trig_Out_20(6) <= \<const0>\;
  Dbg_Trig_Out_20(7) <= \<const0>\;
  Dbg_Trig_Out_21(0) <= \<const0>\;
  Dbg_Trig_Out_21(1) <= \<const0>\;
  Dbg_Trig_Out_21(2) <= \<const0>\;
  Dbg_Trig_Out_21(3) <= \<const0>\;
  Dbg_Trig_Out_21(4) <= \<const0>\;
  Dbg_Trig_Out_21(5) <= \<const0>\;
  Dbg_Trig_Out_21(6) <= \<const0>\;
  Dbg_Trig_Out_21(7) <= \<const0>\;
  Dbg_Trig_Out_22(0) <= \<const0>\;
  Dbg_Trig_Out_22(1) <= \<const0>\;
  Dbg_Trig_Out_22(2) <= \<const0>\;
  Dbg_Trig_Out_22(3) <= \<const0>\;
  Dbg_Trig_Out_22(4) <= \<const0>\;
  Dbg_Trig_Out_22(5) <= \<const0>\;
  Dbg_Trig_Out_22(6) <= \<const0>\;
  Dbg_Trig_Out_22(7) <= \<const0>\;
  Dbg_Trig_Out_23(0) <= \<const0>\;
  Dbg_Trig_Out_23(1) <= \<const0>\;
  Dbg_Trig_Out_23(2) <= \<const0>\;
  Dbg_Trig_Out_23(3) <= \<const0>\;
  Dbg_Trig_Out_23(4) <= \<const0>\;
  Dbg_Trig_Out_23(5) <= \<const0>\;
  Dbg_Trig_Out_23(6) <= \<const0>\;
  Dbg_Trig_Out_23(7) <= \<const0>\;
  Dbg_Trig_Out_24(0) <= \<const0>\;
  Dbg_Trig_Out_24(1) <= \<const0>\;
  Dbg_Trig_Out_24(2) <= \<const0>\;
  Dbg_Trig_Out_24(3) <= \<const0>\;
  Dbg_Trig_Out_24(4) <= \<const0>\;
  Dbg_Trig_Out_24(5) <= \<const0>\;
  Dbg_Trig_Out_24(6) <= \<const0>\;
  Dbg_Trig_Out_24(7) <= \<const0>\;
  Dbg_Trig_Out_25(0) <= \<const0>\;
  Dbg_Trig_Out_25(1) <= \<const0>\;
  Dbg_Trig_Out_25(2) <= \<const0>\;
  Dbg_Trig_Out_25(3) <= \<const0>\;
  Dbg_Trig_Out_25(4) <= \<const0>\;
  Dbg_Trig_Out_25(5) <= \<const0>\;
  Dbg_Trig_Out_25(6) <= \<const0>\;
  Dbg_Trig_Out_25(7) <= \<const0>\;
  Dbg_Trig_Out_26(0) <= \<const0>\;
  Dbg_Trig_Out_26(1) <= \<const0>\;
  Dbg_Trig_Out_26(2) <= \<const0>\;
  Dbg_Trig_Out_26(3) <= \<const0>\;
  Dbg_Trig_Out_26(4) <= \<const0>\;
  Dbg_Trig_Out_26(5) <= \<const0>\;
  Dbg_Trig_Out_26(6) <= \<const0>\;
  Dbg_Trig_Out_26(7) <= \<const0>\;
  Dbg_Trig_Out_27(0) <= \<const0>\;
  Dbg_Trig_Out_27(1) <= \<const0>\;
  Dbg_Trig_Out_27(2) <= \<const0>\;
  Dbg_Trig_Out_27(3) <= \<const0>\;
  Dbg_Trig_Out_27(4) <= \<const0>\;
  Dbg_Trig_Out_27(5) <= \<const0>\;
  Dbg_Trig_Out_27(6) <= \<const0>\;
  Dbg_Trig_Out_27(7) <= \<const0>\;
  Dbg_Trig_Out_28(0) <= \<const0>\;
  Dbg_Trig_Out_28(1) <= \<const0>\;
  Dbg_Trig_Out_28(2) <= \<const0>\;
  Dbg_Trig_Out_28(3) <= \<const0>\;
  Dbg_Trig_Out_28(4) <= \<const0>\;
  Dbg_Trig_Out_28(5) <= \<const0>\;
  Dbg_Trig_Out_28(6) <= \<const0>\;
  Dbg_Trig_Out_28(7) <= \<const0>\;
  Dbg_Trig_Out_29(0) <= \<const0>\;
  Dbg_Trig_Out_29(1) <= \<const0>\;
  Dbg_Trig_Out_29(2) <= \<const0>\;
  Dbg_Trig_Out_29(3) <= \<const0>\;
  Dbg_Trig_Out_29(4) <= \<const0>\;
  Dbg_Trig_Out_29(5) <= \<const0>\;
  Dbg_Trig_Out_29(6) <= \<const0>\;
  Dbg_Trig_Out_29(7) <= \<const0>\;
  Dbg_Trig_Out_3(0) <= \<const0>\;
  Dbg_Trig_Out_3(1) <= \<const0>\;
  Dbg_Trig_Out_3(2) <= \<const0>\;
  Dbg_Trig_Out_3(3) <= \<const0>\;
  Dbg_Trig_Out_3(4) <= \<const0>\;
  Dbg_Trig_Out_3(5) <= \<const0>\;
  Dbg_Trig_Out_3(6) <= \<const0>\;
  Dbg_Trig_Out_3(7) <= \<const0>\;
  Dbg_Trig_Out_30(0) <= \<const0>\;
  Dbg_Trig_Out_30(1) <= \<const0>\;
  Dbg_Trig_Out_30(2) <= \<const0>\;
  Dbg_Trig_Out_30(3) <= \<const0>\;
  Dbg_Trig_Out_30(4) <= \<const0>\;
  Dbg_Trig_Out_30(5) <= \<const0>\;
  Dbg_Trig_Out_30(6) <= \<const0>\;
  Dbg_Trig_Out_30(7) <= \<const0>\;
  Dbg_Trig_Out_31(0) <= \<const0>\;
  Dbg_Trig_Out_31(1) <= \<const0>\;
  Dbg_Trig_Out_31(2) <= \<const0>\;
  Dbg_Trig_Out_31(3) <= \<const0>\;
  Dbg_Trig_Out_31(4) <= \<const0>\;
  Dbg_Trig_Out_31(5) <= \<const0>\;
  Dbg_Trig_Out_31(6) <= \<const0>\;
  Dbg_Trig_Out_31(7) <= \<const0>\;
  Dbg_Trig_Out_4(0) <= \<const0>\;
  Dbg_Trig_Out_4(1) <= \<const0>\;
  Dbg_Trig_Out_4(2) <= \<const0>\;
  Dbg_Trig_Out_4(3) <= \<const0>\;
  Dbg_Trig_Out_4(4) <= \<const0>\;
  Dbg_Trig_Out_4(5) <= \<const0>\;
  Dbg_Trig_Out_4(6) <= \<const0>\;
  Dbg_Trig_Out_4(7) <= \<const0>\;
  Dbg_Trig_Out_5(0) <= \<const0>\;
  Dbg_Trig_Out_5(1) <= \<const0>\;
  Dbg_Trig_Out_5(2) <= \<const0>\;
  Dbg_Trig_Out_5(3) <= \<const0>\;
  Dbg_Trig_Out_5(4) <= \<const0>\;
  Dbg_Trig_Out_5(5) <= \<const0>\;
  Dbg_Trig_Out_5(6) <= \<const0>\;
  Dbg_Trig_Out_5(7) <= \<const0>\;
  Dbg_Trig_Out_6(0) <= \<const0>\;
  Dbg_Trig_Out_6(1) <= \<const0>\;
  Dbg_Trig_Out_6(2) <= \<const0>\;
  Dbg_Trig_Out_6(3) <= \<const0>\;
  Dbg_Trig_Out_6(4) <= \<const0>\;
  Dbg_Trig_Out_6(5) <= \<const0>\;
  Dbg_Trig_Out_6(6) <= \<const0>\;
  Dbg_Trig_Out_6(7) <= \<const0>\;
  Dbg_Trig_Out_7(0) <= \<const0>\;
  Dbg_Trig_Out_7(1) <= \<const0>\;
  Dbg_Trig_Out_7(2) <= \<const0>\;
  Dbg_Trig_Out_7(3) <= \<const0>\;
  Dbg_Trig_Out_7(4) <= \<const0>\;
  Dbg_Trig_Out_7(5) <= \<const0>\;
  Dbg_Trig_Out_7(6) <= \<const0>\;
  Dbg_Trig_Out_7(7) <= \<const0>\;
  Dbg_Trig_Out_8(0) <= \<const0>\;
  Dbg_Trig_Out_8(1) <= \<const0>\;
  Dbg_Trig_Out_8(2) <= \<const0>\;
  Dbg_Trig_Out_8(3) <= \<const0>\;
  Dbg_Trig_Out_8(4) <= \<const0>\;
  Dbg_Trig_Out_8(5) <= \<const0>\;
  Dbg_Trig_Out_8(6) <= \<const0>\;
  Dbg_Trig_Out_8(7) <= \<const0>\;
  Dbg_Trig_Out_9(0) <= \<const0>\;
  Dbg_Trig_Out_9(1) <= \<const0>\;
  Dbg_Trig_Out_9(2) <= \<const0>\;
  Dbg_Trig_Out_9(3) <= \<const0>\;
  Dbg_Trig_Out_9(4) <= \<const0>\;
  Dbg_Trig_Out_9(5) <= \<const0>\;
  Dbg_Trig_Out_9(6) <= \<const0>\;
  Dbg_Trig_Out_9(7) <= \<const0>\;
  Dbg_Update_1 <= \<const0>\;
  Dbg_Update_10 <= \<const0>\;
  Dbg_Update_11 <= \<const0>\;
  Dbg_Update_12 <= \<const0>\;
  Dbg_Update_13 <= \<const0>\;
  Dbg_Update_14 <= \<const0>\;
  Dbg_Update_15 <= \<const0>\;
  Dbg_Update_16 <= \<const0>\;
  Dbg_Update_17 <= \<const0>\;
  Dbg_Update_18 <= \<const0>\;
  Dbg_Update_19 <= \<const0>\;
  Dbg_Update_2 <= \<const0>\;
  Dbg_Update_20 <= \<const0>\;
  Dbg_Update_21 <= \<const0>\;
  Dbg_Update_22 <= \<const0>\;
  Dbg_Update_23 <= \<const0>\;
  Dbg_Update_24 <= \<const0>\;
  Dbg_Update_25 <= \<const0>\;
  Dbg_Update_26 <= \<const0>\;
  Dbg_Update_27 <= \<const0>\;
  Dbg_Update_28 <= \<const0>\;
  Dbg_Update_29 <= \<const0>\;
  Dbg_Update_3 <= \<const0>\;
  Dbg_Update_30 <= \<const0>\;
  Dbg_Update_31 <= \<const0>\;
  Dbg_Update_4 <= \<const0>\;
  Dbg_Update_5 <= \<const0>\;
  Dbg_Update_6 <= \<const0>\;
  Dbg_Update_7 <= \<const0>\;
  Dbg_Update_8 <= \<const0>\;
  Dbg_Update_9 <= \<const0>\;
  Dbg_WDATA_0(31) <= \<const0>\;
  Dbg_WDATA_0(30) <= \<const0>\;
  Dbg_WDATA_0(29) <= \<const0>\;
  Dbg_WDATA_0(28) <= \<const0>\;
  Dbg_WDATA_0(27) <= \<const0>\;
  Dbg_WDATA_0(26) <= \<const0>\;
  Dbg_WDATA_0(25) <= \<const0>\;
  Dbg_WDATA_0(24) <= \<const0>\;
  Dbg_WDATA_0(23) <= \<const0>\;
  Dbg_WDATA_0(22) <= \<const0>\;
  Dbg_WDATA_0(21) <= \<const0>\;
  Dbg_WDATA_0(20) <= \<const0>\;
  Dbg_WDATA_0(19) <= \<const0>\;
  Dbg_WDATA_0(18) <= \<const0>\;
  Dbg_WDATA_0(17) <= \<const0>\;
  Dbg_WDATA_0(16) <= \<const0>\;
  Dbg_WDATA_0(15) <= \<const0>\;
  Dbg_WDATA_0(14) <= \<const0>\;
  Dbg_WDATA_0(13) <= \<const0>\;
  Dbg_WDATA_0(12) <= \<const0>\;
  Dbg_WDATA_0(11) <= \<const0>\;
  Dbg_WDATA_0(10) <= \<const0>\;
  Dbg_WDATA_0(9) <= \<const0>\;
  Dbg_WDATA_0(8) <= \<const0>\;
  Dbg_WDATA_0(7) <= \<const0>\;
  Dbg_WDATA_0(6) <= \<const0>\;
  Dbg_WDATA_0(5) <= \<const0>\;
  Dbg_WDATA_0(4) <= \<const0>\;
  Dbg_WDATA_0(3) <= \<const0>\;
  Dbg_WDATA_0(2) <= \<const0>\;
  Dbg_WDATA_0(1) <= \<const0>\;
  Dbg_WDATA_0(0) <= \<const0>\;
  Dbg_WDATA_1(31) <= \<const0>\;
  Dbg_WDATA_1(30) <= \<const0>\;
  Dbg_WDATA_1(29) <= \<const0>\;
  Dbg_WDATA_1(28) <= \<const0>\;
  Dbg_WDATA_1(27) <= \<const0>\;
  Dbg_WDATA_1(26) <= \<const0>\;
  Dbg_WDATA_1(25) <= \<const0>\;
  Dbg_WDATA_1(24) <= \<const0>\;
  Dbg_WDATA_1(23) <= \<const0>\;
  Dbg_WDATA_1(22) <= \<const0>\;
  Dbg_WDATA_1(21) <= \<const0>\;
  Dbg_WDATA_1(20) <= \<const0>\;
  Dbg_WDATA_1(19) <= \<const0>\;
  Dbg_WDATA_1(18) <= \<const0>\;
  Dbg_WDATA_1(17) <= \<const0>\;
  Dbg_WDATA_1(16) <= \<const0>\;
  Dbg_WDATA_1(15) <= \<const0>\;
  Dbg_WDATA_1(14) <= \<const0>\;
  Dbg_WDATA_1(13) <= \<const0>\;
  Dbg_WDATA_1(12) <= \<const0>\;
  Dbg_WDATA_1(11) <= \<const0>\;
  Dbg_WDATA_1(10) <= \<const0>\;
  Dbg_WDATA_1(9) <= \<const0>\;
  Dbg_WDATA_1(8) <= \<const0>\;
  Dbg_WDATA_1(7) <= \<const0>\;
  Dbg_WDATA_1(6) <= \<const0>\;
  Dbg_WDATA_1(5) <= \<const0>\;
  Dbg_WDATA_1(4) <= \<const0>\;
  Dbg_WDATA_1(3) <= \<const0>\;
  Dbg_WDATA_1(2) <= \<const0>\;
  Dbg_WDATA_1(1) <= \<const0>\;
  Dbg_WDATA_1(0) <= \<const0>\;
  Dbg_WDATA_10(31) <= \<const0>\;
  Dbg_WDATA_10(30) <= \<const0>\;
  Dbg_WDATA_10(29) <= \<const0>\;
  Dbg_WDATA_10(28) <= \<const0>\;
  Dbg_WDATA_10(27) <= \<const0>\;
  Dbg_WDATA_10(26) <= \<const0>\;
  Dbg_WDATA_10(25) <= \<const0>\;
  Dbg_WDATA_10(24) <= \<const0>\;
  Dbg_WDATA_10(23) <= \<const0>\;
  Dbg_WDATA_10(22) <= \<const0>\;
  Dbg_WDATA_10(21) <= \<const0>\;
  Dbg_WDATA_10(20) <= \<const0>\;
  Dbg_WDATA_10(19) <= \<const0>\;
  Dbg_WDATA_10(18) <= \<const0>\;
  Dbg_WDATA_10(17) <= \<const0>\;
  Dbg_WDATA_10(16) <= \<const0>\;
  Dbg_WDATA_10(15) <= \<const0>\;
  Dbg_WDATA_10(14) <= \<const0>\;
  Dbg_WDATA_10(13) <= \<const0>\;
  Dbg_WDATA_10(12) <= \<const0>\;
  Dbg_WDATA_10(11) <= \<const0>\;
  Dbg_WDATA_10(10) <= \<const0>\;
  Dbg_WDATA_10(9) <= \<const0>\;
  Dbg_WDATA_10(8) <= \<const0>\;
  Dbg_WDATA_10(7) <= \<const0>\;
  Dbg_WDATA_10(6) <= \<const0>\;
  Dbg_WDATA_10(5) <= \<const0>\;
  Dbg_WDATA_10(4) <= \<const0>\;
  Dbg_WDATA_10(3) <= \<const0>\;
  Dbg_WDATA_10(2) <= \<const0>\;
  Dbg_WDATA_10(1) <= \<const0>\;
  Dbg_WDATA_10(0) <= \<const0>\;
  Dbg_WDATA_11(31) <= \<const0>\;
  Dbg_WDATA_11(30) <= \<const0>\;
  Dbg_WDATA_11(29) <= \<const0>\;
  Dbg_WDATA_11(28) <= \<const0>\;
  Dbg_WDATA_11(27) <= \<const0>\;
  Dbg_WDATA_11(26) <= \<const0>\;
  Dbg_WDATA_11(25) <= \<const0>\;
  Dbg_WDATA_11(24) <= \<const0>\;
  Dbg_WDATA_11(23) <= \<const0>\;
  Dbg_WDATA_11(22) <= \<const0>\;
  Dbg_WDATA_11(21) <= \<const0>\;
  Dbg_WDATA_11(20) <= \<const0>\;
  Dbg_WDATA_11(19) <= \<const0>\;
  Dbg_WDATA_11(18) <= \<const0>\;
  Dbg_WDATA_11(17) <= \<const0>\;
  Dbg_WDATA_11(16) <= \<const0>\;
  Dbg_WDATA_11(15) <= \<const0>\;
  Dbg_WDATA_11(14) <= \<const0>\;
  Dbg_WDATA_11(13) <= \<const0>\;
  Dbg_WDATA_11(12) <= \<const0>\;
  Dbg_WDATA_11(11) <= \<const0>\;
  Dbg_WDATA_11(10) <= \<const0>\;
  Dbg_WDATA_11(9) <= \<const0>\;
  Dbg_WDATA_11(8) <= \<const0>\;
  Dbg_WDATA_11(7) <= \<const0>\;
  Dbg_WDATA_11(6) <= \<const0>\;
  Dbg_WDATA_11(5) <= \<const0>\;
  Dbg_WDATA_11(4) <= \<const0>\;
  Dbg_WDATA_11(3) <= \<const0>\;
  Dbg_WDATA_11(2) <= \<const0>\;
  Dbg_WDATA_11(1) <= \<const0>\;
  Dbg_WDATA_11(0) <= \<const0>\;
  Dbg_WDATA_12(31) <= \<const0>\;
  Dbg_WDATA_12(30) <= \<const0>\;
  Dbg_WDATA_12(29) <= \<const0>\;
  Dbg_WDATA_12(28) <= \<const0>\;
  Dbg_WDATA_12(27) <= \<const0>\;
  Dbg_WDATA_12(26) <= \<const0>\;
  Dbg_WDATA_12(25) <= \<const0>\;
  Dbg_WDATA_12(24) <= \<const0>\;
  Dbg_WDATA_12(23) <= \<const0>\;
  Dbg_WDATA_12(22) <= \<const0>\;
  Dbg_WDATA_12(21) <= \<const0>\;
  Dbg_WDATA_12(20) <= \<const0>\;
  Dbg_WDATA_12(19) <= \<const0>\;
  Dbg_WDATA_12(18) <= \<const0>\;
  Dbg_WDATA_12(17) <= \<const0>\;
  Dbg_WDATA_12(16) <= \<const0>\;
  Dbg_WDATA_12(15) <= \<const0>\;
  Dbg_WDATA_12(14) <= \<const0>\;
  Dbg_WDATA_12(13) <= \<const0>\;
  Dbg_WDATA_12(12) <= \<const0>\;
  Dbg_WDATA_12(11) <= \<const0>\;
  Dbg_WDATA_12(10) <= \<const0>\;
  Dbg_WDATA_12(9) <= \<const0>\;
  Dbg_WDATA_12(8) <= \<const0>\;
  Dbg_WDATA_12(7) <= \<const0>\;
  Dbg_WDATA_12(6) <= \<const0>\;
  Dbg_WDATA_12(5) <= \<const0>\;
  Dbg_WDATA_12(4) <= \<const0>\;
  Dbg_WDATA_12(3) <= \<const0>\;
  Dbg_WDATA_12(2) <= \<const0>\;
  Dbg_WDATA_12(1) <= \<const0>\;
  Dbg_WDATA_12(0) <= \<const0>\;
  Dbg_WDATA_13(31) <= \<const0>\;
  Dbg_WDATA_13(30) <= \<const0>\;
  Dbg_WDATA_13(29) <= \<const0>\;
  Dbg_WDATA_13(28) <= \<const0>\;
  Dbg_WDATA_13(27) <= \<const0>\;
  Dbg_WDATA_13(26) <= \<const0>\;
  Dbg_WDATA_13(25) <= \<const0>\;
  Dbg_WDATA_13(24) <= \<const0>\;
  Dbg_WDATA_13(23) <= \<const0>\;
  Dbg_WDATA_13(22) <= \<const0>\;
  Dbg_WDATA_13(21) <= \<const0>\;
  Dbg_WDATA_13(20) <= \<const0>\;
  Dbg_WDATA_13(19) <= \<const0>\;
  Dbg_WDATA_13(18) <= \<const0>\;
  Dbg_WDATA_13(17) <= \<const0>\;
  Dbg_WDATA_13(16) <= \<const0>\;
  Dbg_WDATA_13(15) <= \<const0>\;
  Dbg_WDATA_13(14) <= \<const0>\;
  Dbg_WDATA_13(13) <= \<const0>\;
  Dbg_WDATA_13(12) <= \<const0>\;
  Dbg_WDATA_13(11) <= \<const0>\;
  Dbg_WDATA_13(10) <= \<const0>\;
  Dbg_WDATA_13(9) <= \<const0>\;
  Dbg_WDATA_13(8) <= \<const0>\;
  Dbg_WDATA_13(7) <= \<const0>\;
  Dbg_WDATA_13(6) <= \<const0>\;
  Dbg_WDATA_13(5) <= \<const0>\;
  Dbg_WDATA_13(4) <= \<const0>\;
  Dbg_WDATA_13(3) <= \<const0>\;
  Dbg_WDATA_13(2) <= \<const0>\;
  Dbg_WDATA_13(1) <= \<const0>\;
  Dbg_WDATA_13(0) <= \<const0>\;
  Dbg_WDATA_14(31) <= \<const0>\;
  Dbg_WDATA_14(30) <= \<const0>\;
  Dbg_WDATA_14(29) <= \<const0>\;
  Dbg_WDATA_14(28) <= \<const0>\;
  Dbg_WDATA_14(27) <= \<const0>\;
  Dbg_WDATA_14(26) <= \<const0>\;
  Dbg_WDATA_14(25) <= \<const0>\;
  Dbg_WDATA_14(24) <= \<const0>\;
  Dbg_WDATA_14(23) <= \<const0>\;
  Dbg_WDATA_14(22) <= \<const0>\;
  Dbg_WDATA_14(21) <= \<const0>\;
  Dbg_WDATA_14(20) <= \<const0>\;
  Dbg_WDATA_14(19) <= \<const0>\;
  Dbg_WDATA_14(18) <= \<const0>\;
  Dbg_WDATA_14(17) <= \<const0>\;
  Dbg_WDATA_14(16) <= \<const0>\;
  Dbg_WDATA_14(15) <= \<const0>\;
  Dbg_WDATA_14(14) <= \<const0>\;
  Dbg_WDATA_14(13) <= \<const0>\;
  Dbg_WDATA_14(12) <= \<const0>\;
  Dbg_WDATA_14(11) <= \<const0>\;
  Dbg_WDATA_14(10) <= \<const0>\;
  Dbg_WDATA_14(9) <= \<const0>\;
  Dbg_WDATA_14(8) <= \<const0>\;
  Dbg_WDATA_14(7) <= \<const0>\;
  Dbg_WDATA_14(6) <= \<const0>\;
  Dbg_WDATA_14(5) <= \<const0>\;
  Dbg_WDATA_14(4) <= \<const0>\;
  Dbg_WDATA_14(3) <= \<const0>\;
  Dbg_WDATA_14(2) <= \<const0>\;
  Dbg_WDATA_14(1) <= \<const0>\;
  Dbg_WDATA_14(0) <= \<const0>\;
  Dbg_WDATA_15(31) <= \<const0>\;
  Dbg_WDATA_15(30) <= \<const0>\;
  Dbg_WDATA_15(29) <= \<const0>\;
  Dbg_WDATA_15(28) <= \<const0>\;
  Dbg_WDATA_15(27) <= \<const0>\;
  Dbg_WDATA_15(26) <= \<const0>\;
  Dbg_WDATA_15(25) <= \<const0>\;
  Dbg_WDATA_15(24) <= \<const0>\;
  Dbg_WDATA_15(23) <= \<const0>\;
  Dbg_WDATA_15(22) <= \<const0>\;
  Dbg_WDATA_15(21) <= \<const0>\;
  Dbg_WDATA_15(20) <= \<const0>\;
  Dbg_WDATA_15(19) <= \<const0>\;
  Dbg_WDATA_15(18) <= \<const0>\;
  Dbg_WDATA_15(17) <= \<const0>\;
  Dbg_WDATA_15(16) <= \<const0>\;
  Dbg_WDATA_15(15) <= \<const0>\;
  Dbg_WDATA_15(14) <= \<const0>\;
  Dbg_WDATA_15(13) <= \<const0>\;
  Dbg_WDATA_15(12) <= \<const0>\;
  Dbg_WDATA_15(11) <= \<const0>\;
  Dbg_WDATA_15(10) <= \<const0>\;
  Dbg_WDATA_15(9) <= \<const0>\;
  Dbg_WDATA_15(8) <= \<const0>\;
  Dbg_WDATA_15(7) <= \<const0>\;
  Dbg_WDATA_15(6) <= \<const0>\;
  Dbg_WDATA_15(5) <= \<const0>\;
  Dbg_WDATA_15(4) <= \<const0>\;
  Dbg_WDATA_15(3) <= \<const0>\;
  Dbg_WDATA_15(2) <= \<const0>\;
  Dbg_WDATA_15(1) <= \<const0>\;
  Dbg_WDATA_15(0) <= \<const0>\;
  Dbg_WDATA_16(31) <= \<const0>\;
  Dbg_WDATA_16(30) <= \<const0>\;
  Dbg_WDATA_16(29) <= \<const0>\;
  Dbg_WDATA_16(28) <= \<const0>\;
  Dbg_WDATA_16(27) <= \<const0>\;
  Dbg_WDATA_16(26) <= \<const0>\;
  Dbg_WDATA_16(25) <= \<const0>\;
  Dbg_WDATA_16(24) <= \<const0>\;
  Dbg_WDATA_16(23) <= \<const0>\;
  Dbg_WDATA_16(22) <= \<const0>\;
  Dbg_WDATA_16(21) <= \<const0>\;
  Dbg_WDATA_16(20) <= \<const0>\;
  Dbg_WDATA_16(19) <= \<const0>\;
  Dbg_WDATA_16(18) <= \<const0>\;
  Dbg_WDATA_16(17) <= \<const0>\;
  Dbg_WDATA_16(16) <= \<const0>\;
  Dbg_WDATA_16(15) <= \<const0>\;
  Dbg_WDATA_16(14) <= \<const0>\;
  Dbg_WDATA_16(13) <= \<const0>\;
  Dbg_WDATA_16(12) <= \<const0>\;
  Dbg_WDATA_16(11) <= \<const0>\;
  Dbg_WDATA_16(10) <= \<const0>\;
  Dbg_WDATA_16(9) <= \<const0>\;
  Dbg_WDATA_16(8) <= \<const0>\;
  Dbg_WDATA_16(7) <= \<const0>\;
  Dbg_WDATA_16(6) <= \<const0>\;
  Dbg_WDATA_16(5) <= \<const0>\;
  Dbg_WDATA_16(4) <= \<const0>\;
  Dbg_WDATA_16(3) <= \<const0>\;
  Dbg_WDATA_16(2) <= \<const0>\;
  Dbg_WDATA_16(1) <= \<const0>\;
  Dbg_WDATA_16(0) <= \<const0>\;
  Dbg_WDATA_17(31) <= \<const0>\;
  Dbg_WDATA_17(30) <= \<const0>\;
  Dbg_WDATA_17(29) <= \<const0>\;
  Dbg_WDATA_17(28) <= \<const0>\;
  Dbg_WDATA_17(27) <= \<const0>\;
  Dbg_WDATA_17(26) <= \<const0>\;
  Dbg_WDATA_17(25) <= \<const0>\;
  Dbg_WDATA_17(24) <= \<const0>\;
  Dbg_WDATA_17(23) <= \<const0>\;
  Dbg_WDATA_17(22) <= \<const0>\;
  Dbg_WDATA_17(21) <= \<const0>\;
  Dbg_WDATA_17(20) <= \<const0>\;
  Dbg_WDATA_17(19) <= \<const0>\;
  Dbg_WDATA_17(18) <= \<const0>\;
  Dbg_WDATA_17(17) <= \<const0>\;
  Dbg_WDATA_17(16) <= \<const0>\;
  Dbg_WDATA_17(15) <= \<const0>\;
  Dbg_WDATA_17(14) <= \<const0>\;
  Dbg_WDATA_17(13) <= \<const0>\;
  Dbg_WDATA_17(12) <= \<const0>\;
  Dbg_WDATA_17(11) <= \<const0>\;
  Dbg_WDATA_17(10) <= \<const0>\;
  Dbg_WDATA_17(9) <= \<const0>\;
  Dbg_WDATA_17(8) <= \<const0>\;
  Dbg_WDATA_17(7) <= \<const0>\;
  Dbg_WDATA_17(6) <= \<const0>\;
  Dbg_WDATA_17(5) <= \<const0>\;
  Dbg_WDATA_17(4) <= \<const0>\;
  Dbg_WDATA_17(3) <= \<const0>\;
  Dbg_WDATA_17(2) <= \<const0>\;
  Dbg_WDATA_17(1) <= \<const0>\;
  Dbg_WDATA_17(0) <= \<const0>\;
  Dbg_WDATA_18(31) <= \<const0>\;
  Dbg_WDATA_18(30) <= \<const0>\;
  Dbg_WDATA_18(29) <= \<const0>\;
  Dbg_WDATA_18(28) <= \<const0>\;
  Dbg_WDATA_18(27) <= \<const0>\;
  Dbg_WDATA_18(26) <= \<const0>\;
  Dbg_WDATA_18(25) <= \<const0>\;
  Dbg_WDATA_18(24) <= \<const0>\;
  Dbg_WDATA_18(23) <= \<const0>\;
  Dbg_WDATA_18(22) <= \<const0>\;
  Dbg_WDATA_18(21) <= \<const0>\;
  Dbg_WDATA_18(20) <= \<const0>\;
  Dbg_WDATA_18(19) <= \<const0>\;
  Dbg_WDATA_18(18) <= \<const0>\;
  Dbg_WDATA_18(17) <= \<const0>\;
  Dbg_WDATA_18(16) <= \<const0>\;
  Dbg_WDATA_18(15) <= \<const0>\;
  Dbg_WDATA_18(14) <= \<const0>\;
  Dbg_WDATA_18(13) <= \<const0>\;
  Dbg_WDATA_18(12) <= \<const0>\;
  Dbg_WDATA_18(11) <= \<const0>\;
  Dbg_WDATA_18(10) <= \<const0>\;
  Dbg_WDATA_18(9) <= \<const0>\;
  Dbg_WDATA_18(8) <= \<const0>\;
  Dbg_WDATA_18(7) <= \<const0>\;
  Dbg_WDATA_18(6) <= \<const0>\;
  Dbg_WDATA_18(5) <= \<const0>\;
  Dbg_WDATA_18(4) <= \<const0>\;
  Dbg_WDATA_18(3) <= \<const0>\;
  Dbg_WDATA_18(2) <= \<const0>\;
  Dbg_WDATA_18(1) <= \<const0>\;
  Dbg_WDATA_18(0) <= \<const0>\;
  Dbg_WDATA_19(31) <= \<const0>\;
  Dbg_WDATA_19(30) <= \<const0>\;
  Dbg_WDATA_19(29) <= \<const0>\;
  Dbg_WDATA_19(28) <= \<const0>\;
  Dbg_WDATA_19(27) <= \<const0>\;
  Dbg_WDATA_19(26) <= \<const0>\;
  Dbg_WDATA_19(25) <= \<const0>\;
  Dbg_WDATA_19(24) <= \<const0>\;
  Dbg_WDATA_19(23) <= \<const0>\;
  Dbg_WDATA_19(22) <= \<const0>\;
  Dbg_WDATA_19(21) <= \<const0>\;
  Dbg_WDATA_19(20) <= \<const0>\;
  Dbg_WDATA_19(19) <= \<const0>\;
  Dbg_WDATA_19(18) <= \<const0>\;
  Dbg_WDATA_19(17) <= \<const0>\;
  Dbg_WDATA_19(16) <= \<const0>\;
  Dbg_WDATA_19(15) <= \<const0>\;
  Dbg_WDATA_19(14) <= \<const0>\;
  Dbg_WDATA_19(13) <= \<const0>\;
  Dbg_WDATA_19(12) <= \<const0>\;
  Dbg_WDATA_19(11) <= \<const0>\;
  Dbg_WDATA_19(10) <= \<const0>\;
  Dbg_WDATA_19(9) <= \<const0>\;
  Dbg_WDATA_19(8) <= \<const0>\;
  Dbg_WDATA_19(7) <= \<const0>\;
  Dbg_WDATA_19(6) <= \<const0>\;
  Dbg_WDATA_19(5) <= \<const0>\;
  Dbg_WDATA_19(4) <= \<const0>\;
  Dbg_WDATA_19(3) <= \<const0>\;
  Dbg_WDATA_19(2) <= \<const0>\;
  Dbg_WDATA_19(1) <= \<const0>\;
  Dbg_WDATA_19(0) <= \<const0>\;
  Dbg_WDATA_2(31) <= \<const0>\;
  Dbg_WDATA_2(30) <= \<const0>\;
  Dbg_WDATA_2(29) <= \<const0>\;
  Dbg_WDATA_2(28) <= \<const0>\;
  Dbg_WDATA_2(27) <= \<const0>\;
  Dbg_WDATA_2(26) <= \<const0>\;
  Dbg_WDATA_2(25) <= \<const0>\;
  Dbg_WDATA_2(24) <= \<const0>\;
  Dbg_WDATA_2(23) <= \<const0>\;
  Dbg_WDATA_2(22) <= \<const0>\;
  Dbg_WDATA_2(21) <= \<const0>\;
  Dbg_WDATA_2(20) <= \<const0>\;
  Dbg_WDATA_2(19) <= \<const0>\;
  Dbg_WDATA_2(18) <= \<const0>\;
  Dbg_WDATA_2(17) <= \<const0>\;
  Dbg_WDATA_2(16) <= \<const0>\;
  Dbg_WDATA_2(15) <= \<const0>\;
  Dbg_WDATA_2(14) <= \<const0>\;
  Dbg_WDATA_2(13) <= \<const0>\;
  Dbg_WDATA_2(12) <= \<const0>\;
  Dbg_WDATA_2(11) <= \<const0>\;
  Dbg_WDATA_2(10) <= \<const0>\;
  Dbg_WDATA_2(9) <= \<const0>\;
  Dbg_WDATA_2(8) <= \<const0>\;
  Dbg_WDATA_2(7) <= \<const0>\;
  Dbg_WDATA_2(6) <= \<const0>\;
  Dbg_WDATA_2(5) <= \<const0>\;
  Dbg_WDATA_2(4) <= \<const0>\;
  Dbg_WDATA_2(3) <= \<const0>\;
  Dbg_WDATA_2(2) <= \<const0>\;
  Dbg_WDATA_2(1) <= \<const0>\;
  Dbg_WDATA_2(0) <= \<const0>\;
  Dbg_WDATA_20(31) <= \<const0>\;
  Dbg_WDATA_20(30) <= \<const0>\;
  Dbg_WDATA_20(29) <= \<const0>\;
  Dbg_WDATA_20(28) <= \<const0>\;
  Dbg_WDATA_20(27) <= \<const0>\;
  Dbg_WDATA_20(26) <= \<const0>\;
  Dbg_WDATA_20(25) <= \<const0>\;
  Dbg_WDATA_20(24) <= \<const0>\;
  Dbg_WDATA_20(23) <= \<const0>\;
  Dbg_WDATA_20(22) <= \<const0>\;
  Dbg_WDATA_20(21) <= \<const0>\;
  Dbg_WDATA_20(20) <= \<const0>\;
  Dbg_WDATA_20(19) <= \<const0>\;
  Dbg_WDATA_20(18) <= \<const0>\;
  Dbg_WDATA_20(17) <= \<const0>\;
  Dbg_WDATA_20(16) <= \<const0>\;
  Dbg_WDATA_20(15) <= \<const0>\;
  Dbg_WDATA_20(14) <= \<const0>\;
  Dbg_WDATA_20(13) <= \<const0>\;
  Dbg_WDATA_20(12) <= \<const0>\;
  Dbg_WDATA_20(11) <= \<const0>\;
  Dbg_WDATA_20(10) <= \<const0>\;
  Dbg_WDATA_20(9) <= \<const0>\;
  Dbg_WDATA_20(8) <= \<const0>\;
  Dbg_WDATA_20(7) <= \<const0>\;
  Dbg_WDATA_20(6) <= \<const0>\;
  Dbg_WDATA_20(5) <= \<const0>\;
  Dbg_WDATA_20(4) <= \<const0>\;
  Dbg_WDATA_20(3) <= \<const0>\;
  Dbg_WDATA_20(2) <= \<const0>\;
  Dbg_WDATA_20(1) <= \<const0>\;
  Dbg_WDATA_20(0) <= \<const0>\;
  Dbg_WDATA_21(31) <= \<const0>\;
  Dbg_WDATA_21(30) <= \<const0>\;
  Dbg_WDATA_21(29) <= \<const0>\;
  Dbg_WDATA_21(28) <= \<const0>\;
  Dbg_WDATA_21(27) <= \<const0>\;
  Dbg_WDATA_21(26) <= \<const0>\;
  Dbg_WDATA_21(25) <= \<const0>\;
  Dbg_WDATA_21(24) <= \<const0>\;
  Dbg_WDATA_21(23) <= \<const0>\;
  Dbg_WDATA_21(22) <= \<const0>\;
  Dbg_WDATA_21(21) <= \<const0>\;
  Dbg_WDATA_21(20) <= \<const0>\;
  Dbg_WDATA_21(19) <= \<const0>\;
  Dbg_WDATA_21(18) <= \<const0>\;
  Dbg_WDATA_21(17) <= \<const0>\;
  Dbg_WDATA_21(16) <= \<const0>\;
  Dbg_WDATA_21(15) <= \<const0>\;
  Dbg_WDATA_21(14) <= \<const0>\;
  Dbg_WDATA_21(13) <= \<const0>\;
  Dbg_WDATA_21(12) <= \<const0>\;
  Dbg_WDATA_21(11) <= \<const0>\;
  Dbg_WDATA_21(10) <= \<const0>\;
  Dbg_WDATA_21(9) <= \<const0>\;
  Dbg_WDATA_21(8) <= \<const0>\;
  Dbg_WDATA_21(7) <= \<const0>\;
  Dbg_WDATA_21(6) <= \<const0>\;
  Dbg_WDATA_21(5) <= \<const0>\;
  Dbg_WDATA_21(4) <= \<const0>\;
  Dbg_WDATA_21(3) <= \<const0>\;
  Dbg_WDATA_21(2) <= \<const0>\;
  Dbg_WDATA_21(1) <= \<const0>\;
  Dbg_WDATA_21(0) <= \<const0>\;
  Dbg_WDATA_22(31) <= \<const0>\;
  Dbg_WDATA_22(30) <= \<const0>\;
  Dbg_WDATA_22(29) <= \<const0>\;
  Dbg_WDATA_22(28) <= \<const0>\;
  Dbg_WDATA_22(27) <= \<const0>\;
  Dbg_WDATA_22(26) <= \<const0>\;
  Dbg_WDATA_22(25) <= \<const0>\;
  Dbg_WDATA_22(24) <= \<const0>\;
  Dbg_WDATA_22(23) <= \<const0>\;
  Dbg_WDATA_22(22) <= \<const0>\;
  Dbg_WDATA_22(21) <= \<const0>\;
  Dbg_WDATA_22(20) <= \<const0>\;
  Dbg_WDATA_22(19) <= \<const0>\;
  Dbg_WDATA_22(18) <= \<const0>\;
  Dbg_WDATA_22(17) <= \<const0>\;
  Dbg_WDATA_22(16) <= \<const0>\;
  Dbg_WDATA_22(15) <= \<const0>\;
  Dbg_WDATA_22(14) <= \<const0>\;
  Dbg_WDATA_22(13) <= \<const0>\;
  Dbg_WDATA_22(12) <= \<const0>\;
  Dbg_WDATA_22(11) <= \<const0>\;
  Dbg_WDATA_22(10) <= \<const0>\;
  Dbg_WDATA_22(9) <= \<const0>\;
  Dbg_WDATA_22(8) <= \<const0>\;
  Dbg_WDATA_22(7) <= \<const0>\;
  Dbg_WDATA_22(6) <= \<const0>\;
  Dbg_WDATA_22(5) <= \<const0>\;
  Dbg_WDATA_22(4) <= \<const0>\;
  Dbg_WDATA_22(3) <= \<const0>\;
  Dbg_WDATA_22(2) <= \<const0>\;
  Dbg_WDATA_22(1) <= \<const0>\;
  Dbg_WDATA_22(0) <= \<const0>\;
  Dbg_WDATA_23(31) <= \<const0>\;
  Dbg_WDATA_23(30) <= \<const0>\;
  Dbg_WDATA_23(29) <= \<const0>\;
  Dbg_WDATA_23(28) <= \<const0>\;
  Dbg_WDATA_23(27) <= \<const0>\;
  Dbg_WDATA_23(26) <= \<const0>\;
  Dbg_WDATA_23(25) <= \<const0>\;
  Dbg_WDATA_23(24) <= \<const0>\;
  Dbg_WDATA_23(23) <= \<const0>\;
  Dbg_WDATA_23(22) <= \<const0>\;
  Dbg_WDATA_23(21) <= \<const0>\;
  Dbg_WDATA_23(20) <= \<const0>\;
  Dbg_WDATA_23(19) <= \<const0>\;
  Dbg_WDATA_23(18) <= \<const0>\;
  Dbg_WDATA_23(17) <= \<const0>\;
  Dbg_WDATA_23(16) <= \<const0>\;
  Dbg_WDATA_23(15) <= \<const0>\;
  Dbg_WDATA_23(14) <= \<const0>\;
  Dbg_WDATA_23(13) <= \<const0>\;
  Dbg_WDATA_23(12) <= \<const0>\;
  Dbg_WDATA_23(11) <= \<const0>\;
  Dbg_WDATA_23(10) <= \<const0>\;
  Dbg_WDATA_23(9) <= \<const0>\;
  Dbg_WDATA_23(8) <= \<const0>\;
  Dbg_WDATA_23(7) <= \<const0>\;
  Dbg_WDATA_23(6) <= \<const0>\;
  Dbg_WDATA_23(5) <= \<const0>\;
  Dbg_WDATA_23(4) <= \<const0>\;
  Dbg_WDATA_23(3) <= \<const0>\;
  Dbg_WDATA_23(2) <= \<const0>\;
  Dbg_WDATA_23(1) <= \<const0>\;
  Dbg_WDATA_23(0) <= \<const0>\;
  Dbg_WDATA_24(31) <= \<const0>\;
  Dbg_WDATA_24(30) <= \<const0>\;
  Dbg_WDATA_24(29) <= \<const0>\;
  Dbg_WDATA_24(28) <= \<const0>\;
  Dbg_WDATA_24(27) <= \<const0>\;
  Dbg_WDATA_24(26) <= \<const0>\;
  Dbg_WDATA_24(25) <= \<const0>\;
  Dbg_WDATA_24(24) <= \<const0>\;
  Dbg_WDATA_24(23) <= \<const0>\;
  Dbg_WDATA_24(22) <= \<const0>\;
  Dbg_WDATA_24(21) <= \<const0>\;
  Dbg_WDATA_24(20) <= \<const0>\;
  Dbg_WDATA_24(19) <= \<const0>\;
  Dbg_WDATA_24(18) <= \<const0>\;
  Dbg_WDATA_24(17) <= \<const0>\;
  Dbg_WDATA_24(16) <= \<const0>\;
  Dbg_WDATA_24(15) <= \<const0>\;
  Dbg_WDATA_24(14) <= \<const0>\;
  Dbg_WDATA_24(13) <= \<const0>\;
  Dbg_WDATA_24(12) <= \<const0>\;
  Dbg_WDATA_24(11) <= \<const0>\;
  Dbg_WDATA_24(10) <= \<const0>\;
  Dbg_WDATA_24(9) <= \<const0>\;
  Dbg_WDATA_24(8) <= \<const0>\;
  Dbg_WDATA_24(7) <= \<const0>\;
  Dbg_WDATA_24(6) <= \<const0>\;
  Dbg_WDATA_24(5) <= \<const0>\;
  Dbg_WDATA_24(4) <= \<const0>\;
  Dbg_WDATA_24(3) <= \<const0>\;
  Dbg_WDATA_24(2) <= \<const0>\;
  Dbg_WDATA_24(1) <= \<const0>\;
  Dbg_WDATA_24(0) <= \<const0>\;
  Dbg_WDATA_25(31) <= \<const0>\;
  Dbg_WDATA_25(30) <= \<const0>\;
  Dbg_WDATA_25(29) <= \<const0>\;
  Dbg_WDATA_25(28) <= \<const0>\;
  Dbg_WDATA_25(27) <= \<const0>\;
  Dbg_WDATA_25(26) <= \<const0>\;
  Dbg_WDATA_25(25) <= \<const0>\;
  Dbg_WDATA_25(24) <= \<const0>\;
  Dbg_WDATA_25(23) <= \<const0>\;
  Dbg_WDATA_25(22) <= \<const0>\;
  Dbg_WDATA_25(21) <= \<const0>\;
  Dbg_WDATA_25(20) <= \<const0>\;
  Dbg_WDATA_25(19) <= \<const0>\;
  Dbg_WDATA_25(18) <= \<const0>\;
  Dbg_WDATA_25(17) <= \<const0>\;
  Dbg_WDATA_25(16) <= \<const0>\;
  Dbg_WDATA_25(15) <= \<const0>\;
  Dbg_WDATA_25(14) <= \<const0>\;
  Dbg_WDATA_25(13) <= \<const0>\;
  Dbg_WDATA_25(12) <= \<const0>\;
  Dbg_WDATA_25(11) <= \<const0>\;
  Dbg_WDATA_25(10) <= \<const0>\;
  Dbg_WDATA_25(9) <= \<const0>\;
  Dbg_WDATA_25(8) <= \<const0>\;
  Dbg_WDATA_25(7) <= \<const0>\;
  Dbg_WDATA_25(6) <= \<const0>\;
  Dbg_WDATA_25(5) <= \<const0>\;
  Dbg_WDATA_25(4) <= \<const0>\;
  Dbg_WDATA_25(3) <= \<const0>\;
  Dbg_WDATA_25(2) <= \<const0>\;
  Dbg_WDATA_25(1) <= \<const0>\;
  Dbg_WDATA_25(0) <= \<const0>\;
  Dbg_WDATA_26(31) <= \<const0>\;
  Dbg_WDATA_26(30) <= \<const0>\;
  Dbg_WDATA_26(29) <= \<const0>\;
  Dbg_WDATA_26(28) <= \<const0>\;
  Dbg_WDATA_26(27) <= \<const0>\;
  Dbg_WDATA_26(26) <= \<const0>\;
  Dbg_WDATA_26(25) <= \<const0>\;
  Dbg_WDATA_26(24) <= \<const0>\;
  Dbg_WDATA_26(23) <= \<const0>\;
  Dbg_WDATA_26(22) <= \<const0>\;
  Dbg_WDATA_26(21) <= \<const0>\;
  Dbg_WDATA_26(20) <= \<const0>\;
  Dbg_WDATA_26(19) <= \<const0>\;
  Dbg_WDATA_26(18) <= \<const0>\;
  Dbg_WDATA_26(17) <= \<const0>\;
  Dbg_WDATA_26(16) <= \<const0>\;
  Dbg_WDATA_26(15) <= \<const0>\;
  Dbg_WDATA_26(14) <= \<const0>\;
  Dbg_WDATA_26(13) <= \<const0>\;
  Dbg_WDATA_26(12) <= \<const0>\;
  Dbg_WDATA_26(11) <= \<const0>\;
  Dbg_WDATA_26(10) <= \<const0>\;
  Dbg_WDATA_26(9) <= \<const0>\;
  Dbg_WDATA_26(8) <= \<const0>\;
  Dbg_WDATA_26(7) <= \<const0>\;
  Dbg_WDATA_26(6) <= \<const0>\;
  Dbg_WDATA_26(5) <= \<const0>\;
  Dbg_WDATA_26(4) <= \<const0>\;
  Dbg_WDATA_26(3) <= \<const0>\;
  Dbg_WDATA_26(2) <= \<const0>\;
  Dbg_WDATA_26(1) <= \<const0>\;
  Dbg_WDATA_26(0) <= \<const0>\;
  Dbg_WDATA_27(31) <= \<const0>\;
  Dbg_WDATA_27(30) <= \<const0>\;
  Dbg_WDATA_27(29) <= \<const0>\;
  Dbg_WDATA_27(28) <= \<const0>\;
  Dbg_WDATA_27(27) <= \<const0>\;
  Dbg_WDATA_27(26) <= \<const0>\;
  Dbg_WDATA_27(25) <= \<const0>\;
  Dbg_WDATA_27(24) <= \<const0>\;
  Dbg_WDATA_27(23) <= \<const0>\;
  Dbg_WDATA_27(22) <= \<const0>\;
  Dbg_WDATA_27(21) <= \<const0>\;
  Dbg_WDATA_27(20) <= \<const0>\;
  Dbg_WDATA_27(19) <= \<const0>\;
  Dbg_WDATA_27(18) <= \<const0>\;
  Dbg_WDATA_27(17) <= \<const0>\;
  Dbg_WDATA_27(16) <= \<const0>\;
  Dbg_WDATA_27(15) <= \<const0>\;
  Dbg_WDATA_27(14) <= \<const0>\;
  Dbg_WDATA_27(13) <= \<const0>\;
  Dbg_WDATA_27(12) <= \<const0>\;
  Dbg_WDATA_27(11) <= \<const0>\;
  Dbg_WDATA_27(10) <= \<const0>\;
  Dbg_WDATA_27(9) <= \<const0>\;
  Dbg_WDATA_27(8) <= \<const0>\;
  Dbg_WDATA_27(7) <= \<const0>\;
  Dbg_WDATA_27(6) <= \<const0>\;
  Dbg_WDATA_27(5) <= \<const0>\;
  Dbg_WDATA_27(4) <= \<const0>\;
  Dbg_WDATA_27(3) <= \<const0>\;
  Dbg_WDATA_27(2) <= \<const0>\;
  Dbg_WDATA_27(1) <= \<const0>\;
  Dbg_WDATA_27(0) <= \<const0>\;
  Dbg_WDATA_28(31) <= \<const0>\;
  Dbg_WDATA_28(30) <= \<const0>\;
  Dbg_WDATA_28(29) <= \<const0>\;
  Dbg_WDATA_28(28) <= \<const0>\;
  Dbg_WDATA_28(27) <= \<const0>\;
  Dbg_WDATA_28(26) <= \<const0>\;
  Dbg_WDATA_28(25) <= \<const0>\;
  Dbg_WDATA_28(24) <= \<const0>\;
  Dbg_WDATA_28(23) <= \<const0>\;
  Dbg_WDATA_28(22) <= \<const0>\;
  Dbg_WDATA_28(21) <= \<const0>\;
  Dbg_WDATA_28(20) <= \<const0>\;
  Dbg_WDATA_28(19) <= \<const0>\;
  Dbg_WDATA_28(18) <= \<const0>\;
  Dbg_WDATA_28(17) <= \<const0>\;
  Dbg_WDATA_28(16) <= \<const0>\;
  Dbg_WDATA_28(15) <= \<const0>\;
  Dbg_WDATA_28(14) <= \<const0>\;
  Dbg_WDATA_28(13) <= \<const0>\;
  Dbg_WDATA_28(12) <= \<const0>\;
  Dbg_WDATA_28(11) <= \<const0>\;
  Dbg_WDATA_28(10) <= \<const0>\;
  Dbg_WDATA_28(9) <= \<const0>\;
  Dbg_WDATA_28(8) <= \<const0>\;
  Dbg_WDATA_28(7) <= \<const0>\;
  Dbg_WDATA_28(6) <= \<const0>\;
  Dbg_WDATA_28(5) <= \<const0>\;
  Dbg_WDATA_28(4) <= \<const0>\;
  Dbg_WDATA_28(3) <= \<const0>\;
  Dbg_WDATA_28(2) <= \<const0>\;
  Dbg_WDATA_28(1) <= \<const0>\;
  Dbg_WDATA_28(0) <= \<const0>\;
  Dbg_WDATA_29(31) <= \<const0>\;
  Dbg_WDATA_29(30) <= \<const0>\;
  Dbg_WDATA_29(29) <= \<const0>\;
  Dbg_WDATA_29(28) <= \<const0>\;
  Dbg_WDATA_29(27) <= \<const0>\;
  Dbg_WDATA_29(26) <= \<const0>\;
  Dbg_WDATA_29(25) <= \<const0>\;
  Dbg_WDATA_29(24) <= \<const0>\;
  Dbg_WDATA_29(23) <= \<const0>\;
  Dbg_WDATA_29(22) <= \<const0>\;
  Dbg_WDATA_29(21) <= \<const0>\;
  Dbg_WDATA_29(20) <= \<const0>\;
  Dbg_WDATA_29(19) <= \<const0>\;
  Dbg_WDATA_29(18) <= \<const0>\;
  Dbg_WDATA_29(17) <= \<const0>\;
  Dbg_WDATA_29(16) <= \<const0>\;
  Dbg_WDATA_29(15) <= \<const0>\;
  Dbg_WDATA_29(14) <= \<const0>\;
  Dbg_WDATA_29(13) <= \<const0>\;
  Dbg_WDATA_29(12) <= \<const0>\;
  Dbg_WDATA_29(11) <= \<const0>\;
  Dbg_WDATA_29(10) <= \<const0>\;
  Dbg_WDATA_29(9) <= \<const0>\;
  Dbg_WDATA_29(8) <= \<const0>\;
  Dbg_WDATA_29(7) <= \<const0>\;
  Dbg_WDATA_29(6) <= \<const0>\;
  Dbg_WDATA_29(5) <= \<const0>\;
  Dbg_WDATA_29(4) <= \<const0>\;
  Dbg_WDATA_29(3) <= \<const0>\;
  Dbg_WDATA_29(2) <= \<const0>\;
  Dbg_WDATA_29(1) <= \<const0>\;
  Dbg_WDATA_29(0) <= \<const0>\;
  Dbg_WDATA_3(31) <= \<const0>\;
  Dbg_WDATA_3(30) <= \<const0>\;
  Dbg_WDATA_3(29) <= \<const0>\;
  Dbg_WDATA_3(28) <= \<const0>\;
  Dbg_WDATA_3(27) <= \<const0>\;
  Dbg_WDATA_3(26) <= \<const0>\;
  Dbg_WDATA_3(25) <= \<const0>\;
  Dbg_WDATA_3(24) <= \<const0>\;
  Dbg_WDATA_3(23) <= \<const0>\;
  Dbg_WDATA_3(22) <= \<const0>\;
  Dbg_WDATA_3(21) <= \<const0>\;
  Dbg_WDATA_3(20) <= \<const0>\;
  Dbg_WDATA_3(19) <= \<const0>\;
  Dbg_WDATA_3(18) <= \<const0>\;
  Dbg_WDATA_3(17) <= \<const0>\;
  Dbg_WDATA_3(16) <= \<const0>\;
  Dbg_WDATA_3(15) <= \<const0>\;
  Dbg_WDATA_3(14) <= \<const0>\;
  Dbg_WDATA_3(13) <= \<const0>\;
  Dbg_WDATA_3(12) <= \<const0>\;
  Dbg_WDATA_3(11) <= \<const0>\;
  Dbg_WDATA_3(10) <= \<const0>\;
  Dbg_WDATA_3(9) <= \<const0>\;
  Dbg_WDATA_3(8) <= \<const0>\;
  Dbg_WDATA_3(7) <= \<const0>\;
  Dbg_WDATA_3(6) <= \<const0>\;
  Dbg_WDATA_3(5) <= \<const0>\;
  Dbg_WDATA_3(4) <= \<const0>\;
  Dbg_WDATA_3(3) <= \<const0>\;
  Dbg_WDATA_3(2) <= \<const0>\;
  Dbg_WDATA_3(1) <= \<const0>\;
  Dbg_WDATA_3(0) <= \<const0>\;
  Dbg_WDATA_30(31) <= \<const0>\;
  Dbg_WDATA_30(30) <= \<const0>\;
  Dbg_WDATA_30(29) <= \<const0>\;
  Dbg_WDATA_30(28) <= \<const0>\;
  Dbg_WDATA_30(27) <= \<const0>\;
  Dbg_WDATA_30(26) <= \<const0>\;
  Dbg_WDATA_30(25) <= \<const0>\;
  Dbg_WDATA_30(24) <= \<const0>\;
  Dbg_WDATA_30(23) <= \<const0>\;
  Dbg_WDATA_30(22) <= \<const0>\;
  Dbg_WDATA_30(21) <= \<const0>\;
  Dbg_WDATA_30(20) <= \<const0>\;
  Dbg_WDATA_30(19) <= \<const0>\;
  Dbg_WDATA_30(18) <= \<const0>\;
  Dbg_WDATA_30(17) <= \<const0>\;
  Dbg_WDATA_30(16) <= \<const0>\;
  Dbg_WDATA_30(15) <= \<const0>\;
  Dbg_WDATA_30(14) <= \<const0>\;
  Dbg_WDATA_30(13) <= \<const0>\;
  Dbg_WDATA_30(12) <= \<const0>\;
  Dbg_WDATA_30(11) <= \<const0>\;
  Dbg_WDATA_30(10) <= \<const0>\;
  Dbg_WDATA_30(9) <= \<const0>\;
  Dbg_WDATA_30(8) <= \<const0>\;
  Dbg_WDATA_30(7) <= \<const0>\;
  Dbg_WDATA_30(6) <= \<const0>\;
  Dbg_WDATA_30(5) <= \<const0>\;
  Dbg_WDATA_30(4) <= \<const0>\;
  Dbg_WDATA_30(3) <= \<const0>\;
  Dbg_WDATA_30(2) <= \<const0>\;
  Dbg_WDATA_30(1) <= \<const0>\;
  Dbg_WDATA_30(0) <= \<const0>\;
  Dbg_WDATA_31(31) <= \<const0>\;
  Dbg_WDATA_31(30) <= \<const0>\;
  Dbg_WDATA_31(29) <= \<const0>\;
  Dbg_WDATA_31(28) <= \<const0>\;
  Dbg_WDATA_31(27) <= \<const0>\;
  Dbg_WDATA_31(26) <= \<const0>\;
  Dbg_WDATA_31(25) <= \<const0>\;
  Dbg_WDATA_31(24) <= \<const0>\;
  Dbg_WDATA_31(23) <= \<const0>\;
  Dbg_WDATA_31(22) <= \<const0>\;
  Dbg_WDATA_31(21) <= \<const0>\;
  Dbg_WDATA_31(20) <= \<const0>\;
  Dbg_WDATA_31(19) <= \<const0>\;
  Dbg_WDATA_31(18) <= \<const0>\;
  Dbg_WDATA_31(17) <= \<const0>\;
  Dbg_WDATA_31(16) <= \<const0>\;
  Dbg_WDATA_31(15) <= \<const0>\;
  Dbg_WDATA_31(14) <= \<const0>\;
  Dbg_WDATA_31(13) <= \<const0>\;
  Dbg_WDATA_31(12) <= \<const0>\;
  Dbg_WDATA_31(11) <= \<const0>\;
  Dbg_WDATA_31(10) <= \<const0>\;
  Dbg_WDATA_31(9) <= \<const0>\;
  Dbg_WDATA_31(8) <= \<const0>\;
  Dbg_WDATA_31(7) <= \<const0>\;
  Dbg_WDATA_31(6) <= \<const0>\;
  Dbg_WDATA_31(5) <= \<const0>\;
  Dbg_WDATA_31(4) <= \<const0>\;
  Dbg_WDATA_31(3) <= \<const0>\;
  Dbg_WDATA_31(2) <= \<const0>\;
  Dbg_WDATA_31(1) <= \<const0>\;
  Dbg_WDATA_31(0) <= \<const0>\;
  Dbg_WDATA_4(31) <= \<const0>\;
  Dbg_WDATA_4(30) <= \<const0>\;
  Dbg_WDATA_4(29) <= \<const0>\;
  Dbg_WDATA_4(28) <= \<const0>\;
  Dbg_WDATA_4(27) <= \<const0>\;
  Dbg_WDATA_4(26) <= \<const0>\;
  Dbg_WDATA_4(25) <= \<const0>\;
  Dbg_WDATA_4(24) <= \<const0>\;
  Dbg_WDATA_4(23) <= \<const0>\;
  Dbg_WDATA_4(22) <= \<const0>\;
  Dbg_WDATA_4(21) <= \<const0>\;
  Dbg_WDATA_4(20) <= \<const0>\;
  Dbg_WDATA_4(19) <= \<const0>\;
  Dbg_WDATA_4(18) <= \<const0>\;
  Dbg_WDATA_4(17) <= \<const0>\;
  Dbg_WDATA_4(16) <= \<const0>\;
  Dbg_WDATA_4(15) <= \<const0>\;
  Dbg_WDATA_4(14) <= \<const0>\;
  Dbg_WDATA_4(13) <= \<const0>\;
  Dbg_WDATA_4(12) <= \<const0>\;
  Dbg_WDATA_4(11) <= \<const0>\;
  Dbg_WDATA_4(10) <= \<const0>\;
  Dbg_WDATA_4(9) <= \<const0>\;
  Dbg_WDATA_4(8) <= \<const0>\;
  Dbg_WDATA_4(7) <= \<const0>\;
  Dbg_WDATA_4(6) <= \<const0>\;
  Dbg_WDATA_4(5) <= \<const0>\;
  Dbg_WDATA_4(4) <= \<const0>\;
  Dbg_WDATA_4(3) <= \<const0>\;
  Dbg_WDATA_4(2) <= \<const0>\;
  Dbg_WDATA_4(1) <= \<const0>\;
  Dbg_WDATA_4(0) <= \<const0>\;
  Dbg_WDATA_5(31) <= \<const0>\;
  Dbg_WDATA_5(30) <= \<const0>\;
  Dbg_WDATA_5(29) <= \<const0>\;
  Dbg_WDATA_5(28) <= \<const0>\;
  Dbg_WDATA_5(27) <= \<const0>\;
  Dbg_WDATA_5(26) <= \<const0>\;
  Dbg_WDATA_5(25) <= \<const0>\;
  Dbg_WDATA_5(24) <= \<const0>\;
  Dbg_WDATA_5(23) <= \<const0>\;
  Dbg_WDATA_5(22) <= \<const0>\;
  Dbg_WDATA_5(21) <= \<const0>\;
  Dbg_WDATA_5(20) <= \<const0>\;
  Dbg_WDATA_5(19) <= \<const0>\;
  Dbg_WDATA_5(18) <= \<const0>\;
  Dbg_WDATA_5(17) <= \<const0>\;
  Dbg_WDATA_5(16) <= \<const0>\;
  Dbg_WDATA_5(15) <= \<const0>\;
  Dbg_WDATA_5(14) <= \<const0>\;
  Dbg_WDATA_5(13) <= \<const0>\;
  Dbg_WDATA_5(12) <= \<const0>\;
  Dbg_WDATA_5(11) <= \<const0>\;
  Dbg_WDATA_5(10) <= \<const0>\;
  Dbg_WDATA_5(9) <= \<const0>\;
  Dbg_WDATA_5(8) <= \<const0>\;
  Dbg_WDATA_5(7) <= \<const0>\;
  Dbg_WDATA_5(6) <= \<const0>\;
  Dbg_WDATA_5(5) <= \<const0>\;
  Dbg_WDATA_5(4) <= \<const0>\;
  Dbg_WDATA_5(3) <= \<const0>\;
  Dbg_WDATA_5(2) <= \<const0>\;
  Dbg_WDATA_5(1) <= \<const0>\;
  Dbg_WDATA_5(0) <= \<const0>\;
  Dbg_WDATA_6(31) <= \<const0>\;
  Dbg_WDATA_6(30) <= \<const0>\;
  Dbg_WDATA_6(29) <= \<const0>\;
  Dbg_WDATA_6(28) <= \<const0>\;
  Dbg_WDATA_6(27) <= \<const0>\;
  Dbg_WDATA_6(26) <= \<const0>\;
  Dbg_WDATA_6(25) <= \<const0>\;
  Dbg_WDATA_6(24) <= \<const0>\;
  Dbg_WDATA_6(23) <= \<const0>\;
  Dbg_WDATA_6(22) <= \<const0>\;
  Dbg_WDATA_6(21) <= \<const0>\;
  Dbg_WDATA_6(20) <= \<const0>\;
  Dbg_WDATA_6(19) <= \<const0>\;
  Dbg_WDATA_6(18) <= \<const0>\;
  Dbg_WDATA_6(17) <= \<const0>\;
  Dbg_WDATA_6(16) <= \<const0>\;
  Dbg_WDATA_6(15) <= \<const0>\;
  Dbg_WDATA_6(14) <= \<const0>\;
  Dbg_WDATA_6(13) <= \<const0>\;
  Dbg_WDATA_6(12) <= \<const0>\;
  Dbg_WDATA_6(11) <= \<const0>\;
  Dbg_WDATA_6(10) <= \<const0>\;
  Dbg_WDATA_6(9) <= \<const0>\;
  Dbg_WDATA_6(8) <= \<const0>\;
  Dbg_WDATA_6(7) <= \<const0>\;
  Dbg_WDATA_6(6) <= \<const0>\;
  Dbg_WDATA_6(5) <= \<const0>\;
  Dbg_WDATA_6(4) <= \<const0>\;
  Dbg_WDATA_6(3) <= \<const0>\;
  Dbg_WDATA_6(2) <= \<const0>\;
  Dbg_WDATA_6(1) <= \<const0>\;
  Dbg_WDATA_6(0) <= \<const0>\;
  Dbg_WDATA_7(31) <= \<const0>\;
  Dbg_WDATA_7(30) <= \<const0>\;
  Dbg_WDATA_7(29) <= \<const0>\;
  Dbg_WDATA_7(28) <= \<const0>\;
  Dbg_WDATA_7(27) <= \<const0>\;
  Dbg_WDATA_7(26) <= \<const0>\;
  Dbg_WDATA_7(25) <= \<const0>\;
  Dbg_WDATA_7(24) <= \<const0>\;
  Dbg_WDATA_7(23) <= \<const0>\;
  Dbg_WDATA_7(22) <= \<const0>\;
  Dbg_WDATA_7(21) <= \<const0>\;
  Dbg_WDATA_7(20) <= \<const0>\;
  Dbg_WDATA_7(19) <= \<const0>\;
  Dbg_WDATA_7(18) <= \<const0>\;
  Dbg_WDATA_7(17) <= \<const0>\;
  Dbg_WDATA_7(16) <= \<const0>\;
  Dbg_WDATA_7(15) <= \<const0>\;
  Dbg_WDATA_7(14) <= \<const0>\;
  Dbg_WDATA_7(13) <= \<const0>\;
  Dbg_WDATA_7(12) <= \<const0>\;
  Dbg_WDATA_7(11) <= \<const0>\;
  Dbg_WDATA_7(10) <= \<const0>\;
  Dbg_WDATA_7(9) <= \<const0>\;
  Dbg_WDATA_7(8) <= \<const0>\;
  Dbg_WDATA_7(7) <= \<const0>\;
  Dbg_WDATA_7(6) <= \<const0>\;
  Dbg_WDATA_7(5) <= \<const0>\;
  Dbg_WDATA_7(4) <= \<const0>\;
  Dbg_WDATA_7(3) <= \<const0>\;
  Dbg_WDATA_7(2) <= \<const0>\;
  Dbg_WDATA_7(1) <= \<const0>\;
  Dbg_WDATA_7(0) <= \<const0>\;
  Dbg_WDATA_8(31) <= \<const0>\;
  Dbg_WDATA_8(30) <= \<const0>\;
  Dbg_WDATA_8(29) <= \<const0>\;
  Dbg_WDATA_8(28) <= \<const0>\;
  Dbg_WDATA_8(27) <= \<const0>\;
  Dbg_WDATA_8(26) <= \<const0>\;
  Dbg_WDATA_8(25) <= \<const0>\;
  Dbg_WDATA_8(24) <= \<const0>\;
  Dbg_WDATA_8(23) <= \<const0>\;
  Dbg_WDATA_8(22) <= \<const0>\;
  Dbg_WDATA_8(21) <= \<const0>\;
  Dbg_WDATA_8(20) <= \<const0>\;
  Dbg_WDATA_8(19) <= \<const0>\;
  Dbg_WDATA_8(18) <= \<const0>\;
  Dbg_WDATA_8(17) <= \<const0>\;
  Dbg_WDATA_8(16) <= \<const0>\;
  Dbg_WDATA_8(15) <= \<const0>\;
  Dbg_WDATA_8(14) <= \<const0>\;
  Dbg_WDATA_8(13) <= \<const0>\;
  Dbg_WDATA_8(12) <= \<const0>\;
  Dbg_WDATA_8(11) <= \<const0>\;
  Dbg_WDATA_8(10) <= \<const0>\;
  Dbg_WDATA_8(9) <= \<const0>\;
  Dbg_WDATA_8(8) <= \<const0>\;
  Dbg_WDATA_8(7) <= \<const0>\;
  Dbg_WDATA_8(6) <= \<const0>\;
  Dbg_WDATA_8(5) <= \<const0>\;
  Dbg_WDATA_8(4) <= \<const0>\;
  Dbg_WDATA_8(3) <= \<const0>\;
  Dbg_WDATA_8(2) <= \<const0>\;
  Dbg_WDATA_8(1) <= \<const0>\;
  Dbg_WDATA_8(0) <= \<const0>\;
  Dbg_WDATA_9(31) <= \<const0>\;
  Dbg_WDATA_9(30) <= \<const0>\;
  Dbg_WDATA_9(29) <= \<const0>\;
  Dbg_WDATA_9(28) <= \<const0>\;
  Dbg_WDATA_9(27) <= \<const0>\;
  Dbg_WDATA_9(26) <= \<const0>\;
  Dbg_WDATA_9(25) <= \<const0>\;
  Dbg_WDATA_9(24) <= \<const0>\;
  Dbg_WDATA_9(23) <= \<const0>\;
  Dbg_WDATA_9(22) <= \<const0>\;
  Dbg_WDATA_9(21) <= \<const0>\;
  Dbg_WDATA_9(20) <= \<const0>\;
  Dbg_WDATA_9(19) <= \<const0>\;
  Dbg_WDATA_9(18) <= \<const0>\;
  Dbg_WDATA_9(17) <= \<const0>\;
  Dbg_WDATA_9(16) <= \<const0>\;
  Dbg_WDATA_9(15) <= \<const0>\;
  Dbg_WDATA_9(14) <= \<const0>\;
  Dbg_WDATA_9(13) <= \<const0>\;
  Dbg_WDATA_9(12) <= \<const0>\;
  Dbg_WDATA_9(11) <= \<const0>\;
  Dbg_WDATA_9(10) <= \<const0>\;
  Dbg_WDATA_9(9) <= \<const0>\;
  Dbg_WDATA_9(8) <= \<const0>\;
  Dbg_WDATA_9(7) <= \<const0>\;
  Dbg_WDATA_9(6) <= \<const0>\;
  Dbg_WDATA_9(5) <= \<const0>\;
  Dbg_WDATA_9(4) <= \<const0>\;
  Dbg_WDATA_9(3) <= \<const0>\;
  Dbg_WDATA_9(2) <= \<const0>\;
  Dbg_WDATA_9(1) <= \<const0>\;
  Dbg_WDATA_9(0) <= \<const0>\;
  Dbg_WVALID_0 <= \<const0>\;
  Dbg_WVALID_1 <= \<const0>\;
  Dbg_WVALID_10 <= \<const0>\;
  Dbg_WVALID_11 <= \<const0>\;
  Dbg_WVALID_12 <= \<const0>\;
  Dbg_WVALID_13 <= \<const0>\;
  Dbg_WVALID_14 <= \<const0>\;
  Dbg_WVALID_15 <= \<const0>\;
  Dbg_WVALID_16 <= \<const0>\;
  Dbg_WVALID_17 <= \<const0>\;
  Dbg_WVALID_18 <= \<const0>\;
  Dbg_WVALID_19 <= \<const0>\;
  Dbg_WVALID_2 <= \<const0>\;
  Dbg_WVALID_20 <= \<const0>\;
  Dbg_WVALID_21 <= \<const0>\;
  Dbg_WVALID_22 <= \<const0>\;
  Dbg_WVALID_23 <= \<const0>\;
  Dbg_WVALID_24 <= \<const0>\;
  Dbg_WVALID_25 <= \<const0>\;
  Dbg_WVALID_26 <= \<const0>\;
  Dbg_WVALID_27 <= \<const0>\;
  Dbg_WVALID_28 <= \<const0>\;
  Dbg_WVALID_29 <= \<const0>\;
  Dbg_WVALID_3 <= \<const0>\;
  Dbg_WVALID_30 <= \<const0>\;
  Dbg_WVALID_31 <= \<const0>\;
  Dbg_WVALID_4 <= \<const0>\;
  Dbg_WVALID_5 <= \<const0>\;
  Dbg_WVALID_6 <= \<const0>\;
  Dbg_WVALID_7 <= \<const0>\;
  Dbg_WVALID_8 <= \<const0>\;
  Dbg_WVALID_9 <= \<const0>\;
  Ext_BRK <= \<const0>\;
  Ext_JTAG_CAPTURE <= \<const0>\;
  Ext_JTAG_DRCK <= \<const0>\;
  Ext_JTAG_RESET <= \<const0>\;
  Ext_JTAG_SEL <= \<const0>\;
  Ext_JTAG_SHIFT <= \<const0>\;
  Ext_JTAG_TDI <= \^dbg_tdi_0\;
  Ext_JTAG_UPDATE <= \<const0>\;
  Ext_NM_BRK <= \<const0>\;
  Interrupt <= \<const0>\;
  LMB_Addr_Strobe_0 <= \<const0>\;
  LMB_Addr_Strobe_1 <= \<const0>\;
  LMB_Addr_Strobe_10 <= \<const0>\;
  LMB_Addr_Strobe_11 <= \<const0>\;
  LMB_Addr_Strobe_12 <= \<const0>\;
  LMB_Addr_Strobe_13 <= \<const0>\;
  LMB_Addr_Strobe_14 <= \<const0>\;
  LMB_Addr_Strobe_15 <= \<const0>\;
  LMB_Addr_Strobe_16 <= \<const0>\;
  LMB_Addr_Strobe_17 <= \<const0>\;
  LMB_Addr_Strobe_18 <= \<const0>\;
  LMB_Addr_Strobe_19 <= \<const0>\;
  LMB_Addr_Strobe_2 <= \<const0>\;
  LMB_Addr_Strobe_20 <= \<const0>\;
  LMB_Addr_Strobe_21 <= \<const0>\;
  LMB_Addr_Strobe_22 <= \<const0>\;
  LMB_Addr_Strobe_23 <= \<const0>\;
  LMB_Addr_Strobe_24 <= \<const0>\;
  LMB_Addr_Strobe_25 <= \<const0>\;
  LMB_Addr_Strobe_26 <= \<const0>\;
  LMB_Addr_Strobe_27 <= \<const0>\;
  LMB_Addr_Strobe_28 <= \<const0>\;
  LMB_Addr_Strobe_29 <= \<const0>\;
  LMB_Addr_Strobe_3 <= \<const0>\;
  LMB_Addr_Strobe_30 <= \<const0>\;
  LMB_Addr_Strobe_31 <= \<const0>\;
  LMB_Addr_Strobe_4 <= \<const0>\;
  LMB_Addr_Strobe_5 <= \<const0>\;
  LMB_Addr_Strobe_6 <= \<const0>\;
  LMB_Addr_Strobe_7 <= \<const0>\;
  LMB_Addr_Strobe_8 <= \<const0>\;
  LMB_Addr_Strobe_9 <= \<const0>\;
  LMB_Byte_Enable_0(0) <= \<const0>\;
  LMB_Byte_Enable_0(1) <= \<const0>\;
  LMB_Byte_Enable_0(2) <= \<const0>\;
  LMB_Byte_Enable_0(3) <= \<const0>\;
  LMB_Byte_Enable_1(0) <= \<const0>\;
  LMB_Byte_Enable_1(1) <= \<const0>\;
  LMB_Byte_Enable_1(2) <= \<const0>\;
  LMB_Byte_Enable_1(3) <= \<const0>\;
  LMB_Byte_Enable_10(0) <= \<const0>\;
  LMB_Byte_Enable_10(1) <= \<const0>\;
  LMB_Byte_Enable_10(2) <= \<const0>\;
  LMB_Byte_Enable_10(3) <= \<const0>\;
  LMB_Byte_Enable_11(0) <= \<const0>\;
  LMB_Byte_Enable_11(1) <= \<const0>\;
  LMB_Byte_Enable_11(2) <= \<const0>\;
  LMB_Byte_Enable_11(3) <= \<const0>\;
  LMB_Byte_Enable_12(0) <= \<const0>\;
  LMB_Byte_Enable_12(1) <= \<const0>\;
  LMB_Byte_Enable_12(2) <= \<const0>\;
  LMB_Byte_Enable_12(3) <= \<const0>\;
  LMB_Byte_Enable_13(0) <= \<const0>\;
  LMB_Byte_Enable_13(1) <= \<const0>\;
  LMB_Byte_Enable_13(2) <= \<const0>\;
  LMB_Byte_Enable_13(3) <= \<const0>\;
  LMB_Byte_Enable_14(0) <= \<const0>\;
  LMB_Byte_Enable_14(1) <= \<const0>\;
  LMB_Byte_Enable_14(2) <= \<const0>\;
  LMB_Byte_Enable_14(3) <= \<const0>\;
  LMB_Byte_Enable_15(0) <= \<const0>\;
  LMB_Byte_Enable_15(1) <= \<const0>\;
  LMB_Byte_Enable_15(2) <= \<const0>\;
  LMB_Byte_Enable_15(3) <= \<const0>\;
  LMB_Byte_Enable_16(0) <= \<const0>\;
  LMB_Byte_Enable_16(1) <= \<const0>\;
  LMB_Byte_Enable_16(2) <= \<const0>\;
  LMB_Byte_Enable_16(3) <= \<const0>\;
  LMB_Byte_Enable_17(0) <= \<const0>\;
  LMB_Byte_Enable_17(1) <= \<const0>\;
  LMB_Byte_Enable_17(2) <= \<const0>\;
  LMB_Byte_Enable_17(3) <= \<const0>\;
  LMB_Byte_Enable_18(0) <= \<const0>\;
  LMB_Byte_Enable_18(1) <= \<const0>\;
  LMB_Byte_Enable_18(2) <= \<const0>\;
  LMB_Byte_Enable_18(3) <= \<const0>\;
  LMB_Byte_Enable_19(0) <= \<const0>\;
  LMB_Byte_Enable_19(1) <= \<const0>\;
  LMB_Byte_Enable_19(2) <= \<const0>\;
  LMB_Byte_Enable_19(3) <= \<const0>\;
  LMB_Byte_Enable_2(0) <= \<const0>\;
  LMB_Byte_Enable_2(1) <= \<const0>\;
  LMB_Byte_Enable_2(2) <= \<const0>\;
  LMB_Byte_Enable_2(3) <= \<const0>\;
  LMB_Byte_Enable_20(0) <= \<const0>\;
  LMB_Byte_Enable_20(1) <= \<const0>\;
  LMB_Byte_Enable_20(2) <= \<const0>\;
  LMB_Byte_Enable_20(3) <= \<const0>\;
  LMB_Byte_Enable_21(0) <= \<const0>\;
  LMB_Byte_Enable_21(1) <= \<const0>\;
  LMB_Byte_Enable_21(2) <= \<const0>\;
  LMB_Byte_Enable_21(3) <= \<const0>\;
  LMB_Byte_Enable_22(0) <= \<const0>\;
  LMB_Byte_Enable_22(1) <= \<const0>\;
  LMB_Byte_Enable_22(2) <= \<const0>\;
  LMB_Byte_Enable_22(3) <= \<const0>\;
  LMB_Byte_Enable_23(0) <= \<const0>\;
  LMB_Byte_Enable_23(1) <= \<const0>\;
  LMB_Byte_Enable_23(2) <= \<const0>\;
  LMB_Byte_Enable_23(3) <= \<const0>\;
  LMB_Byte_Enable_24(0) <= \<const0>\;
  LMB_Byte_Enable_24(1) <= \<const0>\;
  LMB_Byte_Enable_24(2) <= \<const0>\;
  LMB_Byte_Enable_24(3) <= \<const0>\;
  LMB_Byte_Enable_25(0) <= \<const0>\;
  LMB_Byte_Enable_25(1) <= \<const0>\;
  LMB_Byte_Enable_25(2) <= \<const0>\;
  LMB_Byte_Enable_25(3) <= \<const0>\;
  LMB_Byte_Enable_26(0) <= \<const0>\;
  LMB_Byte_Enable_26(1) <= \<const0>\;
  LMB_Byte_Enable_26(2) <= \<const0>\;
  LMB_Byte_Enable_26(3) <= \<const0>\;
  LMB_Byte_Enable_27(0) <= \<const0>\;
  LMB_Byte_Enable_27(1) <= \<const0>\;
  LMB_Byte_Enable_27(2) <= \<const0>\;
  LMB_Byte_Enable_27(3) <= \<const0>\;
  LMB_Byte_Enable_28(0) <= \<const0>\;
  LMB_Byte_Enable_28(1) <= \<const0>\;
  LMB_Byte_Enable_28(2) <= \<const0>\;
  LMB_Byte_Enable_28(3) <= \<const0>\;
  LMB_Byte_Enable_29(0) <= \<const0>\;
  LMB_Byte_Enable_29(1) <= \<const0>\;
  LMB_Byte_Enable_29(2) <= \<const0>\;
  LMB_Byte_Enable_29(3) <= \<const0>\;
  LMB_Byte_Enable_3(0) <= \<const0>\;
  LMB_Byte_Enable_3(1) <= \<const0>\;
  LMB_Byte_Enable_3(2) <= \<const0>\;
  LMB_Byte_Enable_3(3) <= \<const0>\;
  LMB_Byte_Enable_30(0) <= \<const0>\;
  LMB_Byte_Enable_30(1) <= \<const0>\;
  LMB_Byte_Enable_30(2) <= \<const0>\;
  LMB_Byte_Enable_30(3) <= \<const0>\;
  LMB_Byte_Enable_31(0) <= \<const0>\;
  LMB_Byte_Enable_31(1) <= \<const0>\;
  LMB_Byte_Enable_31(2) <= \<const0>\;
  LMB_Byte_Enable_31(3) <= \<const0>\;
  LMB_Byte_Enable_4(0) <= \<const0>\;
  LMB_Byte_Enable_4(1) <= \<const0>\;
  LMB_Byte_Enable_4(2) <= \<const0>\;
  LMB_Byte_Enable_4(3) <= \<const0>\;
  LMB_Byte_Enable_5(0) <= \<const0>\;
  LMB_Byte_Enable_5(1) <= \<const0>\;
  LMB_Byte_Enable_5(2) <= \<const0>\;
  LMB_Byte_Enable_5(3) <= \<const0>\;
  LMB_Byte_Enable_6(0) <= \<const0>\;
  LMB_Byte_Enable_6(1) <= \<const0>\;
  LMB_Byte_Enable_6(2) <= \<const0>\;
  LMB_Byte_Enable_6(3) <= \<const0>\;
  LMB_Byte_Enable_7(0) <= \<const0>\;
  LMB_Byte_Enable_7(1) <= \<const0>\;
  LMB_Byte_Enable_7(2) <= \<const0>\;
  LMB_Byte_Enable_7(3) <= \<const0>\;
  LMB_Byte_Enable_8(0) <= \<const0>\;
  LMB_Byte_Enable_8(1) <= \<const0>\;
  LMB_Byte_Enable_8(2) <= \<const0>\;
  LMB_Byte_Enable_8(3) <= \<const0>\;
  LMB_Byte_Enable_9(0) <= \<const0>\;
  LMB_Byte_Enable_9(1) <= \<const0>\;
  LMB_Byte_Enable_9(2) <= \<const0>\;
  LMB_Byte_Enable_9(3) <= \<const0>\;
  LMB_Data_Addr_0(0) <= \<const0>\;
  LMB_Data_Addr_0(1) <= \<const0>\;
  LMB_Data_Addr_0(2) <= \<const0>\;
  LMB_Data_Addr_0(3) <= \<const0>\;
  LMB_Data_Addr_0(4) <= \<const0>\;
  LMB_Data_Addr_0(5) <= \<const0>\;
  LMB_Data_Addr_0(6) <= \<const0>\;
  LMB_Data_Addr_0(7) <= \<const0>\;
  LMB_Data_Addr_0(8) <= \<const0>\;
  LMB_Data_Addr_0(9) <= \<const0>\;
  LMB_Data_Addr_0(10) <= \<const0>\;
  LMB_Data_Addr_0(11) <= \<const0>\;
  LMB_Data_Addr_0(12) <= \<const0>\;
  LMB_Data_Addr_0(13) <= \<const0>\;
  LMB_Data_Addr_0(14) <= \<const0>\;
  LMB_Data_Addr_0(15) <= \<const0>\;
  LMB_Data_Addr_0(16) <= \<const0>\;
  LMB_Data_Addr_0(17) <= \<const0>\;
  LMB_Data_Addr_0(18) <= \<const0>\;
  LMB_Data_Addr_0(19) <= \<const0>\;
  LMB_Data_Addr_0(20) <= \<const0>\;
  LMB_Data_Addr_0(21) <= \<const0>\;
  LMB_Data_Addr_0(22) <= \<const0>\;
  LMB_Data_Addr_0(23) <= \<const0>\;
  LMB_Data_Addr_0(24) <= \<const0>\;
  LMB_Data_Addr_0(25) <= \<const0>\;
  LMB_Data_Addr_0(26) <= \<const0>\;
  LMB_Data_Addr_0(27) <= \<const0>\;
  LMB_Data_Addr_0(28) <= \<const0>\;
  LMB_Data_Addr_0(29) <= \<const0>\;
  LMB_Data_Addr_0(30) <= \<const0>\;
  LMB_Data_Addr_0(31) <= \<const0>\;
  LMB_Data_Addr_1(0) <= \<const0>\;
  LMB_Data_Addr_1(1) <= \<const0>\;
  LMB_Data_Addr_1(2) <= \<const0>\;
  LMB_Data_Addr_1(3) <= \<const0>\;
  LMB_Data_Addr_1(4) <= \<const0>\;
  LMB_Data_Addr_1(5) <= \<const0>\;
  LMB_Data_Addr_1(6) <= \<const0>\;
  LMB_Data_Addr_1(7) <= \<const0>\;
  LMB_Data_Addr_1(8) <= \<const0>\;
  LMB_Data_Addr_1(9) <= \<const0>\;
  LMB_Data_Addr_1(10) <= \<const0>\;
  LMB_Data_Addr_1(11) <= \<const0>\;
  LMB_Data_Addr_1(12) <= \<const0>\;
  LMB_Data_Addr_1(13) <= \<const0>\;
  LMB_Data_Addr_1(14) <= \<const0>\;
  LMB_Data_Addr_1(15) <= \<const0>\;
  LMB_Data_Addr_1(16) <= \<const0>\;
  LMB_Data_Addr_1(17) <= \<const0>\;
  LMB_Data_Addr_1(18) <= \<const0>\;
  LMB_Data_Addr_1(19) <= \<const0>\;
  LMB_Data_Addr_1(20) <= \<const0>\;
  LMB_Data_Addr_1(21) <= \<const0>\;
  LMB_Data_Addr_1(22) <= \<const0>\;
  LMB_Data_Addr_1(23) <= \<const0>\;
  LMB_Data_Addr_1(24) <= \<const0>\;
  LMB_Data_Addr_1(25) <= \<const0>\;
  LMB_Data_Addr_1(26) <= \<const0>\;
  LMB_Data_Addr_1(27) <= \<const0>\;
  LMB_Data_Addr_1(28) <= \<const0>\;
  LMB_Data_Addr_1(29) <= \<const0>\;
  LMB_Data_Addr_1(30) <= \<const0>\;
  LMB_Data_Addr_1(31) <= \<const0>\;
  LMB_Data_Addr_10(0) <= \<const0>\;
  LMB_Data_Addr_10(1) <= \<const0>\;
  LMB_Data_Addr_10(2) <= \<const0>\;
  LMB_Data_Addr_10(3) <= \<const0>\;
  LMB_Data_Addr_10(4) <= \<const0>\;
  LMB_Data_Addr_10(5) <= \<const0>\;
  LMB_Data_Addr_10(6) <= \<const0>\;
  LMB_Data_Addr_10(7) <= \<const0>\;
  LMB_Data_Addr_10(8) <= \<const0>\;
  LMB_Data_Addr_10(9) <= \<const0>\;
  LMB_Data_Addr_10(10) <= \<const0>\;
  LMB_Data_Addr_10(11) <= \<const0>\;
  LMB_Data_Addr_10(12) <= \<const0>\;
  LMB_Data_Addr_10(13) <= \<const0>\;
  LMB_Data_Addr_10(14) <= \<const0>\;
  LMB_Data_Addr_10(15) <= \<const0>\;
  LMB_Data_Addr_10(16) <= \<const0>\;
  LMB_Data_Addr_10(17) <= \<const0>\;
  LMB_Data_Addr_10(18) <= \<const0>\;
  LMB_Data_Addr_10(19) <= \<const0>\;
  LMB_Data_Addr_10(20) <= \<const0>\;
  LMB_Data_Addr_10(21) <= \<const0>\;
  LMB_Data_Addr_10(22) <= \<const0>\;
  LMB_Data_Addr_10(23) <= \<const0>\;
  LMB_Data_Addr_10(24) <= \<const0>\;
  LMB_Data_Addr_10(25) <= \<const0>\;
  LMB_Data_Addr_10(26) <= \<const0>\;
  LMB_Data_Addr_10(27) <= \<const0>\;
  LMB_Data_Addr_10(28) <= \<const0>\;
  LMB_Data_Addr_10(29) <= \<const0>\;
  LMB_Data_Addr_10(30) <= \<const0>\;
  LMB_Data_Addr_10(31) <= \<const0>\;
  LMB_Data_Addr_11(0) <= \<const0>\;
  LMB_Data_Addr_11(1) <= \<const0>\;
  LMB_Data_Addr_11(2) <= \<const0>\;
  LMB_Data_Addr_11(3) <= \<const0>\;
  LMB_Data_Addr_11(4) <= \<const0>\;
  LMB_Data_Addr_11(5) <= \<const0>\;
  LMB_Data_Addr_11(6) <= \<const0>\;
  LMB_Data_Addr_11(7) <= \<const0>\;
  LMB_Data_Addr_11(8) <= \<const0>\;
  LMB_Data_Addr_11(9) <= \<const0>\;
  LMB_Data_Addr_11(10) <= \<const0>\;
  LMB_Data_Addr_11(11) <= \<const0>\;
  LMB_Data_Addr_11(12) <= \<const0>\;
  LMB_Data_Addr_11(13) <= \<const0>\;
  LMB_Data_Addr_11(14) <= \<const0>\;
  LMB_Data_Addr_11(15) <= \<const0>\;
  LMB_Data_Addr_11(16) <= \<const0>\;
  LMB_Data_Addr_11(17) <= \<const0>\;
  LMB_Data_Addr_11(18) <= \<const0>\;
  LMB_Data_Addr_11(19) <= \<const0>\;
  LMB_Data_Addr_11(20) <= \<const0>\;
  LMB_Data_Addr_11(21) <= \<const0>\;
  LMB_Data_Addr_11(22) <= \<const0>\;
  LMB_Data_Addr_11(23) <= \<const0>\;
  LMB_Data_Addr_11(24) <= \<const0>\;
  LMB_Data_Addr_11(25) <= \<const0>\;
  LMB_Data_Addr_11(26) <= \<const0>\;
  LMB_Data_Addr_11(27) <= \<const0>\;
  LMB_Data_Addr_11(28) <= \<const0>\;
  LMB_Data_Addr_11(29) <= \<const0>\;
  LMB_Data_Addr_11(30) <= \<const0>\;
  LMB_Data_Addr_11(31) <= \<const0>\;
  LMB_Data_Addr_12(0) <= \<const0>\;
  LMB_Data_Addr_12(1) <= \<const0>\;
  LMB_Data_Addr_12(2) <= \<const0>\;
  LMB_Data_Addr_12(3) <= \<const0>\;
  LMB_Data_Addr_12(4) <= \<const0>\;
  LMB_Data_Addr_12(5) <= \<const0>\;
  LMB_Data_Addr_12(6) <= \<const0>\;
  LMB_Data_Addr_12(7) <= \<const0>\;
  LMB_Data_Addr_12(8) <= \<const0>\;
  LMB_Data_Addr_12(9) <= \<const0>\;
  LMB_Data_Addr_12(10) <= \<const0>\;
  LMB_Data_Addr_12(11) <= \<const0>\;
  LMB_Data_Addr_12(12) <= \<const0>\;
  LMB_Data_Addr_12(13) <= \<const0>\;
  LMB_Data_Addr_12(14) <= \<const0>\;
  LMB_Data_Addr_12(15) <= \<const0>\;
  LMB_Data_Addr_12(16) <= \<const0>\;
  LMB_Data_Addr_12(17) <= \<const0>\;
  LMB_Data_Addr_12(18) <= \<const0>\;
  LMB_Data_Addr_12(19) <= \<const0>\;
  LMB_Data_Addr_12(20) <= \<const0>\;
  LMB_Data_Addr_12(21) <= \<const0>\;
  LMB_Data_Addr_12(22) <= \<const0>\;
  LMB_Data_Addr_12(23) <= \<const0>\;
  LMB_Data_Addr_12(24) <= \<const0>\;
  LMB_Data_Addr_12(25) <= \<const0>\;
  LMB_Data_Addr_12(26) <= \<const0>\;
  LMB_Data_Addr_12(27) <= \<const0>\;
  LMB_Data_Addr_12(28) <= \<const0>\;
  LMB_Data_Addr_12(29) <= \<const0>\;
  LMB_Data_Addr_12(30) <= \<const0>\;
  LMB_Data_Addr_12(31) <= \<const0>\;
  LMB_Data_Addr_13(0) <= \<const0>\;
  LMB_Data_Addr_13(1) <= \<const0>\;
  LMB_Data_Addr_13(2) <= \<const0>\;
  LMB_Data_Addr_13(3) <= \<const0>\;
  LMB_Data_Addr_13(4) <= \<const0>\;
  LMB_Data_Addr_13(5) <= \<const0>\;
  LMB_Data_Addr_13(6) <= \<const0>\;
  LMB_Data_Addr_13(7) <= \<const0>\;
  LMB_Data_Addr_13(8) <= \<const0>\;
  LMB_Data_Addr_13(9) <= \<const0>\;
  LMB_Data_Addr_13(10) <= \<const0>\;
  LMB_Data_Addr_13(11) <= \<const0>\;
  LMB_Data_Addr_13(12) <= \<const0>\;
  LMB_Data_Addr_13(13) <= \<const0>\;
  LMB_Data_Addr_13(14) <= \<const0>\;
  LMB_Data_Addr_13(15) <= \<const0>\;
  LMB_Data_Addr_13(16) <= \<const0>\;
  LMB_Data_Addr_13(17) <= \<const0>\;
  LMB_Data_Addr_13(18) <= \<const0>\;
  LMB_Data_Addr_13(19) <= \<const0>\;
  LMB_Data_Addr_13(20) <= \<const0>\;
  LMB_Data_Addr_13(21) <= \<const0>\;
  LMB_Data_Addr_13(22) <= \<const0>\;
  LMB_Data_Addr_13(23) <= \<const0>\;
  LMB_Data_Addr_13(24) <= \<const0>\;
  LMB_Data_Addr_13(25) <= \<const0>\;
  LMB_Data_Addr_13(26) <= \<const0>\;
  LMB_Data_Addr_13(27) <= \<const0>\;
  LMB_Data_Addr_13(28) <= \<const0>\;
  LMB_Data_Addr_13(29) <= \<const0>\;
  LMB_Data_Addr_13(30) <= \<const0>\;
  LMB_Data_Addr_13(31) <= \<const0>\;
  LMB_Data_Addr_14(0) <= \<const0>\;
  LMB_Data_Addr_14(1) <= \<const0>\;
  LMB_Data_Addr_14(2) <= \<const0>\;
  LMB_Data_Addr_14(3) <= \<const0>\;
  LMB_Data_Addr_14(4) <= \<const0>\;
  LMB_Data_Addr_14(5) <= \<const0>\;
  LMB_Data_Addr_14(6) <= \<const0>\;
  LMB_Data_Addr_14(7) <= \<const0>\;
  LMB_Data_Addr_14(8) <= \<const0>\;
  LMB_Data_Addr_14(9) <= \<const0>\;
  LMB_Data_Addr_14(10) <= \<const0>\;
  LMB_Data_Addr_14(11) <= \<const0>\;
  LMB_Data_Addr_14(12) <= \<const0>\;
  LMB_Data_Addr_14(13) <= \<const0>\;
  LMB_Data_Addr_14(14) <= \<const0>\;
  LMB_Data_Addr_14(15) <= \<const0>\;
  LMB_Data_Addr_14(16) <= \<const0>\;
  LMB_Data_Addr_14(17) <= \<const0>\;
  LMB_Data_Addr_14(18) <= \<const0>\;
  LMB_Data_Addr_14(19) <= \<const0>\;
  LMB_Data_Addr_14(20) <= \<const0>\;
  LMB_Data_Addr_14(21) <= \<const0>\;
  LMB_Data_Addr_14(22) <= \<const0>\;
  LMB_Data_Addr_14(23) <= \<const0>\;
  LMB_Data_Addr_14(24) <= \<const0>\;
  LMB_Data_Addr_14(25) <= \<const0>\;
  LMB_Data_Addr_14(26) <= \<const0>\;
  LMB_Data_Addr_14(27) <= \<const0>\;
  LMB_Data_Addr_14(28) <= \<const0>\;
  LMB_Data_Addr_14(29) <= \<const0>\;
  LMB_Data_Addr_14(30) <= \<const0>\;
  LMB_Data_Addr_14(31) <= \<const0>\;
  LMB_Data_Addr_15(0) <= \<const0>\;
  LMB_Data_Addr_15(1) <= \<const0>\;
  LMB_Data_Addr_15(2) <= \<const0>\;
  LMB_Data_Addr_15(3) <= \<const0>\;
  LMB_Data_Addr_15(4) <= \<const0>\;
  LMB_Data_Addr_15(5) <= \<const0>\;
  LMB_Data_Addr_15(6) <= \<const0>\;
  LMB_Data_Addr_15(7) <= \<const0>\;
  LMB_Data_Addr_15(8) <= \<const0>\;
  LMB_Data_Addr_15(9) <= \<const0>\;
  LMB_Data_Addr_15(10) <= \<const0>\;
  LMB_Data_Addr_15(11) <= \<const0>\;
  LMB_Data_Addr_15(12) <= \<const0>\;
  LMB_Data_Addr_15(13) <= \<const0>\;
  LMB_Data_Addr_15(14) <= \<const0>\;
  LMB_Data_Addr_15(15) <= \<const0>\;
  LMB_Data_Addr_15(16) <= \<const0>\;
  LMB_Data_Addr_15(17) <= \<const0>\;
  LMB_Data_Addr_15(18) <= \<const0>\;
  LMB_Data_Addr_15(19) <= \<const0>\;
  LMB_Data_Addr_15(20) <= \<const0>\;
  LMB_Data_Addr_15(21) <= \<const0>\;
  LMB_Data_Addr_15(22) <= \<const0>\;
  LMB_Data_Addr_15(23) <= \<const0>\;
  LMB_Data_Addr_15(24) <= \<const0>\;
  LMB_Data_Addr_15(25) <= \<const0>\;
  LMB_Data_Addr_15(26) <= \<const0>\;
  LMB_Data_Addr_15(27) <= \<const0>\;
  LMB_Data_Addr_15(28) <= \<const0>\;
  LMB_Data_Addr_15(29) <= \<const0>\;
  LMB_Data_Addr_15(30) <= \<const0>\;
  LMB_Data_Addr_15(31) <= \<const0>\;
  LMB_Data_Addr_16(0) <= \<const0>\;
  LMB_Data_Addr_16(1) <= \<const0>\;
  LMB_Data_Addr_16(2) <= \<const0>\;
  LMB_Data_Addr_16(3) <= \<const0>\;
  LMB_Data_Addr_16(4) <= \<const0>\;
  LMB_Data_Addr_16(5) <= \<const0>\;
  LMB_Data_Addr_16(6) <= \<const0>\;
  LMB_Data_Addr_16(7) <= \<const0>\;
  LMB_Data_Addr_16(8) <= \<const0>\;
  LMB_Data_Addr_16(9) <= \<const0>\;
  LMB_Data_Addr_16(10) <= \<const0>\;
  LMB_Data_Addr_16(11) <= \<const0>\;
  LMB_Data_Addr_16(12) <= \<const0>\;
  LMB_Data_Addr_16(13) <= \<const0>\;
  LMB_Data_Addr_16(14) <= \<const0>\;
  LMB_Data_Addr_16(15) <= \<const0>\;
  LMB_Data_Addr_16(16) <= \<const0>\;
  LMB_Data_Addr_16(17) <= \<const0>\;
  LMB_Data_Addr_16(18) <= \<const0>\;
  LMB_Data_Addr_16(19) <= \<const0>\;
  LMB_Data_Addr_16(20) <= \<const0>\;
  LMB_Data_Addr_16(21) <= \<const0>\;
  LMB_Data_Addr_16(22) <= \<const0>\;
  LMB_Data_Addr_16(23) <= \<const0>\;
  LMB_Data_Addr_16(24) <= \<const0>\;
  LMB_Data_Addr_16(25) <= \<const0>\;
  LMB_Data_Addr_16(26) <= \<const0>\;
  LMB_Data_Addr_16(27) <= \<const0>\;
  LMB_Data_Addr_16(28) <= \<const0>\;
  LMB_Data_Addr_16(29) <= \<const0>\;
  LMB_Data_Addr_16(30) <= \<const0>\;
  LMB_Data_Addr_16(31) <= \<const0>\;
  LMB_Data_Addr_17(0) <= \<const0>\;
  LMB_Data_Addr_17(1) <= \<const0>\;
  LMB_Data_Addr_17(2) <= \<const0>\;
  LMB_Data_Addr_17(3) <= \<const0>\;
  LMB_Data_Addr_17(4) <= \<const0>\;
  LMB_Data_Addr_17(5) <= \<const0>\;
  LMB_Data_Addr_17(6) <= \<const0>\;
  LMB_Data_Addr_17(7) <= \<const0>\;
  LMB_Data_Addr_17(8) <= \<const0>\;
  LMB_Data_Addr_17(9) <= \<const0>\;
  LMB_Data_Addr_17(10) <= \<const0>\;
  LMB_Data_Addr_17(11) <= \<const0>\;
  LMB_Data_Addr_17(12) <= \<const0>\;
  LMB_Data_Addr_17(13) <= \<const0>\;
  LMB_Data_Addr_17(14) <= \<const0>\;
  LMB_Data_Addr_17(15) <= \<const0>\;
  LMB_Data_Addr_17(16) <= \<const0>\;
  LMB_Data_Addr_17(17) <= \<const0>\;
  LMB_Data_Addr_17(18) <= \<const0>\;
  LMB_Data_Addr_17(19) <= \<const0>\;
  LMB_Data_Addr_17(20) <= \<const0>\;
  LMB_Data_Addr_17(21) <= \<const0>\;
  LMB_Data_Addr_17(22) <= \<const0>\;
  LMB_Data_Addr_17(23) <= \<const0>\;
  LMB_Data_Addr_17(24) <= \<const0>\;
  LMB_Data_Addr_17(25) <= \<const0>\;
  LMB_Data_Addr_17(26) <= \<const0>\;
  LMB_Data_Addr_17(27) <= \<const0>\;
  LMB_Data_Addr_17(28) <= \<const0>\;
  LMB_Data_Addr_17(29) <= \<const0>\;
  LMB_Data_Addr_17(30) <= \<const0>\;
  LMB_Data_Addr_17(31) <= \<const0>\;
  LMB_Data_Addr_18(0) <= \<const0>\;
  LMB_Data_Addr_18(1) <= \<const0>\;
  LMB_Data_Addr_18(2) <= \<const0>\;
  LMB_Data_Addr_18(3) <= \<const0>\;
  LMB_Data_Addr_18(4) <= \<const0>\;
  LMB_Data_Addr_18(5) <= \<const0>\;
  LMB_Data_Addr_18(6) <= \<const0>\;
  LMB_Data_Addr_18(7) <= \<const0>\;
  LMB_Data_Addr_18(8) <= \<const0>\;
  LMB_Data_Addr_18(9) <= \<const0>\;
  LMB_Data_Addr_18(10) <= \<const0>\;
  LMB_Data_Addr_18(11) <= \<const0>\;
  LMB_Data_Addr_18(12) <= \<const0>\;
  LMB_Data_Addr_18(13) <= \<const0>\;
  LMB_Data_Addr_18(14) <= \<const0>\;
  LMB_Data_Addr_18(15) <= \<const0>\;
  LMB_Data_Addr_18(16) <= \<const0>\;
  LMB_Data_Addr_18(17) <= \<const0>\;
  LMB_Data_Addr_18(18) <= \<const0>\;
  LMB_Data_Addr_18(19) <= \<const0>\;
  LMB_Data_Addr_18(20) <= \<const0>\;
  LMB_Data_Addr_18(21) <= \<const0>\;
  LMB_Data_Addr_18(22) <= \<const0>\;
  LMB_Data_Addr_18(23) <= \<const0>\;
  LMB_Data_Addr_18(24) <= \<const0>\;
  LMB_Data_Addr_18(25) <= \<const0>\;
  LMB_Data_Addr_18(26) <= \<const0>\;
  LMB_Data_Addr_18(27) <= \<const0>\;
  LMB_Data_Addr_18(28) <= \<const0>\;
  LMB_Data_Addr_18(29) <= \<const0>\;
  LMB_Data_Addr_18(30) <= \<const0>\;
  LMB_Data_Addr_18(31) <= \<const0>\;
  LMB_Data_Addr_19(0) <= \<const0>\;
  LMB_Data_Addr_19(1) <= \<const0>\;
  LMB_Data_Addr_19(2) <= \<const0>\;
  LMB_Data_Addr_19(3) <= \<const0>\;
  LMB_Data_Addr_19(4) <= \<const0>\;
  LMB_Data_Addr_19(5) <= \<const0>\;
  LMB_Data_Addr_19(6) <= \<const0>\;
  LMB_Data_Addr_19(7) <= \<const0>\;
  LMB_Data_Addr_19(8) <= \<const0>\;
  LMB_Data_Addr_19(9) <= \<const0>\;
  LMB_Data_Addr_19(10) <= \<const0>\;
  LMB_Data_Addr_19(11) <= \<const0>\;
  LMB_Data_Addr_19(12) <= \<const0>\;
  LMB_Data_Addr_19(13) <= \<const0>\;
  LMB_Data_Addr_19(14) <= \<const0>\;
  LMB_Data_Addr_19(15) <= \<const0>\;
  LMB_Data_Addr_19(16) <= \<const0>\;
  LMB_Data_Addr_19(17) <= \<const0>\;
  LMB_Data_Addr_19(18) <= \<const0>\;
  LMB_Data_Addr_19(19) <= \<const0>\;
  LMB_Data_Addr_19(20) <= \<const0>\;
  LMB_Data_Addr_19(21) <= \<const0>\;
  LMB_Data_Addr_19(22) <= \<const0>\;
  LMB_Data_Addr_19(23) <= \<const0>\;
  LMB_Data_Addr_19(24) <= \<const0>\;
  LMB_Data_Addr_19(25) <= \<const0>\;
  LMB_Data_Addr_19(26) <= \<const0>\;
  LMB_Data_Addr_19(27) <= \<const0>\;
  LMB_Data_Addr_19(28) <= \<const0>\;
  LMB_Data_Addr_19(29) <= \<const0>\;
  LMB_Data_Addr_19(30) <= \<const0>\;
  LMB_Data_Addr_19(31) <= \<const0>\;
  LMB_Data_Addr_2(0) <= \<const0>\;
  LMB_Data_Addr_2(1) <= \<const0>\;
  LMB_Data_Addr_2(2) <= \<const0>\;
  LMB_Data_Addr_2(3) <= \<const0>\;
  LMB_Data_Addr_2(4) <= \<const0>\;
  LMB_Data_Addr_2(5) <= \<const0>\;
  LMB_Data_Addr_2(6) <= \<const0>\;
  LMB_Data_Addr_2(7) <= \<const0>\;
  LMB_Data_Addr_2(8) <= \<const0>\;
  LMB_Data_Addr_2(9) <= \<const0>\;
  LMB_Data_Addr_2(10) <= \<const0>\;
  LMB_Data_Addr_2(11) <= \<const0>\;
  LMB_Data_Addr_2(12) <= \<const0>\;
  LMB_Data_Addr_2(13) <= \<const0>\;
  LMB_Data_Addr_2(14) <= \<const0>\;
  LMB_Data_Addr_2(15) <= \<const0>\;
  LMB_Data_Addr_2(16) <= \<const0>\;
  LMB_Data_Addr_2(17) <= \<const0>\;
  LMB_Data_Addr_2(18) <= \<const0>\;
  LMB_Data_Addr_2(19) <= \<const0>\;
  LMB_Data_Addr_2(20) <= \<const0>\;
  LMB_Data_Addr_2(21) <= \<const0>\;
  LMB_Data_Addr_2(22) <= \<const0>\;
  LMB_Data_Addr_2(23) <= \<const0>\;
  LMB_Data_Addr_2(24) <= \<const0>\;
  LMB_Data_Addr_2(25) <= \<const0>\;
  LMB_Data_Addr_2(26) <= \<const0>\;
  LMB_Data_Addr_2(27) <= \<const0>\;
  LMB_Data_Addr_2(28) <= \<const0>\;
  LMB_Data_Addr_2(29) <= \<const0>\;
  LMB_Data_Addr_2(30) <= \<const0>\;
  LMB_Data_Addr_2(31) <= \<const0>\;
  LMB_Data_Addr_20(0) <= \<const0>\;
  LMB_Data_Addr_20(1) <= \<const0>\;
  LMB_Data_Addr_20(2) <= \<const0>\;
  LMB_Data_Addr_20(3) <= \<const0>\;
  LMB_Data_Addr_20(4) <= \<const0>\;
  LMB_Data_Addr_20(5) <= \<const0>\;
  LMB_Data_Addr_20(6) <= \<const0>\;
  LMB_Data_Addr_20(7) <= \<const0>\;
  LMB_Data_Addr_20(8) <= \<const0>\;
  LMB_Data_Addr_20(9) <= \<const0>\;
  LMB_Data_Addr_20(10) <= \<const0>\;
  LMB_Data_Addr_20(11) <= \<const0>\;
  LMB_Data_Addr_20(12) <= \<const0>\;
  LMB_Data_Addr_20(13) <= \<const0>\;
  LMB_Data_Addr_20(14) <= \<const0>\;
  LMB_Data_Addr_20(15) <= \<const0>\;
  LMB_Data_Addr_20(16) <= \<const0>\;
  LMB_Data_Addr_20(17) <= \<const0>\;
  LMB_Data_Addr_20(18) <= \<const0>\;
  LMB_Data_Addr_20(19) <= \<const0>\;
  LMB_Data_Addr_20(20) <= \<const0>\;
  LMB_Data_Addr_20(21) <= \<const0>\;
  LMB_Data_Addr_20(22) <= \<const0>\;
  LMB_Data_Addr_20(23) <= \<const0>\;
  LMB_Data_Addr_20(24) <= \<const0>\;
  LMB_Data_Addr_20(25) <= \<const0>\;
  LMB_Data_Addr_20(26) <= \<const0>\;
  LMB_Data_Addr_20(27) <= \<const0>\;
  LMB_Data_Addr_20(28) <= \<const0>\;
  LMB_Data_Addr_20(29) <= \<const0>\;
  LMB_Data_Addr_20(30) <= \<const0>\;
  LMB_Data_Addr_20(31) <= \<const0>\;
  LMB_Data_Addr_21(0) <= \<const0>\;
  LMB_Data_Addr_21(1) <= \<const0>\;
  LMB_Data_Addr_21(2) <= \<const0>\;
  LMB_Data_Addr_21(3) <= \<const0>\;
  LMB_Data_Addr_21(4) <= \<const0>\;
  LMB_Data_Addr_21(5) <= \<const0>\;
  LMB_Data_Addr_21(6) <= \<const0>\;
  LMB_Data_Addr_21(7) <= \<const0>\;
  LMB_Data_Addr_21(8) <= \<const0>\;
  LMB_Data_Addr_21(9) <= \<const0>\;
  LMB_Data_Addr_21(10) <= \<const0>\;
  LMB_Data_Addr_21(11) <= \<const0>\;
  LMB_Data_Addr_21(12) <= \<const0>\;
  LMB_Data_Addr_21(13) <= \<const0>\;
  LMB_Data_Addr_21(14) <= \<const0>\;
  LMB_Data_Addr_21(15) <= \<const0>\;
  LMB_Data_Addr_21(16) <= \<const0>\;
  LMB_Data_Addr_21(17) <= \<const0>\;
  LMB_Data_Addr_21(18) <= \<const0>\;
  LMB_Data_Addr_21(19) <= \<const0>\;
  LMB_Data_Addr_21(20) <= \<const0>\;
  LMB_Data_Addr_21(21) <= \<const0>\;
  LMB_Data_Addr_21(22) <= \<const0>\;
  LMB_Data_Addr_21(23) <= \<const0>\;
  LMB_Data_Addr_21(24) <= \<const0>\;
  LMB_Data_Addr_21(25) <= \<const0>\;
  LMB_Data_Addr_21(26) <= \<const0>\;
  LMB_Data_Addr_21(27) <= \<const0>\;
  LMB_Data_Addr_21(28) <= \<const0>\;
  LMB_Data_Addr_21(29) <= \<const0>\;
  LMB_Data_Addr_21(30) <= \<const0>\;
  LMB_Data_Addr_21(31) <= \<const0>\;
  LMB_Data_Addr_22(0) <= \<const0>\;
  LMB_Data_Addr_22(1) <= \<const0>\;
  LMB_Data_Addr_22(2) <= \<const0>\;
  LMB_Data_Addr_22(3) <= \<const0>\;
  LMB_Data_Addr_22(4) <= \<const0>\;
  LMB_Data_Addr_22(5) <= \<const0>\;
  LMB_Data_Addr_22(6) <= \<const0>\;
  LMB_Data_Addr_22(7) <= \<const0>\;
  LMB_Data_Addr_22(8) <= \<const0>\;
  LMB_Data_Addr_22(9) <= \<const0>\;
  LMB_Data_Addr_22(10) <= \<const0>\;
  LMB_Data_Addr_22(11) <= \<const0>\;
  LMB_Data_Addr_22(12) <= \<const0>\;
  LMB_Data_Addr_22(13) <= \<const0>\;
  LMB_Data_Addr_22(14) <= \<const0>\;
  LMB_Data_Addr_22(15) <= \<const0>\;
  LMB_Data_Addr_22(16) <= \<const0>\;
  LMB_Data_Addr_22(17) <= \<const0>\;
  LMB_Data_Addr_22(18) <= \<const0>\;
  LMB_Data_Addr_22(19) <= \<const0>\;
  LMB_Data_Addr_22(20) <= \<const0>\;
  LMB_Data_Addr_22(21) <= \<const0>\;
  LMB_Data_Addr_22(22) <= \<const0>\;
  LMB_Data_Addr_22(23) <= \<const0>\;
  LMB_Data_Addr_22(24) <= \<const0>\;
  LMB_Data_Addr_22(25) <= \<const0>\;
  LMB_Data_Addr_22(26) <= \<const0>\;
  LMB_Data_Addr_22(27) <= \<const0>\;
  LMB_Data_Addr_22(28) <= \<const0>\;
  LMB_Data_Addr_22(29) <= \<const0>\;
  LMB_Data_Addr_22(30) <= \<const0>\;
  LMB_Data_Addr_22(31) <= \<const0>\;
  LMB_Data_Addr_23(0) <= \<const0>\;
  LMB_Data_Addr_23(1) <= \<const0>\;
  LMB_Data_Addr_23(2) <= \<const0>\;
  LMB_Data_Addr_23(3) <= \<const0>\;
  LMB_Data_Addr_23(4) <= \<const0>\;
  LMB_Data_Addr_23(5) <= \<const0>\;
  LMB_Data_Addr_23(6) <= \<const0>\;
  LMB_Data_Addr_23(7) <= \<const0>\;
  LMB_Data_Addr_23(8) <= \<const0>\;
  LMB_Data_Addr_23(9) <= \<const0>\;
  LMB_Data_Addr_23(10) <= \<const0>\;
  LMB_Data_Addr_23(11) <= \<const0>\;
  LMB_Data_Addr_23(12) <= \<const0>\;
  LMB_Data_Addr_23(13) <= \<const0>\;
  LMB_Data_Addr_23(14) <= \<const0>\;
  LMB_Data_Addr_23(15) <= \<const0>\;
  LMB_Data_Addr_23(16) <= \<const0>\;
  LMB_Data_Addr_23(17) <= \<const0>\;
  LMB_Data_Addr_23(18) <= \<const0>\;
  LMB_Data_Addr_23(19) <= \<const0>\;
  LMB_Data_Addr_23(20) <= \<const0>\;
  LMB_Data_Addr_23(21) <= \<const0>\;
  LMB_Data_Addr_23(22) <= \<const0>\;
  LMB_Data_Addr_23(23) <= \<const0>\;
  LMB_Data_Addr_23(24) <= \<const0>\;
  LMB_Data_Addr_23(25) <= \<const0>\;
  LMB_Data_Addr_23(26) <= \<const0>\;
  LMB_Data_Addr_23(27) <= \<const0>\;
  LMB_Data_Addr_23(28) <= \<const0>\;
  LMB_Data_Addr_23(29) <= \<const0>\;
  LMB_Data_Addr_23(30) <= \<const0>\;
  LMB_Data_Addr_23(31) <= \<const0>\;
  LMB_Data_Addr_24(0) <= \<const0>\;
  LMB_Data_Addr_24(1) <= \<const0>\;
  LMB_Data_Addr_24(2) <= \<const0>\;
  LMB_Data_Addr_24(3) <= \<const0>\;
  LMB_Data_Addr_24(4) <= \<const0>\;
  LMB_Data_Addr_24(5) <= \<const0>\;
  LMB_Data_Addr_24(6) <= \<const0>\;
  LMB_Data_Addr_24(7) <= \<const0>\;
  LMB_Data_Addr_24(8) <= \<const0>\;
  LMB_Data_Addr_24(9) <= \<const0>\;
  LMB_Data_Addr_24(10) <= \<const0>\;
  LMB_Data_Addr_24(11) <= \<const0>\;
  LMB_Data_Addr_24(12) <= \<const0>\;
  LMB_Data_Addr_24(13) <= \<const0>\;
  LMB_Data_Addr_24(14) <= \<const0>\;
  LMB_Data_Addr_24(15) <= \<const0>\;
  LMB_Data_Addr_24(16) <= \<const0>\;
  LMB_Data_Addr_24(17) <= \<const0>\;
  LMB_Data_Addr_24(18) <= \<const0>\;
  LMB_Data_Addr_24(19) <= \<const0>\;
  LMB_Data_Addr_24(20) <= \<const0>\;
  LMB_Data_Addr_24(21) <= \<const0>\;
  LMB_Data_Addr_24(22) <= \<const0>\;
  LMB_Data_Addr_24(23) <= \<const0>\;
  LMB_Data_Addr_24(24) <= \<const0>\;
  LMB_Data_Addr_24(25) <= \<const0>\;
  LMB_Data_Addr_24(26) <= \<const0>\;
  LMB_Data_Addr_24(27) <= \<const0>\;
  LMB_Data_Addr_24(28) <= \<const0>\;
  LMB_Data_Addr_24(29) <= \<const0>\;
  LMB_Data_Addr_24(30) <= \<const0>\;
  LMB_Data_Addr_24(31) <= \<const0>\;
  LMB_Data_Addr_25(0) <= \<const0>\;
  LMB_Data_Addr_25(1) <= \<const0>\;
  LMB_Data_Addr_25(2) <= \<const0>\;
  LMB_Data_Addr_25(3) <= \<const0>\;
  LMB_Data_Addr_25(4) <= \<const0>\;
  LMB_Data_Addr_25(5) <= \<const0>\;
  LMB_Data_Addr_25(6) <= \<const0>\;
  LMB_Data_Addr_25(7) <= \<const0>\;
  LMB_Data_Addr_25(8) <= \<const0>\;
  LMB_Data_Addr_25(9) <= \<const0>\;
  LMB_Data_Addr_25(10) <= \<const0>\;
  LMB_Data_Addr_25(11) <= \<const0>\;
  LMB_Data_Addr_25(12) <= \<const0>\;
  LMB_Data_Addr_25(13) <= \<const0>\;
  LMB_Data_Addr_25(14) <= \<const0>\;
  LMB_Data_Addr_25(15) <= \<const0>\;
  LMB_Data_Addr_25(16) <= \<const0>\;
  LMB_Data_Addr_25(17) <= \<const0>\;
  LMB_Data_Addr_25(18) <= \<const0>\;
  LMB_Data_Addr_25(19) <= \<const0>\;
  LMB_Data_Addr_25(20) <= \<const0>\;
  LMB_Data_Addr_25(21) <= \<const0>\;
  LMB_Data_Addr_25(22) <= \<const0>\;
  LMB_Data_Addr_25(23) <= \<const0>\;
  LMB_Data_Addr_25(24) <= \<const0>\;
  LMB_Data_Addr_25(25) <= \<const0>\;
  LMB_Data_Addr_25(26) <= \<const0>\;
  LMB_Data_Addr_25(27) <= \<const0>\;
  LMB_Data_Addr_25(28) <= \<const0>\;
  LMB_Data_Addr_25(29) <= \<const0>\;
  LMB_Data_Addr_25(30) <= \<const0>\;
  LMB_Data_Addr_25(31) <= \<const0>\;
  LMB_Data_Addr_26(0) <= \<const0>\;
  LMB_Data_Addr_26(1) <= \<const0>\;
  LMB_Data_Addr_26(2) <= \<const0>\;
  LMB_Data_Addr_26(3) <= \<const0>\;
  LMB_Data_Addr_26(4) <= \<const0>\;
  LMB_Data_Addr_26(5) <= \<const0>\;
  LMB_Data_Addr_26(6) <= \<const0>\;
  LMB_Data_Addr_26(7) <= \<const0>\;
  LMB_Data_Addr_26(8) <= \<const0>\;
  LMB_Data_Addr_26(9) <= \<const0>\;
  LMB_Data_Addr_26(10) <= \<const0>\;
  LMB_Data_Addr_26(11) <= \<const0>\;
  LMB_Data_Addr_26(12) <= \<const0>\;
  LMB_Data_Addr_26(13) <= \<const0>\;
  LMB_Data_Addr_26(14) <= \<const0>\;
  LMB_Data_Addr_26(15) <= \<const0>\;
  LMB_Data_Addr_26(16) <= \<const0>\;
  LMB_Data_Addr_26(17) <= \<const0>\;
  LMB_Data_Addr_26(18) <= \<const0>\;
  LMB_Data_Addr_26(19) <= \<const0>\;
  LMB_Data_Addr_26(20) <= \<const0>\;
  LMB_Data_Addr_26(21) <= \<const0>\;
  LMB_Data_Addr_26(22) <= \<const0>\;
  LMB_Data_Addr_26(23) <= \<const0>\;
  LMB_Data_Addr_26(24) <= \<const0>\;
  LMB_Data_Addr_26(25) <= \<const0>\;
  LMB_Data_Addr_26(26) <= \<const0>\;
  LMB_Data_Addr_26(27) <= \<const0>\;
  LMB_Data_Addr_26(28) <= \<const0>\;
  LMB_Data_Addr_26(29) <= \<const0>\;
  LMB_Data_Addr_26(30) <= \<const0>\;
  LMB_Data_Addr_26(31) <= \<const0>\;
  LMB_Data_Addr_27(0) <= \<const0>\;
  LMB_Data_Addr_27(1) <= \<const0>\;
  LMB_Data_Addr_27(2) <= \<const0>\;
  LMB_Data_Addr_27(3) <= \<const0>\;
  LMB_Data_Addr_27(4) <= \<const0>\;
  LMB_Data_Addr_27(5) <= \<const0>\;
  LMB_Data_Addr_27(6) <= \<const0>\;
  LMB_Data_Addr_27(7) <= \<const0>\;
  LMB_Data_Addr_27(8) <= \<const0>\;
  LMB_Data_Addr_27(9) <= \<const0>\;
  LMB_Data_Addr_27(10) <= \<const0>\;
  LMB_Data_Addr_27(11) <= \<const0>\;
  LMB_Data_Addr_27(12) <= \<const0>\;
  LMB_Data_Addr_27(13) <= \<const0>\;
  LMB_Data_Addr_27(14) <= \<const0>\;
  LMB_Data_Addr_27(15) <= \<const0>\;
  LMB_Data_Addr_27(16) <= \<const0>\;
  LMB_Data_Addr_27(17) <= \<const0>\;
  LMB_Data_Addr_27(18) <= \<const0>\;
  LMB_Data_Addr_27(19) <= \<const0>\;
  LMB_Data_Addr_27(20) <= \<const0>\;
  LMB_Data_Addr_27(21) <= \<const0>\;
  LMB_Data_Addr_27(22) <= \<const0>\;
  LMB_Data_Addr_27(23) <= \<const0>\;
  LMB_Data_Addr_27(24) <= \<const0>\;
  LMB_Data_Addr_27(25) <= \<const0>\;
  LMB_Data_Addr_27(26) <= \<const0>\;
  LMB_Data_Addr_27(27) <= \<const0>\;
  LMB_Data_Addr_27(28) <= \<const0>\;
  LMB_Data_Addr_27(29) <= \<const0>\;
  LMB_Data_Addr_27(30) <= \<const0>\;
  LMB_Data_Addr_27(31) <= \<const0>\;
  LMB_Data_Addr_28(0) <= \<const0>\;
  LMB_Data_Addr_28(1) <= \<const0>\;
  LMB_Data_Addr_28(2) <= \<const0>\;
  LMB_Data_Addr_28(3) <= \<const0>\;
  LMB_Data_Addr_28(4) <= \<const0>\;
  LMB_Data_Addr_28(5) <= \<const0>\;
  LMB_Data_Addr_28(6) <= \<const0>\;
  LMB_Data_Addr_28(7) <= \<const0>\;
  LMB_Data_Addr_28(8) <= \<const0>\;
  LMB_Data_Addr_28(9) <= \<const0>\;
  LMB_Data_Addr_28(10) <= \<const0>\;
  LMB_Data_Addr_28(11) <= \<const0>\;
  LMB_Data_Addr_28(12) <= \<const0>\;
  LMB_Data_Addr_28(13) <= \<const0>\;
  LMB_Data_Addr_28(14) <= \<const0>\;
  LMB_Data_Addr_28(15) <= \<const0>\;
  LMB_Data_Addr_28(16) <= \<const0>\;
  LMB_Data_Addr_28(17) <= \<const0>\;
  LMB_Data_Addr_28(18) <= \<const0>\;
  LMB_Data_Addr_28(19) <= \<const0>\;
  LMB_Data_Addr_28(20) <= \<const0>\;
  LMB_Data_Addr_28(21) <= \<const0>\;
  LMB_Data_Addr_28(22) <= \<const0>\;
  LMB_Data_Addr_28(23) <= \<const0>\;
  LMB_Data_Addr_28(24) <= \<const0>\;
  LMB_Data_Addr_28(25) <= \<const0>\;
  LMB_Data_Addr_28(26) <= \<const0>\;
  LMB_Data_Addr_28(27) <= \<const0>\;
  LMB_Data_Addr_28(28) <= \<const0>\;
  LMB_Data_Addr_28(29) <= \<const0>\;
  LMB_Data_Addr_28(30) <= \<const0>\;
  LMB_Data_Addr_28(31) <= \<const0>\;
  LMB_Data_Addr_29(0) <= \<const0>\;
  LMB_Data_Addr_29(1) <= \<const0>\;
  LMB_Data_Addr_29(2) <= \<const0>\;
  LMB_Data_Addr_29(3) <= \<const0>\;
  LMB_Data_Addr_29(4) <= \<const0>\;
  LMB_Data_Addr_29(5) <= \<const0>\;
  LMB_Data_Addr_29(6) <= \<const0>\;
  LMB_Data_Addr_29(7) <= \<const0>\;
  LMB_Data_Addr_29(8) <= \<const0>\;
  LMB_Data_Addr_29(9) <= \<const0>\;
  LMB_Data_Addr_29(10) <= \<const0>\;
  LMB_Data_Addr_29(11) <= \<const0>\;
  LMB_Data_Addr_29(12) <= \<const0>\;
  LMB_Data_Addr_29(13) <= \<const0>\;
  LMB_Data_Addr_29(14) <= \<const0>\;
  LMB_Data_Addr_29(15) <= \<const0>\;
  LMB_Data_Addr_29(16) <= \<const0>\;
  LMB_Data_Addr_29(17) <= \<const0>\;
  LMB_Data_Addr_29(18) <= \<const0>\;
  LMB_Data_Addr_29(19) <= \<const0>\;
  LMB_Data_Addr_29(20) <= \<const0>\;
  LMB_Data_Addr_29(21) <= \<const0>\;
  LMB_Data_Addr_29(22) <= \<const0>\;
  LMB_Data_Addr_29(23) <= \<const0>\;
  LMB_Data_Addr_29(24) <= \<const0>\;
  LMB_Data_Addr_29(25) <= \<const0>\;
  LMB_Data_Addr_29(26) <= \<const0>\;
  LMB_Data_Addr_29(27) <= \<const0>\;
  LMB_Data_Addr_29(28) <= \<const0>\;
  LMB_Data_Addr_29(29) <= \<const0>\;
  LMB_Data_Addr_29(30) <= \<const0>\;
  LMB_Data_Addr_29(31) <= \<const0>\;
  LMB_Data_Addr_3(0) <= \<const0>\;
  LMB_Data_Addr_3(1) <= \<const0>\;
  LMB_Data_Addr_3(2) <= \<const0>\;
  LMB_Data_Addr_3(3) <= \<const0>\;
  LMB_Data_Addr_3(4) <= \<const0>\;
  LMB_Data_Addr_3(5) <= \<const0>\;
  LMB_Data_Addr_3(6) <= \<const0>\;
  LMB_Data_Addr_3(7) <= \<const0>\;
  LMB_Data_Addr_3(8) <= \<const0>\;
  LMB_Data_Addr_3(9) <= \<const0>\;
  LMB_Data_Addr_3(10) <= \<const0>\;
  LMB_Data_Addr_3(11) <= \<const0>\;
  LMB_Data_Addr_3(12) <= \<const0>\;
  LMB_Data_Addr_3(13) <= \<const0>\;
  LMB_Data_Addr_3(14) <= \<const0>\;
  LMB_Data_Addr_3(15) <= \<const0>\;
  LMB_Data_Addr_3(16) <= \<const0>\;
  LMB_Data_Addr_3(17) <= \<const0>\;
  LMB_Data_Addr_3(18) <= \<const0>\;
  LMB_Data_Addr_3(19) <= \<const0>\;
  LMB_Data_Addr_3(20) <= \<const0>\;
  LMB_Data_Addr_3(21) <= \<const0>\;
  LMB_Data_Addr_3(22) <= \<const0>\;
  LMB_Data_Addr_3(23) <= \<const0>\;
  LMB_Data_Addr_3(24) <= \<const0>\;
  LMB_Data_Addr_3(25) <= \<const0>\;
  LMB_Data_Addr_3(26) <= \<const0>\;
  LMB_Data_Addr_3(27) <= \<const0>\;
  LMB_Data_Addr_3(28) <= \<const0>\;
  LMB_Data_Addr_3(29) <= \<const0>\;
  LMB_Data_Addr_3(30) <= \<const0>\;
  LMB_Data_Addr_3(31) <= \<const0>\;
  LMB_Data_Addr_30(0) <= \<const0>\;
  LMB_Data_Addr_30(1) <= \<const0>\;
  LMB_Data_Addr_30(2) <= \<const0>\;
  LMB_Data_Addr_30(3) <= \<const0>\;
  LMB_Data_Addr_30(4) <= \<const0>\;
  LMB_Data_Addr_30(5) <= \<const0>\;
  LMB_Data_Addr_30(6) <= \<const0>\;
  LMB_Data_Addr_30(7) <= \<const0>\;
  LMB_Data_Addr_30(8) <= \<const0>\;
  LMB_Data_Addr_30(9) <= \<const0>\;
  LMB_Data_Addr_30(10) <= \<const0>\;
  LMB_Data_Addr_30(11) <= \<const0>\;
  LMB_Data_Addr_30(12) <= \<const0>\;
  LMB_Data_Addr_30(13) <= \<const0>\;
  LMB_Data_Addr_30(14) <= \<const0>\;
  LMB_Data_Addr_30(15) <= \<const0>\;
  LMB_Data_Addr_30(16) <= \<const0>\;
  LMB_Data_Addr_30(17) <= \<const0>\;
  LMB_Data_Addr_30(18) <= \<const0>\;
  LMB_Data_Addr_30(19) <= \<const0>\;
  LMB_Data_Addr_30(20) <= \<const0>\;
  LMB_Data_Addr_30(21) <= \<const0>\;
  LMB_Data_Addr_30(22) <= \<const0>\;
  LMB_Data_Addr_30(23) <= \<const0>\;
  LMB_Data_Addr_30(24) <= \<const0>\;
  LMB_Data_Addr_30(25) <= \<const0>\;
  LMB_Data_Addr_30(26) <= \<const0>\;
  LMB_Data_Addr_30(27) <= \<const0>\;
  LMB_Data_Addr_30(28) <= \<const0>\;
  LMB_Data_Addr_30(29) <= \<const0>\;
  LMB_Data_Addr_30(30) <= \<const0>\;
  LMB_Data_Addr_30(31) <= \<const0>\;
  LMB_Data_Addr_31(0) <= \<const0>\;
  LMB_Data_Addr_31(1) <= \<const0>\;
  LMB_Data_Addr_31(2) <= \<const0>\;
  LMB_Data_Addr_31(3) <= \<const0>\;
  LMB_Data_Addr_31(4) <= \<const0>\;
  LMB_Data_Addr_31(5) <= \<const0>\;
  LMB_Data_Addr_31(6) <= \<const0>\;
  LMB_Data_Addr_31(7) <= \<const0>\;
  LMB_Data_Addr_31(8) <= \<const0>\;
  LMB_Data_Addr_31(9) <= \<const0>\;
  LMB_Data_Addr_31(10) <= \<const0>\;
  LMB_Data_Addr_31(11) <= \<const0>\;
  LMB_Data_Addr_31(12) <= \<const0>\;
  LMB_Data_Addr_31(13) <= \<const0>\;
  LMB_Data_Addr_31(14) <= \<const0>\;
  LMB_Data_Addr_31(15) <= \<const0>\;
  LMB_Data_Addr_31(16) <= \<const0>\;
  LMB_Data_Addr_31(17) <= \<const0>\;
  LMB_Data_Addr_31(18) <= \<const0>\;
  LMB_Data_Addr_31(19) <= \<const0>\;
  LMB_Data_Addr_31(20) <= \<const0>\;
  LMB_Data_Addr_31(21) <= \<const0>\;
  LMB_Data_Addr_31(22) <= \<const0>\;
  LMB_Data_Addr_31(23) <= \<const0>\;
  LMB_Data_Addr_31(24) <= \<const0>\;
  LMB_Data_Addr_31(25) <= \<const0>\;
  LMB_Data_Addr_31(26) <= \<const0>\;
  LMB_Data_Addr_31(27) <= \<const0>\;
  LMB_Data_Addr_31(28) <= \<const0>\;
  LMB_Data_Addr_31(29) <= \<const0>\;
  LMB_Data_Addr_31(30) <= \<const0>\;
  LMB_Data_Addr_31(31) <= \<const0>\;
  LMB_Data_Addr_4(0) <= \<const0>\;
  LMB_Data_Addr_4(1) <= \<const0>\;
  LMB_Data_Addr_4(2) <= \<const0>\;
  LMB_Data_Addr_4(3) <= \<const0>\;
  LMB_Data_Addr_4(4) <= \<const0>\;
  LMB_Data_Addr_4(5) <= \<const0>\;
  LMB_Data_Addr_4(6) <= \<const0>\;
  LMB_Data_Addr_4(7) <= \<const0>\;
  LMB_Data_Addr_4(8) <= \<const0>\;
  LMB_Data_Addr_4(9) <= \<const0>\;
  LMB_Data_Addr_4(10) <= \<const0>\;
  LMB_Data_Addr_4(11) <= \<const0>\;
  LMB_Data_Addr_4(12) <= \<const0>\;
  LMB_Data_Addr_4(13) <= \<const0>\;
  LMB_Data_Addr_4(14) <= \<const0>\;
  LMB_Data_Addr_4(15) <= \<const0>\;
  LMB_Data_Addr_4(16) <= \<const0>\;
  LMB_Data_Addr_4(17) <= \<const0>\;
  LMB_Data_Addr_4(18) <= \<const0>\;
  LMB_Data_Addr_4(19) <= \<const0>\;
  LMB_Data_Addr_4(20) <= \<const0>\;
  LMB_Data_Addr_4(21) <= \<const0>\;
  LMB_Data_Addr_4(22) <= \<const0>\;
  LMB_Data_Addr_4(23) <= \<const0>\;
  LMB_Data_Addr_4(24) <= \<const0>\;
  LMB_Data_Addr_4(25) <= \<const0>\;
  LMB_Data_Addr_4(26) <= \<const0>\;
  LMB_Data_Addr_4(27) <= \<const0>\;
  LMB_Data_Addr_4(28) <= \<const0>\;
  LMB_Data_Addr_4(29) <= \<const0>\;
  LMB_Data_Addr_4(30) <= \<const0>\;
  LMB_Data_Addr_4(31) <= \<const0>\;
  LMB_Data_Addr_5(0) <= \<const0>\;
  LMB_Data_Addr_5(1) <= \<const0>\;
  LMB_Data_Addr_5(2) <= \<const0>\;
  LMB_Data_Addr_5(3) <= \<const0>\;
  LMB_Data_Addr_5(4) <= \<const0>\;
  LMB_Data_Addr_5(5) <= \<const0>\;
  LMB_Data_Addr_5(6) <= \<const0>\;
  LMB_Data_Addr_5(7) <= \<const0>\;
  LMB_Data_Addr_5(8) <= \<const0>\;
  LMB_Data_Addr_5(9) <= \<const0>\;
  LMB_Data_Addr_5(10) <= \<const0>\;
  LMB_Data_Addr_5(11) <= \<const0>\;
  LMB_Data_Addr_5(12) <= \<const0>\;
  LMB_Data_Addr_5(13) <= \<const0>\;
  LMB_Data_Addr_5(14) <= \<const0>\;
  LMB_Data_Addr_5(15) <= \<const0>\;
  LMB_Data_Addr_5(16) <= \<const0>\;
  LMB_Data_Addr_5(17) <= \<const0>\;
  LMB_Data_Addr_5(18) <= \<const0>\;
  LMB_Data_Addr_5(19) <= \<const0>\;
  LMB_Data_Addr_5(20) <= \<const0>\;
  LMB_Data_Addr_5(21) <= \<const0>\;
  LMB_Data_Addr_5(22) <= \<const0>\;
  LMB_Data_Addr_5(23) <= \<const0>\;
  LMB_Data_Addr_5(24) <= \<const0>\;
  LMB_Data_Addr_5(25) <= \<const0>\;
  LMB_Data_Addr_5(26) <= \<const0>\;
  LMB_Data_Addr_5(27) <= \<const0>\;
  LMB_Data_Addr_5(28) <= \<const0>\;
  LMB_Data_Addr_5(29) <= \<const0>\;
  LMB_Data_Addr_5(30) <= \<const0>\;
  LMB_Data_Addr_5(31) <= \<const0>\;
  LMB_Data_Addr_6(0) <= \<const0>\;
  LMB_Data_Addr_6(1) <= \<const0>\;
  LMB_Data_Addr_6(2) <= \<const0>\;
  LMB_Data_Addr_6(3) <= \<const0>\;
  LMB_Data_Addr_6(4) <= \<const0>\;
  LMB_Data_Addr_6(5) <= \<const0>\;
  LMB_Data_Addr_6(6) <= \<const0>\;
  LMB_Data_Addr_6(7) <= \<const0>\;
  LMB_Data_Addr_6(8) <= \<const0>\;
  LMB_Data_Addr_6(9) <= \<const0>\;
  LMB_Data_Addr_6(10) <= \<const0>\;
  LMB_Data_Addr_6(11) <= \<const0>\;
  LMB_Data_Addr_6(12) <= \<const0>\;
  LMB_Data_Addr_6(13) <= \<const0>\;
  LMB_Data_Addr_6(14) <= \<const0>\;
  LMB_Data_Addr_6(15) <= \<const0>\;
  LMB_Data_Addr_6(16) <= \<const0>\;
  LMB_Data_Addr_6(17) <= \<const0>\;
  LMB_Data_Addr_6(18) <= \<const0>\;
  LMB_Data_Addr_6(19) <= \<const0>\;
  LMB_Data_Addr_6(20) <= \<const0>\;
  LMB_Data_Addr_6(21) <= \<const0>\;
  LMB_Data_Addr_6(22) <= \<const0>\;
  LMB_Data_Addr_6(23) <= \<const0>\;
  LMB_Data_Addr_6(24) <= \<const0>\;
  LMB_Data_Addr_6(25) <= \<const0>\;
  LMB_Data_Addr_6(26) <= \<const0>\;
  LMB_Data_Addr_6(27) <= \<const0>\;
  LMB_Data_Addr_6(28) <= \<const0>\;
  LMB_Data_Addr_6(29) <= \<const0>\;
  LMB_Data_Addr_6(30) <= \<const0>\;
  LMB_Data_Addr_6(31) <= \<const0>\;
  LMB_Data_Addr_7(0) <= \<const0>\;
  LMB_Data_Addr_7(1) <= \<const0>\;
  LMB_Data_Addr_7(2) <= \<const0>\;
  LMB_Data_Addr_7(3) <= \<const0>\;
  LMB_Data_Addr_7(4) <= \<const0>\;
  LMB_Data_Addr_7(5) <= \<const0>\;
  LMB_Data_Addr_7(6) <= \<const0>\;
  LMB_Data_Addr_7(7) <= \<const0>\;
  LMB_Data_Addr_7(8) <= \<const0>\;
  LMB_Data_Addr_7(9) <= \<const0>\;
  LMB_Data_Addr_7(10) <= \<const0>\;
  LMB_Data_Addr_7(11) <= \<const0>\;
  LMB_Data_Addr_7(12) <= \<const0>\;
  LMB_Data_Addr_7(13) <= \<const0>\;
  LMB_Data_Addr_7(14) <= \<const0>\;
  LMB_Data_Addr_7(15) <= \<const0>\;
  LMB_Data_Addr_7(16) <= \<const0>\;
  LMB_Data_Addr_7(17) <= \<const0>\;
  LMB_Data_Addr_7(18) <= \<const0>\;
  LMB_Data_Addr_7(19) <= \<const0>\;
  LMB_Data_Addr_7(20) <= \<const0>\;
  LMB_Data_Addr_7(21) <= \<const0>\;
  LMB_Data_Addr_7(22) <= \<const0>\;
  LMB_Data_Addr_7(23) <= \<const0>\;
  LMB_Data_Addr_7(24) <= \<const0>\;
  LMB_Data_Addr_7(25) <= \<const0>\;
  LMB_Data_Addr_7(26) <= \<const0>\;
  LMB_Data_Addr_7(27) <= \<const0>\;
  LMB_Data_Addr_7(28) <= \<const0>\;
  LMB_Data_Addr_7(29) <= \<const0>\;
  LMB_Data_Addr_7(30) <= \<const0>\;
  LMB_Data_Addr_7(31) <= \<const0>\;
  LMB_Data_Addr_8(0) <= \<const0>\;
  LMB_Data_Addr_8(1) <= \<const0>\;
  LMB_Data_Addr_8(2) <= \<const0>\;
  LMB_Data_Addr_8(3) <= \<const0>\;
  LMB_Data_Addr_8(4) <= \<const0>\;
  LMB_Data_Addr_8(5) <= \<const0>\;
  LMB_Data_Addr_8(6) <= \<const0>\;
  LMB_Data_Addr_8(7) <= \<const0>\;
  LMB_Data_Addr_8(8) <= \<const0>\;
  LMB_Data_Addr_8(9) <= \<const0>\;
  LMB_Data_Addr_8(10) <= \<const0>\;
  LMB_Data_Addr_8(11) <= \<const0>\;
  LMB_Data_Addr_8(12) <= \<const0>\;
  LMB_Data_Addr_8(13) <= \<const0>\;
  LMB_Data_Addr_8(14) <= \<const0>\;
  LMB_Data_Addr_8(15) <= \<const0>\;
  LMB_Data_Addr_8(16) <= \<const0>\;
  LMB_Data_Addr_8(17) <= \<const0>\;
  LMB_Data_Addr_8(18) <= \<const0>\;
  LMB_Data_Addr_8(19) <= \<const0>\;
  LMB_Data_Addr_8(20) <= \<const0>\;
  LMB_Data_Addr_8(21) <= \<const0>\;
  LMB_Data_Addr_8(22) <= \<const0>\;
  LMB_Data_Addr_8(23) <= \<const0>\;
  LMB_Data_Addr_8(24) <= \<const0>\;
  LMB_Data_Addr_8(25) <= \<const0>\;
  LMB_Data_Addr_8(26) <= \<const0>\;
  LMB_Data_Addr_8(27) <= \<const0>\;
  LMB_Data_Addr_8(28) <= \<const0>\;
  LMB_Data_Addr_8(29) <= \<const0>\;
  LMB_Data_Addr_8(30) <= \<const0>\;
  LMB_Data_Addr_8(31) <= \<const0>\;
  LMB_Data_Addr_9(0) <= \<const0>\;
  LMB_Data_Addr_9(1) <= \<const0>\;
  LMB_Data_Addr_9(2) <= \<const0>\;
  LMB_Data_Addr_9(3) <= \<const0>\;
  LMB_Data_Addr_9(4) <= \<const0>\;
  LMB_Data_Addr_9(5) <= \<const0>\;
  LMB_Data_Addr_9(6) <= \<const0>\;
  LMB_Data_Addr_9(7) <= \<const0>\;
  LMB_Data_Addr_9(8) <= \<const0>\;
  LMB_Data_Addr_9(9) <= \<const0>\;
  LMB_Data_Addr_9(10) <= \<const0>\;
  LMB_Data_Addr_9(11) <= \<const0>\;
  LMB_Data_Addr_9(12) <= \<const0>\;
  LMB_Data_Addr_9(13) <= \<const0>\;
  LMB_Data_Addr_9(14) <= \<const0>\;
  LMB_Data_Addr_9(15) <= \<const0>\;
  LMB_Data_Addr_9(16) <= \<const0>\;
  LMB_Data_Addr_9(17) <= \<const0>\;
  LMB_Data_Addr_9(18) <= \<const0>\;
  LMB_Data_Addr_9(19) <= \<const0>\;
  LMB_Data_Addr_9(20) <= \<const0>\;
  LMB_Data_Addr_9(21) <= \<const0>\;
  LMB_Data_Addr_9(22) <= \<const0>\;
  LMB_Data_Addr_9(23) <= \<const0>\;
  LMB_Data_Addr_9(24) <= \<const0>\;
  LMB_Data_Addr_9(25) <= \<const0>\;
  LMB_Data_Addr_9(26) <= \<const0>\;
  LMB_Data_Addr_9(27) <= \<const0>\;
  LMB_Data_Addr_9(28) <= \<const0>\;
  LMB_Data_Addr_9(29) <= \<const0>\;
  LMB_Data_Addr_9(30) <= \<const0>\;
  LMB_Data_Addr_9(31) <= \<const0>\;
  LMB_Data_Write_0(0) <= \<const0>\;
  LMB_Data_Write_0(1) <= \<const0>\;
  LMB_Data_Write_0(2) <= \<const0>\;
  LMB_Data_Write_0(3) <= \<const0>\;
  LMB_Data_Write_0(4) <= \<const0>\;
  LMB_Data_Write_0(5) <= \<const0>\;
  LMB_Data_Write_0(6) <= \<const0>\;
  LMB_Data_Write_0(7) <= \<const0>\;
  LMB_Data_Write_0(8) <= \<const0>\;
  LMB_Data_Write_0(9) <= \<const0>\;
  LMB_Data_Write_0(10) <= \<const0>\;
  LMB_Data_Write_0(11) <= \<const0>\;
  LMB_Data_Write_0(12) <= \<const0>\;
  LMB_Data_Write_0(13) <= \<const0>\;
  LMB_Data_Write_0(14) <= \<const0>\;
  LMB_Data_Write_0(15) <= \<const0>\;
  LMB_Data_Write_0(16) <= \<const0>\;
  LMB_Data_Write_0(17) <= \<const0>\;
  LMB_Data_Write_0(18) <= \<const0>\;
  LMB_Data_Write_0(19) <= \<const0>\;
  LMB_Data_Write_0(20) <= \<const0>\;
  LMB_Data_Write_0(21) <= \<const0>\;
  LMB_Data_Write_0(22) <= \<const0>\;
  LMB_Data_Write_0(23) <= \<const0>\;
  LMB_Data_Write_0(24) <= \<const0>\;
  LMB_Data_Write_0(25) <= \<const0>\;
  LMB_Data_Write_0(26) <= \<const0>\;
  LMB_Data_Write_0(27) <= \<const0>\;
  LMB_Data_Write_0(28) <= \<const0>\;
  LMB_Data_Write_0(29) <= \<const0>\;
  LMB_Data_Write_0(30) <= \<const0>\;
  LMB_Data_Write_0(31) <= \<const0>\;
  LMB_Data_Write_1(0) <= \<const0>\;
  LMB_Data_Write_1(1) <= \<const0>\;
  LMB_Data_Write_1(2) <= \<const0>\;
  LMB_Data_Write_1(3) <= \<const0>\;
  LMB_Data_Write_1(4) <= \<const0>\;
  LMB_Data_Write_1(5) <= \<const0>\;
  LMB_Data_Write_1(6) <= \<const0>\;
  LMB_Data_Write_1(7) <= \<const0>\;
  LMB_Data_Write_1(8) <= \<const0>\;
  LMB_Data_Write_1(9) <= \<const0>\;
  LMB_Data_Write_1(10) <= \<const0>\;
  LMB_Data_Write_1(11) <= \<const0>\;
  LMB_Data_Write_1(12) <= \<const0>\;
  LMB_Data_Write_1(13) <= \<const0>\;
  LMB_Data_Write_1(14) <= \<const0>\;
  LMB_Data_Write_1(15) <= \<const0>\;
  LMB_Data_Write_1(16) <= \<const0>\;
  LMB_Data_Write_1(17) <= \<const0>\;
  LMB_Data_Write_1(18) <= \<const0>\;
  LMB_Data_Write_1(19) <= \<const0>\;
  LMB_Data_Write_1(20) <= \<const0>\;
  LMB_Data_Write_1(21) <= \<const0>\;
  LMB_Data_Write_1(22) <= \<const0>\;
  LMB_Data_Write_1(23) <= \<const0>\;
  LMB_Data_Write_1(24) <= \<const0>\;
  LMB_Data_Write_1(25) <= \<const0>\;
  LMB_Data_Write_1(26) <= \<const0>\;
  LMB_Data_Write_1(27) <= \<const0>\;
  LMB_Data_Write_1(28) <= \<const0>\;
  LMB_Data_Write_1(29) <= \<const0>\;
  LMB_Data_Write_1(30) <= \<const0>\;
  LMB_Data_Write_1(31) <= \<const0>\;
  LMB_Data_Write_10(0) <= \<const0>\;
  LMB_Data_Write_10(1) <= \<const0>\;
  LMB_Data_Write_10(2) <= \<const0>\;
  LMB_Data_Write_10(3) <= \<const0>\;
  LMB_Data_Write_10(4) <= \<const0>\;
  LMB_Data_Write_10(5) <= \<const0>\;
  LMB_Data_Write_10(6) <= \<const0>\;
  LMB_Data_Write_10(7) <= \<const0>\;
  LMB_Data_Write_10(8) <= \<const0>\;
  LMB_Data_Write_10(9) <= \<const0>\;
  LMB_Data_Write_10(10) <= \<const0>\;
  LMB_Data_Write_10(11) <= \<const0>\;
  LMB_Data_Write_10(12) <= \<const0>\;
  LMB_Data_Write_10(13) <= \<const0>\;
  LMB_Data_Write_10(14) <= \<const0>\;
  LMB_Data_Write_10(15) <= \<const0>\;
  LMB_Data_Write_10(16) <= \<const0>\;
  LMB_Data_Write_10(17) <= \<const0>\;
  LMB_Data_Write_10(18) <= \<const0>\;
  LMB_Data_Write_10(19) <= \<const0>\;
  LMB_Data_Write_10(20) <= \<const0>\;
  LMB_Data_Write_10(21) <= \<const0>\;
  LMB_Data_Write_10(22) <= \<const0>\;
  LMB_Data_Write_10(23) <= \<const0>\;
  LMB_Data_Write_10(24) <= \<const0>\;
  LMB_Data_Write_10(25) <= \<const0>\;
  LMB_Data_Write_10(26) <= \<const0>\;
  LMB_Data_Write_10(27) <= \<const0>\;
  LMB_Data_Write_10(28) <= \<const0>\;
  LMB_Data_Write_10(29) <= \<const0>\;
  LMB_Data_Write_10(30) <= \<const0>\;
  LMB_Data_Write_10(31) <= \<const0>\;
  LMB_Data_Write_11(0) <= \<const0>\;
  LMB_Data_Write_11(1) <= \<const0>\;
  LMB_Data_Write_11(2) <= \<const0>\;
  LMB_Data_Write_11(3) <= \<const0>\;
  LMB_Data_Write_11(4) <= \<const0>\;
  LMB_Data_Write_11(5) <= \<const0>\;
  LMB_Data_Write_11(6) <= \<const0>\;
  LMB_Data_Write_11(7) <= \<const0>\;
  LMB_Data_Write_11(8) <= \<const0>\;
  LMB_Data_Write_11(9) <= \<const0>\;
  LMB_Data_Write_11(10) <= \<const0>\;
  LMB_Data_Write_11(11) <= \<const0>\;
  LMB_Data_Write_11(12) <= \<const0>\;
  LMB_Data_Write_11(13) <= \<const0>\;
  LMB_Data_Write_11(14) <= \<const0>\;
  LMB_Data_Write_11(15) <= \<const0>\;
  LMB_Data_Write_11(16) <= \<const0>\;
  LMB_Data_Write_11(17) <= \<const0>\;
  LMB_Data_Write_11(18) <= \<const0>\;
  LMB_Data_Write_11(19) <= \<const0>\;
  LMB_Data_Write_11(20) <= \<const0>\;
  LMB_Data_Write_11(21) <= \<const0>\;
  LMB_Data_Write_11(22) <= \<const0>\;
  LMB_Data_Write_11(23) <= \<const0>\;
  LMB_Data_Write_11(24) <= \<const0>\;
  LMB_Data_Write_11(25) <= \<const0>\;
  LMB_Data_Write_11(26) <= \<const0>\;
  LMB_Data_Write_11(27) <= \<const0>\;
  LMB_Data_Write_11(28) <= \<const0>\;
  LMB_Data_Write_11(29) <= \<const0>\;
  LMB_Data_Write_11(30) <= \<const0>\;
  LMB_Data_Write_11(31) <= \<const0>\;
  LMB_Data_Write_12(0) <= \<const0>\;
  LMB_Data_Write_12(1) <= \<const0>\;
  LMB_Data_Write_12(2) <= \<const0>\;
  LMB_Data_Write_12(3) <= \<const0>\;
  LMB_Data_Write_12(4) <= \<const0>\;
  LMB_Data_Write_12(5) <= \<const0>\;
  LMB_Data_Write_12(6) <= \<const0>\;
  LMB_Data_Write_12(7) <= \<const0>\;
  LMB_Data_Write_12(8) <= \<const0>\;
  LMB_Data_Write_12(9) <= \<const0>\;
  LMB_Data_Write_12(10) <= \<const0>\;
  LMB_Data_Write_12(11) <= \<const0>\;
  LMB_Data_Write_12(12) <= \<const0>\;
  LMB_Data_Write_12(13) <= \<const0>\;
  LMB_Data_Write_12(14) <= \<const0>\;
  LMB_Data_Write_12(15) <= \<const0>\;
  LMB_Data_Write_12(16) <= \<const0>\;
  LMB_Data_Write_12(17) <= \<const0>\;
  LMB_Data_Write_12(18) <= \<const0>\;
  LMB_Data_Write_12(19) <= \<const0>\;
  LMB_Data_Write_12(20) <= \<const0>\;
  LMB_Data_Write_12(21) <= \<const0>\;
  LMB_Data_Write_12(22) <= \<const0>\;
  LMB_Data_Write_12(23) <= \<const0>\;
  LMB_Data_Write_12(24) <= \<const0>\;
  LMB_Data_Write_12(25) <= \<const0>\;
  LMB_Data_Write_12(26) <= \<const0>\;
  LMB_Data_Write_12(27) <= \<const0>\;
  LMB_Data_Write_12(28) <= \<const0>\;
  LMB_Data_Write_12(29) <= \<const0>\;
  LMB_Data_Write_12(30) <= \<const0>\;
  LMB_Data_Write_12(31) <= \<const0>\;
  LMB_Data_Write_13(0) <= \<const0>\;
  LMB_Data_Write_13(1) <= \<const0>\;
  LMB_Data_Write_13(2) <= \<const0>\;
  LMB_Data_Write_13(3) <= \<const0>\;
  LMB_Data_Write_13(4) <= \<const0>\;
  LMB_Data_Write_13(5) <= \<const0>\;
  LMB_Data_Write_13(6) <= \<const0>\;
  LMB_Data_Write_13(7) <= \<const0>\;
  LMB_Data_Write_13(8) <= \<const0>\;
  LMB_Data_Write_13(9) <= \<const0>\;
  LMB_Data_Write_13(10) <= \<const0>\;
  LMB_Data_Write_13(11) <= \<const0>\;
  LMB_Data_Write_13(12) <= \<const0>\;
  LMB_Data_Write_13(13) <= \<const0>\;
  LMB_Data_Write_13(14) <= \<const0>\;
  LMB_Data_Write_13(15) <= \<const0>\;
  LMB_Data_Write_13(16) <= \<const0>\;
  LMB_Data_Write_13(17) <= \<const0>\;
  LMB_Data_Write_13(18) <= \<const0>\;
  LMB_Data_Write_13(19) <= \<const0>\;
  LMB_Data_Write_13(20) <= \<const0>\;
  LMB_Data_Write_13(21) <= \<const0>\;
  LMB_Data_Write_13(22) <= \<const0>\;
  LMB_Data_Write_13(23) <= \<const0>\;
  LMB_Data_Write_13(24) <= \<const0>\;
  LMB_Data_Write_13(25) <= \<const0>\;
  LMB_Data_Write_13(26) <= \<const0>\;
  LMB_Data_Write_13(27) <= \<const0>\;
  LMB_Data_Write_13(28) <= \<const0>\;
  LMB_Data_Write_13(29) <= \<const0>\;
  LMB_Data_Write_13(30) <= \<const0>\;
  LMB_Data_Write_13(31) <= \<const0>\;
  LMB_Data_Write_14(0) <= \<const0>\;
  LMB_Data_Write_14(1) <= \<const0>\;
  LMB_Data_Write_14(2) <= \<const0>\;
  LMB_Data_Write_14(3) <= \<const0>\;
  LMB_Data_Write_14(4) <= \<const0>\;
  LMB_Data_Write_14(5) <= \<const0>\;
  LMB_Data_Write_14(6) <= \<const0>\;
  LMB_Data_Write_14(7) <= \<const0>\;
  LMB_Data_Write_14(8) <= \<const0>\;
  LMB_Data_Write_14(9) <= \<const0>\;
  LMB_Data_Write_14(10) <= \<const0>\;
  LMB_Data_Write_14(11) <= \<const0>\;
  LMB_Data_Write_14(12) <= \<const0>\;
  LMB_Data_Write_14(13) <= \<const0>\;
  LMB_Data_Write_14(14) <= \<const0>\;
  LMB_Data_Write_14(15) <= \<const0>\;
  LMB_Data_Write_14(16) <= \<const0>\;
  LMB_Data_Write_14(17) <= \<const0>\;
  LMB_Data_Write_14(18) <= \<const0>\;
  LMB_Data_Write_14(19) <= \<const0>\;
  LMB_Data_Write_14(20) <= \<const0>\;
  LMB_Data_Write_14(21) <= \<const0>\;
  LMB_Data_Write_14(22) <= \<const0>\;
  LMB_Data_Write_14(23) <= \<const0>\;
  LMB_Data_Write_14(24) <= \<const0>\;
  LMB_Data_Write_14(25) <= \<const0>\;
  LMB_Data_Write_14(26) <= \<const0>\;
  LMB_Data_Write_14(27) <= \<const0>\;
  LMB_Data_Write_14(28) <= \<const0>\;
  LMB_Data_Write_14(29) <= \<const0>\;
  LMB_Data_Write_14(30) <= \<const0>\;
  LMB_Data_Write_14(31) <= \<const0>\;
  LMB_Data_Write_15(0) <= \<const0>\;
  LMB_Data_Write_15(1) <= \<const0>\;
  LMB_Data_Write_15(2) <= \<const0>\;
  LMB_Data_Write_15(3) <= \<const0>\;
  LMB_Data_Write_15(4) <= \<const0>\;
  LMB_Data_Write_15(5) <= \<const0>\;
  LMB_Data_Write_15(6) <= \<const0>\;
  LMB_Data_Write_15(7) <= \<const0>\;
  LMB_Data_Write_15(8) <= \<const0>\;
  LMB_Data_Write_15(9) <= \<const0>\;
  LMB_Data_Write_15(10) <= \<const0>\;
  LMB_Data_Write_15(11) <= \<const0>\;
  LMB_Data_Write_15(12) <= \<const0>\;
  LMB_Data_Write_15(13) <= \<const0>\;
  LMB_Data_Write_15(14) <= \<const0>\;
  LMB_Data_Write_15(15) <= \<const0>\;
  LMB_Data_Write_15(16) <= \<const0>\;
  LMB_Data_Write_15(17) <= \<const0>\;
  LMB_Data_Write_15(18) <= \<const0>\;
  LMB_Data_Write_15(19) <= \<const0>\;
  LMB_Data_Write_15(20) <= \<const0>\;
  LMB_Data_Write_15(21) <= \<const0>\;
  LMB_Data_Write_15(22) <= \<const0>\;
  LMB_Data_Write_15(23) <= \<const0>\;
  LMB_Data_Write_15(24) <= \<const0>\;
  LMB_Data_Write_15(25) <= \<const0>\;
  LMB_Data_Write_15(26) <= \<const0>\;
  LMB_Data_Write_15(27) <= \<const0>\;
  LMB_Data_Write_15(28) <= \<const0>\;
  LMB_Data_Write_15(29) <= \<const0>\;
  LMB_Data_Write_15(30) <= \<const0>\;
  LMB_Data_Write_15(31) <= \<const0>\;
  LMB_Data_Write_16(0) <= \<const0>\;
  LMB_Data_Write_16(1) <= \<const0>\;
  LMB_Data_Write_16(2) <= \<const0>\;
  LMB_Data_Write_16(3) <= \<const0>\;
  LMB_Data_Write_16(4) <= \<const0>\;
  LMB_Data_Write_16(5) <= \<const0>\;
  LMB_Data_Write_16(6) <= \<const0>\;
  LMB_Data_Write_16(7) <= \<const0>\;
  LMB_Data_Write_16(8) <= \<const0>\;
  LMB_Data_Write_16(9) <= \<const0>\;
  LMB_Data_Write_16(10) <= \<const0>\;
  LMB_Data_Write_16(11) <= \<const0>\;
  LMB_Data_Write_16(12) <= \<const0>\;
  LMB_Data_Write_16(13) <= \<const0>\;
  LMB_Data_Write_16(14) <= \<const0>\;
  LMB_Data_Write_16(15) <= \<const0>\;
  LMB_Data_Write_16(16) <= \<const0>\;
  LMB_Data_Write_16(17) <= \<const0>\;
  LMB_Data_Write_16(18) <= \<const0>\;
  LMB_Data_Write_16(19) <= \<const0>\;
  LMB_Data_Write_16(20) <= \<const0>\;
  LMB_Data_Write_16(21) <= \<const0>\;
  LMB_Data_Write_16(22) <= \<const0>\;
  LMB_Data_Write_16(23) <= \<const0>\;
  LMB_Data_Write_16(24) <= \<const0>\;
  LMB_Data_Write_16(25) <= \<const0>\;
  LMB_Data_Write_16(26) <= \<const0>\;
  LMB_Data_Write_16(27) <= \<const0>\;
  LMB_Data_Write_16(28) <= \<const0>\;
  LMB_Data_Write_16(29) <= \<const0>\;
  LMB_Data_Write_16(30) <= \<const0>\;
  LMB_Data_Write_16(31) <= \<const0>\;
  LMB_Data_Write_17(0) <= \<const0>\;
  LMB_Data_Write_17(1) <= \<const0>\;
  LMB_Data_Write_17(2) <= \<const0>\;
  LMB_Data_Write_17(3) <= \<const0>\;
  LMB_Data_Write_17(4) <= \<const0>\;
  LMB_Data_Write_17(5) <= \<const0>\;
  LMB_Data_Write_17(6) <= \<const0>\;
  LMB_Data_Write_17(7) <= \<const0>\;
  LMB_Data_Write_17(8) <= \<const0>\;
  LMB_Data_Write_17(9) <= \<const0>\;
  LMB_Data_Write_17(10) <= \<const0>\;
  LMB_Data_Write_17(11) <= \<const0>\;
  LMB_Data_Write_17(12) <= \<const0>\;
  LMB_Data_Write_17(13) <= \<const0>\;
  LMB_Data_Write_17(14) <= \<const0>\;
  LMB_Data_Write_17(15) <= \<const0>\;
  LMB_Data_Write_17(16) <= \<const0>\;
  LMB_Data_Write_17(17) <= \<const0>\;
  LMB_Data_Write_17(18) <= \<const0>\;
  LMB_Data_Write_17(19) <= \<const0>\;
  LMB_Data_Write_17(20) <= \<const0>\;
  LMB_Data_Write_17(21) <= \<const0>\;
  LMB_Data_Write_17(22) <= \<const0>\;
  LMB_Data_Write_17(23) <= \<const0>\;
  LMB_Data_Write_17(24) <= \<const0>\;
  LMB_Data_Write_17(25) <= \<const0>\;
  LMB_Data_Write_17(26) <= \<const0>\;
  LMB_Data_Write_17(27) <= \<const0>\;
  LMB_Data_Write_17(28) <= \<const0>\;
  LMB_Data_Write_17(29) <= \<const0>\;
  LMB_Data_Write_17(30) <= \<const0>\;
  LMB_Data_Write_17(31) <= \<const0>\;
  LMB_Data_Write_18(0) <= \<const0>\;
  LMB_Data_Write_18(1) <= \<const0>\;
  LMB_Data_Write_18(2) <= \<const0>\;
  LMB_Data_Write_18(3) <= \<const0>\;
  LMB_Data_Write_18(4) <= \<const0>\;
  LMB_Data_Write_18(5) <= \<const0>\;
  LMB_Data_Write_18(6) <= \<const0>\;
  LMB_Data_Write_18(7) <= \<const0>\;
  LMB_Data_Write_18(8) <= \<const0>\;
  LMB_Data_Write_18(9) <= \<const0>\;
  LMB_Data_Write_18(10) <= \<const0>\;
  LMB_Data_Write_18(11) <= \<const0>\;
  LMB_Data_Write_18(12) <= \<const0>\;
  LMB_Data_Write_18(13) <= \<const0>\;
  LMB_Data_Write_18(14) <= \<const0>\;
  LMB_Data_Write_18(15) <= \<const0>\;
  LMB_Data_Write_18(16) <= \<const0>\;
  LMB_Data_Write_18(17) <= \<const0>\;
  LMB_Data_Write_18(18) <= \<const0>\;
  LMB_Data_Write_18(19) <= \<const0>\;
  LMB_Data_Write_18(20) <= \<const0>\;
  LMB_Data_Write_18(21) <= \<const0>\;
  LMB_Data_Write_18(22) <= \<const0>\;
  LMB_Data_Write_18(23) <= \<const0>\;
  LMB_Data_Write_18(24) <= \<const0>\;
  LMB_Data_Write_18(25) <= \<const0>\;
  LMB_Data_Write_18(26) <= \<const0>\;
  LMB_Data_Write_18(27) <= \<const0>\;
  LMB_Data_Write_18(28) <= \<const0>\;
  LMB_Data_Write_18(29) <= \<const0>\;
  LMB_Data_Write_18(30) <= \<const0>\;
  LMB_Data_Write_18(31) <= \<const0>\;
  LMB_Data_Write_19(0) <= \<const0>\;
  LMB_Data_Write_19(1) <= \<const0>\;
  LMB_Data_Write_19(2) <= \<const0>\;
  LMB_Data_Write_19(3) <= \<const0>\;
  LMB_Data_Write_19(4) <= \<const0>\;
  LMB_Data_Write_19(5) <= \<const0>\;
  LMB_Data_Write_19(6) <= \<const0>\;
  LMB_Data_Write_19(7) <= \<const0>\;
  LMB_Data_Write_19(8) <= \<const0>\;
  LMB_Data_Write_19(9) <= \<const0>\;
  LMB_Data_Write_19(10) <= \<const0>\;
  LMB_Data_Write_19(11) <= \<const0>\;
  LMB_Data_Write_19(12) <= \<const0>\;
  LMB_Data_Write_19(13) <= \<const0>\;
  LMB_Data_Write_19(14) <= \<const0>\;
  LMB_Data_Write_19(15) <= \<const0>\;
  LMB_Data_Write_19(16) <= \<const0>\;
  LMB_Data_Write_19(17) <= \<const0>\;
  LMB_Data_Write_19(18) <= \<const0>\;
  LMB_Data_Write_19(19) <= \<const0>\;
  LMB_Data_Write_19(20) <= \<const0>\;
  LMB_Data_Write_19(21) <= \<const0>\;
  LMB_Data_Write_19(22) <= \<const0>\;
  LMB_Data_Write_19(23) <= \<const0>\;
  LMB_Data_Write_19(24) <= \<const0>\;
  LMB_Data_Write_19(25) <= \<const0>\;
  LMB_Data_Write_19(26) <= \<const0>\;
  LMB_Data_Write_19(27) <= \<const0>\;
  LMB_Data_Write_19(28) <= \<const0>\;
  LMB_Data_Write_19(29) <= \<const0>\;
  LMB_Data_Write_19(30) <= \<const0>\;
  LMB_Data_Write_19(31) <= \<const0>\;
  LMB_Data_Write_2(0) <= \<const0>\;
  LMB_Data_Write_2(1) <= \<const0>\;
  LMB_Data_Write_2(2) <= \<const0>\;
  LMB_Data_Write_2(3) <= \<const0>\;
  LMB_Data_Write_2(4) <= \<const0>\;
  LMB_Data_Write_2(5) <= \<const0>\;
  LMB_Data_Write_2(6) <= \<const0>\;
  LMB_Data_Write_2(7) <= \<const0>\;
  LMB_Data_Write_2(8) <= \<const0>\;
  LMB_Data_Write_2(9) <= \<const0>\;
  LMB_Data_Write_2(10) <= \<const0>\;
  LMB_Data_Write_2(11) <= \<const0>\;
  LMB_Data_Write_2(12) <= \<const0>\;
  LMB_Data_Write_2(13) <= \<const0>\;
  LMB_Data_Write_2(14) <= \<const0>\;
  LMB_Data_Write_2(15) <= \<const0>\;
  LMB_Data_Write_2(16) <= \<const0>\;
  LMB_Data_Write_2(17) <= \<const0>\;
  LMB_Data_Write_2(18) <= \<const0>\;
  LMB_Data_Write_2(19) <= \<const0>\;
  LMB_Data_Write_2(20) <= \<const0>\;
  LMB_Data_Write_2(21) <= \<const0>\;
  LMB_Data_Write_2(22) <= \<const0>\;
  LMB_Data_Write_2(23) <= \<const0>\;
  LMB_Data_Write_2(24) <= \<const0>\;
  LMB_Data_Write_2(25) <= \<const0>\;
  LMB_Data_Write_2(26) <= \<const0>\;
  LMB_Data_Write_2(27) <= \<const0>\;
  LMB_Data_Write_2(28) <= \<const0>\;
  LMB_Data_Write_2(29) <= \<const0>\;
  LMB_Data_Write_2(30) <= \<const0>\;
  LMB_Data_Write_2(31) <= \<const0>\;
  LMB_Data_Write_20(0) <= \<const0>\;
  LMB_Data_Write_20(1) <= \<const0>\;
  LMB_Data_Write_20(2) <= \<const0>\;
  LMB_Data_Write_20(3) <= \<const0>\;
  LMB_Data_Write_20(4) <= \<const0>\;
  LMB_Data_Write_20(5) <= \<const0>\;
  LMB_Data_Write_20(6) <= \<const0>\;
  LMB_Data_Write_20(7) <= \<const0>\;
  LMB_Data_Write_20(8) <= \<const0>\;
  LMB_Data_Write_20(9) <= \<const0>\;
  LMB_Data_Write_20(10) <= \<const0>\;
  LMB_Data_Write_20(11) <= \<const0>\;
  LMB_Data_Write_20(12) <= \<const0>\;
  LMB_Data_Write_20(13) <= \<const0>\;
  LMB_Data_Write_20(14) <= \<const0>\;
  LMB_Data_Write_20(15) <= \<const0>\;
  LMB_Data_Write_20(16) <= \<const0>\;
  LMB_Data_Write_20(17) <= \<const0>\;
  LMB_Data_Write_20(18) <= \<const0>\;
  LMB_Data_Write_20(19) <= \<const0>\;
  LMB_Data_Write_20(20) <= \<const0>\;
  LMB_Data_Write_20(21) <= \<const0>\;
  LMB_Data_Write_20(22) <= \<const0>\;
  LMB_Data_Write_20(23) <= \<const0>\;
  LMB_Data_Write_20(24) <= \<const0>\;
  LMB_Data_Write_20(25) <= \<const0>\;
  LMB_Data_Write_20(26) <= \<const0>\;
  LMB_Data_Write_20(27) <= \<const0>\;
  LMB_Data_Write_20(28) <= \<const0>\;
  LMB_Data_Write_20(29) <= \<const0>\;
  LMB_Data_Write_20(30) <= \<const0>\;
  LMB_Data_Write_20(31) <= \<const0>\;
  LMB_Data_Write_21(0) <= \<const0>\;
  LMB_Data_Write_21(1) <= \<const0>\;
  LMB_Data_Write_21(2) <= \<const0>\;
  LMB_Data_Write_21(3) <= \<const0>\;
  LMB_Data_Write_21(4) <= \<const0>\;
  LMB_Data_Write_21(5) <= \<const0>\;
  LMB_Data_Write_21(6) <= \<const0>\;
  LMB_Data_Write_21(7) <= \<const0>\;
  LMB_Data_Write_21(8) <= \<const0>\;
  LMB_Data_Write_21(9) <= \<const0>\;
  LMB_Data_Write_21(10) <= \<const0>\;
  LMB_Data_Write_21(11) <= \<const0>\;
  LMB_Data_Write_21(12) <= \<const0>\;
  LMB_Data_Write_21(13) <= \<const0>\;
  LMB_Data_Write_21(14) <= \<const0>\;
  LMB_Data_Write_21(15) <= \<const0>\;
  LMB_Data_Write_21(16) <= \<const0>\;
  LMB_Data_Write_21(17) <= \<const0>\;
  LMB_Data_Write_21(18) <= \<const0>\;
  LMB_Data_Write_21(19) <= \<const0>\;
  LMB_Data_Write_21(20) <= \<const0>\;
  LMB_Data_Write_21(21) <= \<const0>\;
  LMB_Data_Write_21(22) <= \<const0>\;
  LMB_Data_Write_21(23) <= \<const0>\;
  LMB_Data_Write_21(24) <= \<const0>\;
  LMB_Data_Write_21(25) <= \<const0>\;
  LMB_Data_Write_21(26) <= \<const0>\;
  LMB_Data_Write_21(27) <= \<const0>\;
  LMB_Data_Write_21(28) <= \<const0>\;
  LMB_Data_Write_21(29) <= \<const0>\;
  LMB_Data_Write_21(30) <= \<const0>\;
  LMB_Data_Write_21(31) <= \<const0>\;
  LMB_Data_Write_22(0) <= \<const0>\;
  LMB_Data_Write_22(1) <= \<const0>\;
  LMB_Data_Write_22(2) <= \<const0>\;
  LMB_Data_Write_22(3) <= \<const0>\;
  LMB_Data_Write_22(4) <= \<const0>\;
  LMB_Data_Write_22(5) <= \<const0>\;
  LMB_Data_Write_22(6) <= \<const0>\;
  LMB_Data_Write_22(7) <= \<const0>\;
  LMB_Data_Write_22(8) <= \<const0>\;
  LMB_Data_Write_22(9) <= \<const0>\;
  LMB_Data_Write_22(10) <= \<const0>\;
  LMB_Data_Write_22(11) <= \<const0>\;
  LMB_Data_Write_22(12) <= \<const0>\;
  LMB_Data_Write_22(13) <= \<const0>\;
  LMB_Data_Write_22(14) <= \<const0>\;
  LMB_Data_Write_22(15) <= \<const0>\;
  LMB_Data_Write_22(16) <= \<const0>\;
  LMB_Data_Write_22(17) <= \<const0>\;
  LMB_Data_Write_22(18) <= \<const0>\;
  LMB_Data_Write_22(19) <= \<const0>\;
  LMB_Data_Write_22(20) <= \<const0>\;
  LMB_Data_Write_22(21) <= \<const0>\;
  LMB_Data_Write_22(22) <= \<const0>\;
  LMB_Data_Write_22(23) <= \<const0>\;
  LMB_Data_Write_22(24) <= \<const0>\;
  LMB_Data_Write_22(25) <= \<const0>\;
  LMB_Data_Write_22(26) <= \<const0>\;
  LMB_Data_Write_22(27) <= \<const0>\;
  LMB_Data_Write_22(28) <= \<const0>\;
  LMB_Data_Write_22(29) <= \<const0>\;
  LMB_Data_Write_22(30) <= \<const0>\;
  LMB_Data_Write_22(31) <= \<const0>\;
  LMB_Data_Write_23(0) <= \<const0>\;
  LMB_Data_Write_23(1) <= \<const0>\;
  LMB_Data_Write_23(2) <= \<const0>\;
  LMB_Data_Write_23(3) <= \<const0>\;
  LMB_Data_Write_23(4) <= \<const0>\;
  LMB_Data_Write_23(5) <= \<const0>\;
  LMB_Data_Write_23(6) <= \<const0>\;
  LMB_Data_Write_23(7) <= \<const0>\;
  LMB_Data_Write_23(8) <= \<const0>\;
  LMB_Data_Write_23(9) <= \<const0>\;
  LMB_Data_Write_23(10) <= \<const0>\;
  LMB_Data_Write_23(11) <= \<const0>\;
  LMB_Data_Write_23(12) <= \<const0>\;
  LMB_Data_Write_23(13) <= \<const0>\;
  LMB_Data_Write_23(14) <= \<const0>\;
  LMB_Data_Write_23(15) <= \<const0>\;
  LMB_Data_Write_23(16) <= \<const0>\;
  LMB_Data_Write_23(17) <= \<const0>\;
  LMB_Data_Write_23(18) <= \<const0>\;
  LMB_Data_Write_23(19) <= \<const0>\;
  LMB_Data_Write_23(20) <= \<const0>\;
  LMB_Data_Write_23(21) <= \<const0>\;
  LMB_Data_Write_23(22) <= \<const0>\;
  LMB_Data_Write_23(23) <= \<const0>\;
  LMB_Data_Write_23(24) <= \<const0>\;
  LMB_Data_Write_23(25) <= \<const0>\;
  LMB_Data_Write_23(26) <= \<const0>\;
  LMB_Data_Write_23(27) <= \<const0>\;
  LMB_Data_Write_23(28) <= \<const0>\;
  LMB_Data_Write_23(29) <= \<const0>\;
  LMB_Data_Write_23(30) <= \<const0>\;
  LMB_Data_Write_23(31) <= \<const0>\;
  LMB_Data_Write_24(0) <= \<const0>\;
  LMB_Data_Write_24(1) <= \<const0>\;
  LMB_Data_Write_24(2) <= \<const0>\;
  LMB_Data_Write_24(3) <= \<const0>\;
  LMB_Data_Write_24(4) <= \<const0>\;
  LMB_Data_Write_24(5) <= \<const0>\;
  LMB_Data_Write_24(6) <= \<const0>\;
  LMB_Data_Write_24(7) <= \<const0>\;
  LMB_Data_Write_24(8) <= \<const0>\;
  LMB_Data_Write_24(9) <= \<const0>\;
  LMB_Data_Write_24(10) <= \<const0>\;
  LMB_Data_Write_24(11) <= \<const0>\;
  LMB_Data_Write_24(12) <= \<const0>\;
  LMB_Data_Write_24(13) <= \<const0>\;
  LMB_Data_Write_24(14) <= \<const0>\;
  LMB_Data_Write_24(15) <= \<const0>\;
  LMB_Data_Write_24(16) <= \<const0>\;
  LMB_Data_Write_24(17) <= \<const0>\;
  LMB_Data_Write_24(18) <= \<const0>\;
  LMB_Data_Write_24(19) <= \<const0>\;
  LMB_Data_Write_24(20) <= \<const0>\;
  LMB_Data_Write_24(21) <= \<const0>\;
  LMB_Data_Write_24(22) <= \<const0>\;
  LMB_Data_Write_24(23) <= \<const0>\;
  LMB_Data_Write_24(24) <= \<const0>\;
  LMB_Data_Write_24(25) <= \<const0>\;
  LMB_Data_Write_24(26) <= \<const0>\;
  LMB_Data_Write_24(27) <= \<const0>\;
  LMB_Data_Write_24(28) <= \<const0>\;
  LMB_Data_Write_24(29) <= \<const0>\;
  LMB_Data_Write_24(30) <= \<const0>\;
  LMB_Data_Write_24(31) <= \<const0>\;
  LMB_Data_Write_25(0) <= \<const0>\;
  LMB_Data_Write_25(1) <= \<const0>\;
  LMB_Data_Write_25(2) <= \<const0>\;
  LMB_Data_Write_25(3) <= \<const0>\;
  LMB_Data_Write_25(4) <= \<const0>\;
  LMB_Data_Write_25(5) <= \<const0>\;
  LMB_Data_Write_25(6) <= \<const0>\;
  LMB_Data_Write_25(7) <= \<const0>\;
  LMB_Data_Write_25(8) <= \<const0>\;
  LMB_Data_Write_25(9) <= \<const0>\;
  LMB_Data_Write_25(10) <= \<const0>\;
  LMB_Data_Write_25(11) <= \<const0>\;
  LMB_Data_Write_25(12) <= \<const0>\;
  LMB_Data_Write_25(13) <= \<const0>\;
  LMB_Data_Write_25(14) <= \<const0>\;
  LMB_Data_Write_25(15) <= \<const0>\;
  LMB_Data_Write_25(16) <= \<const0>\;
  LMB_Data_Write_25(17) <= \<const0>\;
  LMB_Data_Write_25(18) <= \<const0>\;
  LMB_Data_Write_25(19) <= \<const0>\;
  LMB_Data_Write_25(20) <= \<const0>\;
  LMB_Data_Write_25(21) <= \<const0>\;
  LMB_Data_Write_25(22) <= \<const0>\;
  LMB_Data_Write_25(23) <= \<const0>\;
  LMB_Data_Write_25(24) <= \<const0>\;
  LMB_Data_Write_25(25) <= \<const0>\;
  LMB_Data_Write_25(26) <= \<const0>\;
  LMB_Data_Write_25(27) <= \<const0>\;
  LMB_Data_Write_25(28) <= \<const0>\;
  LMB_Data_Write_25(29) <= \<const0>\;
  LMB_Data_Write_25(30) <= \<const0>\;
  LMB_Data_Write_25(31) <= \<const0>\;
  LMB_Data_Write_26(0) <= \<const0>\;
  LMB_Data_Write_26(1) <= \<const0>\;
  LMB_Data_Write_26(2) <= \<const0>\;
  LMB_Data_Write_26(3) <= \<const0>\;
  LMB_Data_Write_26(4) <= \<const0>\;
  LMB_Data_Write_26(5) <= \<const0>\;
  LMB_Data_Write_26(6) <= \<const0>\;
  LMB_Data_Write_26(7) <= \<const0>\;
  LMB_Data_Write_26(8) <= \<const0>\;
  LMB_Data_Write_26(9) <= \<const0>\;
  LMB_Data_Write_26(10) <= \<const0>\;
  LMB_Data_Write_26(11) <= \<const0>\;
  LMB_Data_Write_26(12) <= \<const0>\;
  LMB_Data_Write_26(13) <= \<const0>\;
  LMB_Data_Write_26(14) <= \<const0>\;
  LMB_Data_Write_26(15) <= \<const0>\;
  LMB_Data_Write_26(16) <= \<const0>\;
  LMB_Data_Write_26(17) <= \<const0>\;
  LMB_Data_Write_26(18) <= \<const0>\;
  LMB_Data_Write_26(19) <= \<const0>\;
  LMB_Data_Write_26(20) <= \<const0>\;
  LMB_Data_Write_26(21) <= \<const0>\;
  LMB_Data_Write_26(22) <= \<const0>\;
  LMB_Data_Write_26(23) <= \<const0>\;
  LMB_Data_Write_26(24) <= \<const0>\;
  LMB_Data_Write_26(25) <= \<const0>\;
  LMB_Data_Write_26(26) <= \<const0>\;
  LMB_Data_Write_26(27) <= \<const0>\;
  LMB_Data_Write_26(28) <= \<const0>\;
  LMB_Data_Write_26(29) <= \<const0>\;
  LMB_Data_Write_26(30) <= \<const0>\;
  LMB_Data_Write_26(31) <= \<const0>\;
  LMB_Data_Write_27(0) <= \<const0>\;
  LMB_Data_Write_27(1) <= \<const0>\;
  LMB_Data_Write_27(2) <= \<const0>\;
  LMB_Data_Write_27(3) <= \<const0>\;
  LMB_Data_Write_27(4) <= \<const0>\;
  LMB_Data_Write_27(5) <= \<const0>\;
  LMB_Data_Write_27(6) <= \<const0>\;
  LMB_Data_Write_27(7) <= \<const0>\;
  LMB_Data_Write_27(8) <= \<const0>\;
  LMB_Data_Write_27(9) <= \<const0>\;
  LMB_Data_Write_27(10) <= \<const0>\;
  LMB_Data_Write_27(11) <= \<const0>\;
  LMB_Data_Write_27(12) <= \<const0>\;
  LMB_Data_Write_27(13) <= \<const0>\;
  LMB_Data_Write_27(14) <= \<const0>\;
  LMB_Data_Write_27(15) <= \<const0>\;
  LMB_Data_Write_27(16) <= \<const0>\;
  LMB_Data_Write_27(17) <= \<const0>\;
  LMB_Data_Write_27(18) <= \<const0>\;
  LMB_Data_Write_27(19) <= \<const0>\;
  LMB_Data_Write_27(20) <= \<const0>\;
  LMB_Data_Write_27(21) <= \<const0>\;
  LMB_Data_Write_27(22) <= \<const0>\;
  LMB_Data_Write_27(23) <= \<const0>\;
  LMB_Data_Write_27(24) <= \<const0>\;
  LMB_Data_Write_27(25) <= \<const0>\;
  LMB_Data_Write_27(26) <= \<const0>\;
  LMB_Data_Write_27(27) <= \<const0>\;
  LMB_Data_Write_27(28) <= \<const0>\;
  LMB_Data_Write_27(29) <= \<const0>\;
  LMB_Data_Write_27(30) <= \<const0>\;
  LMB_Data_Write_27(31) <= \<const0>\;
  LMB_Data_Write_28(0) <= \<const0>\;
  LMB_Data_Write_28(1) <= \<const0>\;
  LMB_Data_Write_28(2) <= \<const0>\;
  LMB_Data_Write_28(3) <= \<const0>\;
  LMB_Data_Write_28(4) <= \<const0>\;
  LMB_Data_Write_28(5) <= \<const0>\;
  LMB_Data_Write_28(6) <= \<const0>\;
  LMB_Data_Write_28(7) <= \<const0>\;
  LMB_Data_Write_28(8) <= \<const0>\;
  LMB_Data_Write_28(9) <= \<const0>\;
  LMB_Data_Write_28(10) <= \<const0>\;
  LMB_Data_Write_28(11) <= \<const0>\;
  LMB_Data_Write_28(12) <= \<const0>\;
  LMB_Data_Write_28(13) <= \<const0>\;
  LMB_Data_Write_28(14) <= \<const0>\;
  LMB_Data_Write_28(15) <= \<const0>\;
  LMB_Data_Write_28(16) <= \<const0>\;
  LMB_Data_Write_28(17) <= \<const0>\;
  LMB_Data_Write_28(18) <= \<const0>\;
  LMB_Data_Write_28(19) <= \<const0>\;
  LMB_Data_Write_28(20) <= \<const0>\;
  LMB_Data_Write_28(21) <= \<const0>\;
  LMB_Data_Write_28(22) <= \<const0>\;
  LMB_Data_Write_28(23) <= \<const0>\;
  LMB_Data_Write_28(24) <= \<const0>\;
  LMB_Data_Write_28(25) <= \<const0>\;
  LMB_Data_Write_28(26) <= \<const0>\;
  LMB_Data_Write_28(27) <= \<const0>\;
  LMB_Data_Write_28(28) <= \<const0>\;
  LMB_Data_Write_28(29) <= \<const0>\;
  LMB_Data_Write_28(30) <= \<const0>\;
  LMB_Data_Write_28(31) <= \<const0>\;
  LMB_Data_Write_29(0) <= \<const0>\;
  LMB_Data_Write_29(1) <= \<const0>\;
  LMB_Data_Write_29(2) <= \<const0>\;
  LMB_Data_Write_29(3) <= \<const0>\;
  LMB_Data_Write_29(4) <= \<const0>\;
  LMB_Data_Write_29(5) <= \<const0>\;
  LMB_Data_Write_29(6) <= \<const0>\;
  LMB_Data_Write_29(7) <= \<const0>\;
  LMB_Data_Write_29(8) <= \<const0>\;
  LMB_Data_Write_29(9) <= \<const0>\;
  LMB_Data_Write_29(10) <= \<const0>\;
  LMB_Data_Write_29(11) <= \<const0>\;
  LMB_Data_Write_29(12) <= \<const0>\;
  LMB_Data_Write_29(13) <= \<const0>\;
  LMB_Data_Write_29(14) <= \<const0>\;
  LMB_Data_Write_29(15) <= \<const0>\;
  LMB_Data_Write_29(16) <= \<const0>\;
  LMB_Data_Write_29(17) <= \<const0>\;
  LMB_Data_Write_29(18) <= \<const0>\;
  LMB_Data_Write_29(19) <= \<const0>\;
  LMB_Data_Write_29(20) <= \<const0>\;
  LMB_Data_Write_29(21) <= \<const0>\;
  LMB_Data_Write_29(22) <= \<const0>\;
  LMB_Data_Write_29(23) <= \<const0>\;
  LMB_Data_Write_29(24) <= \<const0>\;
  LMB_Data_Write_29(25) <= \<const0>\;
  LMB_Data_Write_29(26) <= \<const0>\;
  LMB_Data_Write_29(27) <= \<const0>\;
  LMB_Data_Write_29(28) <= \<const0>\;
  LMB_Data_Write_29(29) <= \<const0>\;
  LMB_Data_Write_29(30) <= \<const0>\;
  LMB_Data_Write_29(31) <= \<const0>\;
  LMB_Data_Write_3(0) <= \<const0>\;
  LMB_Data_Write_3(1) <= \<const0>\;
  LMB_Data_Write_3(2) <= \<const0>\;
  LMB_Data_Write_3(3) <= \<const0>\;
  LMB_Data_Write_3(4) <= \<const0>\;
  LMB_Data_Write_3(5) <= \<const0>\;
  LMB_Data_Write_3(6) <= \<const0>\;
  LMB_Data_Write_3(7) <= \<const0>\;
  LMB_Data_Write_3(8) <= \<const0>\;
  LMB_Data_Write_3(9) <= \<const0>\;
  LMB_Data_Write_3(10) <= \<const0>\;
  LMB_Data_Write_3(11) <= \<const0>\;
  LMB_Data_Write_3(12) <= \<const0>\;
  LMB_Data_Write_3(13) <= \<const0>\;
  LMB_Data_Write_3(14) <= \<const0>\;
  LMB_Data_Write_3(15) <= \<const0>\;
  LMB_Data_Write_3(16) <= \<const0>\;
  LMB_Data_Write_3(17) <= \<const0>\;
  LMB_Data_Write_3(18) <= \<const0>\;
  LMB_Data_Write_3(19) <= \<const0>\;
  LMB_Data_Write_3(20) <= \<const0>\;
  LMB_Data_Write_3(21) <= \<const0>\;
  LMB_Data_Write_3(22) <= \<const0>\;
  LMB_Data_Write_3(23) <= \<const0>\;
  LMB_Data_Write_3(24) <= \<const0>\;
  LMB_Data_Write_3(25) <= \<const0>\;
  LMB_Data_Write_3(26) <= \<const0>\;
  LMB_Data_Write_3(27) <= \<const0>\;
  LMB_Data_Write_3(28) <= \<const0>\;
  LMB_Data_Write_3(29) <= \<const0>\;
  LMB_Data_Write_3(30) <= \<const0>\;
  LMB_Data_Write_3(31) <= \<const0>\;
  LMB_Data_Write_30(0) <= \<const0>\;
  LMB_Data_Write_30(1) <= \<const0>\;
  LMB_Data_Write_30(2) <= \<const0>\;
  LMB_Data_Write_30(3) <= \<const0>\;
  LMB_Data_Write_30(4) <= \<const0>\;
  LMB_Data_Write_30(5) <= \<const0>\;
  LMB_Data_Write_30(6) <= \<const0>\;
  LMB_Data_Write_30(7) <= \<const0>\;
  LMB_Data_Write_30(8) <= \<const0>\;
  LMB_Data_Write_30(9) <= \<const0>\;
  LMB_Data_Write_30(10) <= \<const0>\;
  LMB_Data_Write_30(11) <= \<const0>\;
  LMB_Data_Write_30(12) <= \<const0>\;
  LMB_Data_Write_30(13) <= \<const0>\;
  LMB_Data_Write_30(14) <= \<const0>\;
  LMB_Data_Write_30(15) <= \<const0>\;
  LMB_Data_Write_30(16) <= \<const0>\;
  LMB_Data_Write_30(17) <= \<const0>\;
  LMB_Data_Write_30(18) <= \<const0>\;
  LMB_Data_Write_30(19) <= \<const0>\;
  LMB_Data_Write_30(20) <= \<const0>\;
  LMB_Data_Write_30(21) <= \<const0>\;
  LMB_Data_Write_30(22) <= \<const0>\;
  LMB_Data_Write_30(23) <= \<const0>\;
  LMB_Data_Write_30(24) <= \<const0>\;
  LMB_Data_Write_30(25) <= \<const0>\;
  LMB_Data_Write_30(26) <= \<const0>\;
  LMB_Data_Write_30(27) <= \<const0>\;
  LMB_Data_Write_30(28) <= \<const0>\;
  LMB_Data_Write_30(29) <= \<const0>\;
  LMB_Data_Write_30(30) <= \<const0>\;
  LMB_Data_Write_30(31) <= \<const0>\;
  LMB_Data_Write_31(0) <= \<const0>\;
  LMB_Data_Write_31(1) <= \<const0>\;
  LMB_Data_Write_31(2) <= \<const0>\;
  LMB_Data_Write_31(3) <= \<const0>\;
  LMB_Data_Write_31(4) <= \<const0>\;
  LMB_Data_Write_31(5) <= \<const0>\;
  LMB_Data_Write_31(6) <= \<const0>\;
  LMB_Data_Write_31(7) <= \<const0>\;
  LMB_Data_Write_31(8) <= \<const0>\;
  LMB_Data_Write_31(9) <= \<const0>\;
  LMB_Data_Write_31(10) <= \<const0>\;
  LMB_Data_Write_31(11) <= \<const0>\;
  LMB_Data_Write_31(12) <= \<const0>\;
  LMB_Data_Write_31(13) <= \<const0>\;
  LMB_Data_Write_31(14) <= \<const0>\;
  LMB_Data_Write_31(15) <= \<const0>\;
  LMB_Data_Write_31(16) <= \<const0>\;
  LMB_Data_Write_31(17) <= \<const0>\;
  LMB_Data_Write_31(18) <= \<const0>\;
  LMB_Data_Write_31(19) <= \<const0>\;
  LMB_Data_Write_31(20) <= \<const0>\;
  LMB_Data_Write_31(21) <= \<const0>\;
  LMB_Data_Write_31(22) <= \<const0>\;
  LMB_Data_Write_31(23) <= \<const0>\;
  LMB_Data_Write_31(24) <= \<const0>\;
  LMB_Data_Write_31(25) <= \<const0>\;
  LMB_Data_Write_31(26) <= \<const0>\;
  LMB_Data_Write_31(27) <= \<const0>\;
  LMB_Data_Write_31(28) <= \<const0>\;
  LMB_Data_Write_31(29) <= \<const0>\;
  LMB_Data_Write_31(30) <= \<const0>\;
  LMB_Data_Write_31(31) <= \<const0>\;
  LMB_Data_Write_4(0) <= \<const0>\;
  LMB_Data_Write_4(1) <= \<const0>\;
  LMB_Data_Write_4(2) <= \<const0>\;
  LMB_Data_Write_4(3) <= \<const0>\;
  LMB_Data_Write_4(4) <= \<const0>\;
  LMB_Data_Write_4(5) <= \<const0>\;
  LMB_Data_Write_4(6) <= \<const0>\;
  LMB_Data_Write_4(7) <= \<const0>\;
  LMB_Data_Write_4(8) <= \<const0>\;
  LMB_Data_Write_4(9) <= \<const0>\;
  LMB_Data_Write_4(10) <= \<const0>\;
  LMB_Data_Write_4(11) <= \<const0>\;
  LMB_Data_Write_4(12) <= \<const0>\;
  LMB_Data_Write_4(13) <= \<const0>\;
  LMB_Data_Write_4(14) <= \<const0>\;
  LMB_Data_Write_4(15) <= \<const0>\;
  LMB_Data_Write_4(16) <= \<const0>\;
  LMB_Data_Write_4(17) <= \<const0>\;
  LMB_Data_Write_4(18) <= \<const0>\;
  LMB_Data_Write_4(19) <= \<const0>\;
  LMB_Data_Write_4(20) <= \<const0>\;
  LMB_Data_Write_4(21) <= \<const0>\;
  LMB_Data_Write_4(22) <= \<const0>\;
  LMB_Data_Write_4(23) <= \<const0>\;
  LMB_Data_Write_4(24) <= \<const0>\;
  LMB_Data_Write_4(25) <= \<const0>\;
  LMB_Data_Write_4(26) <= \<const0>\;
  LMB_Data_Write_4(27) <= \<const0>\;
  LMB_Data_Write_4(28) <= \<const0>\;
  LMB_Data_Write_4(29) <= \<const0>\;
  LMB_Data_Write_4(30) <= \<const0>\;
  LMB_Data_Write_4(31) <= \<const0>\;
  LMB_Data_Write_5(0) <= \<const0>\;
  LMB_Data_Write_5(1) <= \<const0>\;
  LMB_Data_Write_5(2) <= \<const0>\;
  LMB_Data_Write_5(3) <= \<const0>\;
  LMB_Data_Write_5(4) <= \<const0>\;
  LMB_Data_Write_5(5) <= \<const0>\;
  LMB_Data_Write_5(6) <= \<const0>\;
  LMB_Data_Write_5(7) <= \<const0>\;
  LMB_Data_Write_5(8) <= \<const0>\;
  LMB_Data_Write_5(9) <= \<const0>\;
  LMB_Data_Write_5(10) <= \<const0>\;
  LMB_Data_Write_5(11) <= \<const0>\;
  LMB_Data_Write_5(12) <= \<const0>\;
  LMB_Data_Write_5(13) <= \<const0>\;
  LMB_Data_Write_5(14) <= \<const0>\;
  LMB_Data_Write_5(15) <= \<const0>\;
  LMB_Data_Write_5(16) <= \<const0>\;
  LMB_Data_Write_5(17) <= \<const0>\;
  LMB_Data_Write_5(18) <= \<const0>\;
  LMB_Data_Write_5(19) <= \<const0>\;
  LMB_Data_Write_5(20) <= \<const0>\;
  LMB_Data_Write_5(21) <= \<const0>\;
  LMB_Data_Write_5(22) <= \<const0>\;
  LMB_Data_Write_5(23) <= \<const0>\;
  LMB_Data_Write_5(24) <= \<const0>\;
  LMB_Data_Write_5(25) <= \<const0>\;
  LMB_Data_Write_5(26) <= \<const0>\;
  LMB_Data_Write_5(27) <= \<const0>\;
  LMB_Data_Write_5(28) <= \<const0>\;
  LMB_Data_Write_5(29) <= \<const0>\;
  LMB_Data_Write_5(30) <= \<const0>\;
  LMB_Data_Write_5(31) <= \<const0>\;
  LMB_Data_Write_6(0) <= \<const0>\;
  LMB_Data_Write_6(1) <= \<const0>\;
  LMB_Data_Write_6(2) <= \<const0>\;
  LMB_Data_Write_6(3) <= \<const0>\;
  LMB_Data_Write_6(4) <= \<const0>\;
  LMB_Data_Write_6(5) <= \<const0>\;
  LMB_Data_Write_6(6) <= \<const0>\;
  LMB_Data_Write_6(7) <= \<const0>\;
  LMB_Data_Write_6(8) <= \<const0>\;
  LMB_Data_Write_6(9) <= \<const0>\;
  LMB_Data_Write_6(10) <= \<const0>\;
  LMB_Data_Write_6(11) <= \<const0>\;
  LMB_Data_Write_6(12) <= \<const0>\;
  LMB_Data_Write_6(13) <= \<const0>\;
  LMB_Data_Write_6(14) <= \<const0>\;
  LMB_Data_Write_6(15) <= \<const0>\;
  LMB_Data_Write_6(16) <= \<const0>\;
  LMB_Data_Write_6(17) <= \<const0>\;
  LMB_Data_Write_6(18) <= \<const0>\;
  LMB_Data_Write_6(19) <= \<const0>\;
  LMB_Data_Write_6(20) <= \<const0>\;
  LMB_Data_Write_6(21) <= \<const0>\;
  LMB_Data_Write_6(22) <= \<const0>\;
  LMB_Data_Write_6(23) <= \<const0>\;
  LMB_Data_Write_6(24) <= \<const0>\;
  LMB_Data_Write_6(25) <= \<const0>\;
  LMB_Data_Write_6(26) <= \<const0>\;
  LMB_Data_Write_6(27) <= \<const0>\;
  LMB_Data_Write_6(28) <= \<const0>\;
  LMB_Data_Write_6(29) <= \<const0>\;
  LMB_Data_Write_6(30) <= \<const0>\;
  LMB_Data_Write_6(31) <= \<const0>\;
  LMB_Data_Write_7(0) <= \<const0>\;
  LMB_Data_Write_7(1) <= \<const0>\;
  LMB_Data_Write_7(2) <= \<const0>\;
  LMB_Data_Write_7(3) <= \<const0>\;
  LMB_Data_Write_7(4) <= \<const0>\;
  LMB_Data_Write_7(5) <= \<const0>\;
  LMB_Data_Write_7(6) <= \<const0>\;
  LMB_Data_Write_7(7) <= \<const0>\;
  LMB_Data_Write_7(8) <= \<const0>\;
  LMB_Data_Write_7(9) <= \<const0>\;
  LMB_Data_Write_7(10) <= \<const0>\;
  LMB_Data_Write_7(11) <= \<const0>\;
  LMB_Data_Write_7(12) <= \<const0>\;
  LMB_Data_Write_7(13) <= \<const0>\;
  LMB_Data_Write_7(14) <= \<const0>\;
  LMB_Data_Write_7(15) <= \<const0>\;
  LMB_Data_Write_7(16) <= \<const0>\;
  LMB_Data_Write_7(17) <= \<const0>\;
  LMB_Data_Write_7(18) <= \<const0>\;
  LMB_Data_Write_7(19) <= \<const0>\;
  LMB_Data_Write_7(20) <= \<const0>\;
  LMB_Data_Write_7(21) <= \<const0>\;
  LMB_Data_Write_7(22) <= \<const0>\;
  LMB_Data_Write_7(23) <= \<const0>\;
  LMB_Data_Write_7(24) <= \<const0>\;
  LMB_Data_Write_7(25) <= \<const0>\;
  LMB_Data_Write_7(26) <= \<const0>\;
  LMB_Data_Write_7(27) <= \<const0>\;
  LMB_Data_Write_7(28) <= \<const0>\;
  LMB_Data_Write_7(29) <= \<const0>\;
  LMB_Data_Write_7(30) <= \<const0>\;
  LMB_Data_Write_7(31) <= \<const0>\;
  LMB_Data_Write_8(0) <= \<const0>\;
  LMB_Data_Write_8(1) <= \<const0>\;
  LMB_Data_Write_8(2) <= \<const0>\;
  LMB_Data_Write_8(3) <= \<const0>\;
  LMB_Data_Write_8(4) <= \<const0>\;
  LMB_Data_Write_8(5) <= \<const0>\;
  LMB_Data_Write_8(6) <= \<const0>\;
  LMB_Data_Write_8(7) <= \<const0>\;
  LMB_Data_Write_8(8) <= \<const0>\;
  LMB_Data_Write_8(9) <= \<const0>\;
  LMB_Data_Write_8(10) <= \<const0>\;
  LMB_Data_Write_8(11) <= \<const0>\;
  LMB_Data_Write_8(12) <= \<const0>\;
  LMB_Data_Write_8(13) <= \<const0>\;
  LMB_Data_Write_8(14) <= \<const0>\;
  LMB_Data_Write_8(15) <= \<const0>\;
  LMB_Data_Write_8(16) <= \<const0>\;
  LMB_Data_Write_8(17) <= \<const0>\;
  LMB_Data_Write_8(18) <= \<const0>\;
  LMB_Data_Write_8(19) <= \<const0>\;
  LMB_Data_Write_8(20) <= \<const0>\;
  LMB_Data_Write_8(21) <= \<const0>\;
  LMB_Data_Write_8(22) <= \<const0>\;
  LMB_Data_Write_8(23) <= \<const0>\;
  LMB_Data_Write_8(24) <= \<const0>\;
  LMB_Data_Write_8(25) <= \<const0>\;
  LMB_Data_Write_8(26) <= \<const0>\;
  LMB_Data_Write_8(27) <= \<const0>\;
  LMB_Data_Write_8(28) <= \<const0>\;
  LMB_Data_Write_8(29) <= \<const0>\;
  LMB_Data_Write_8(30) <= \<const0>\;
  LMB_Data_Write_8(31) <= \<const0>\;
  LMB_Data_Write_9(0) <= \<const0>\;
  LMB_Data_Write_9(1) <= \<const0>\;
  LMB_Data_Write_9(2) <= \<const0>\;
  LMB_Data_Write_9(3) <= \<const0>\;
  LMB_Data_Write_9(4) <= \<const0>\;
  LMB_Data_Write_9(5) <= \<const0>\;
  LMB_Data_Write_9(6) <= \<const0>\;
  LMB_Data_Write_9(7) <= \<const0>\;
  LMB_Data_Write_9(8) <= \<const0>\;
  LMB_Data_Write_9(9) <= \<const0>\;
  LMB_Data_Write_9(10) <= \<const0>\;
  LMB_Data_Write_9(11) <= \<const0>\;
  LMB_Data_Write_9(12) <= \<const0>\;
  LMB_Data_Write_9(13) <= \<const0>\;
  LMB_Data_Write_9(14) <= \<const0>\;
  LMB_Data_Write_9(15) <= \<const0>\;
  LMB_Data_Write_9(16) <= \<const0>\;
  LMB_Data_Write_9(17) <= \<const0>\;
  LMB_Data_Write_9(18) <= \<const0>\;
  LMB_Data_Write_9(19) <= \<const0>\;
  LMB_Data_Write_9(20) <= \<const0>\;
  LMB_Data_Write_9(21) <= \<const0>\;
  LMB_Data_Write_9(22) <= \<const0>\;
  LMB_Data_Write_9(23) <= \<const0>\;
  LMB_Data_Write_9(24) <= \<const0>\;
  LMB_Data_Write_9(25) <= \<const0>\;
  LMB_Data_Write_9(26) <= \<const0>\;
  LMB_Data_Write_9(27) <= \<const0>\;
  LMB_Data_Write_9(28) <= \<const0>\;
  LMB_Data_Write_9(29) <= \<const0>\;
  LMB_Data_Write_9(30) <= \<const0>\;
  LMB_Data_Write_9(31) <= \<const0>\;
  LMB_Read_Strobe_0 <= \<const0>\;
  LMB_Read_Strobe_1 <= \<const0>\;
  LMB_Read_Strobe_10 <= \<const0>\;
  LMB_Read_Strobe_11 <= \<const0>\;
  LMB_Read_Strobe_12 <= \<const0>\;
  LMB_Read_Strobe_13 <= \<const0>\;
  LMB_Read_Strobe_14 <= \<const0>\;
  LMB_Read_Strobe_15 <= \<const0>\;
  LMB_Read_Strobe_16 <= \<const0>\;
  LMB_Read_Strobe_17 <= \<const0>\;
  LMB_Read_Strobe_18 <= \<const0>\;
  LMB_Read_Strobe_19 <= \<const0>\;
  LMB_Read_Strobe_2 <= \<const0>\;
  LMB_Read_Strobe_20 <= \<const0>\;
  LMB_Read_Strobe_21 <= \<const0>\;
  LMB_Read_Strobe_22 <= \<const0>\;
  LMB_Read_Strobe_23 <= \<const0>\;
  LMB_Read_Strobe_24 <= \<const0>\;
  LMB_Read_Strobe_25 <= \<const0>\;
  LMB_Read_Strobe_26 <= \<const0>\;
  LMB_Read_Strobe_27 <= \<const0>\;
  LMB_Read_Strobe_28 <= \<const0>\;
  LMB_Read_Strobe_29 <= \<const0>\;
  LMB_Read_Strobe_3 <= \<const0>\;
  LMB_Read_Strobe_30 <= \<const0>\;
  LMB_Read_Strobe_31 <= \<const0>\;
  LMB_Read_Strobe_4 <= \<const0>\;
  LMB_Read_Strobe_5 <= \<const0>\;
  LMB_Read_Strobe_6 <= \<const0>\;
  LMB_Read_Strobe_7 <= \<const0>\;
  LMB_Read_Strobe_8 <= \<const0>\;
  LMB_Read_Strobe_9 <= \<const0>\;
  LMB_Write_Strobe_0 <= \<const0>\;
  LMB_Write_Strobe_1 <= \<const0>\;
  LMB_Write_Strobe_10 <= \<const0>\;
  LMB_Write_Strobe_11 <= \<const0>\;
  LMB_Write_Strobe_12 <= \<const0>\;
  LMB_Write_Strobe_13 <= \<const0>\;
  LMB_Write_Strobe_14 <= \<const0>\;
  LMB_Write_Strobe_15 <= \<const0>\;
  LMB_Write_Strobe_16 <= \<const0>\;
  LMB_Write_Strobe_17 <= \<const0>\;
  LMB_Write_Strobe_18 <= \<const0>\;
  LMB_Write_Strobe_19 <= \<const0>\;
  LMB_Write_Strobe_2 <= \<const0>\;
  LMB_Write_Strobe_20 <= \<const0>\;
  LMB_Write_Strobe_21 <= \<const0>\;
  LMB_Write_Strobe_22 <= \<const0>\;
  LMB_Write_Strobe_23 <= \<const0>\;
  LMB_Write_Strobe_24 <= \<const0>\;
  LMB_Write_Strobe_25 <= \<const0>\;
  LMB_Write_Strobe_26 <= \<const0>\;
  LMB_Write_Strobe_27 <= \<const0>\;
  LMB_Write_Strobe_28 <= \<const0>\;
  LMB_Write_Strobe_29 <= \<const0>\;
  LMB_Write_Strobe_3 <= \<const0>\;
  LMB_Write_Strobe_30 <= \<const0>\;
  LMB_Write_Strobe_31 <= \<const0>\;
  LMB_Write_Strobe_4 <= \<const0>\;
  LMB_Write_Strobe_5 <= \<const0>\;
  LMB_Write_Strobe_6 <= \<const0>\;
  LMB_Write_Strobe_7 <= \<const0>\;
  LMB_Write_Strobe_8 <= \<const0>\;
  LMB_Write_Strobe_9 <= \<const0>\;
  M_AXIS_TDATA(31) <= \<const0>\;
  M_AXIS_TDATA(30) <= \<const0>\;
  M_AXIS_TDATA(29) <= \<const0>\;
  M_AXIS_TDATA(28) <= \<const0>\;
  M_AXIS_TDATA(27) <= \<const0>\;
  M_AXIS_TDATA(26) <= \<const0>\;
  M_AXIS_TDATA(25) <= \<const0>\;
  M_AXIS_TDATA(24) <= \<const0>\;
  M_AXIS_TDATA(23) <= \<const0>\;
  M_AXIS_TDATA(22) <= \<const0>\;
  M_AXIS_TDATA(21) <= \<const0>\;
  M_AXIS_TDATA(20) <= \<const0>\;
  M_AXIS_TDATA(19) <= \<const0>\;
  M_AXIS_TDATA(18) <= \<const0>\;
  M_AXIS_TDATA(17) <= \<const0>\;
  M_AXIS_TDATA(16) <= \<const0>\;
  M_AXIS_TDATA(15) <= \<const0>\;
  M_AXIS_TDATA(14) <= \<const0>\;
  M_AXIS_TDATA(13) <= \<const0>\;
  M_AXIS_TDATA(12) <= \<const0>\;
  M_AXIS_TDATA(11) <= \<const0>\;
  M_AXIS_TDATA(10) <= \<const0>\;
  M_AXIS_TDATA(9) <= \<const0>\;
  M_AXIS_TDATA(8) <= \<const0>\;
  M_AXIS_TDATA(7) <= \<const0>\;
  M_AXIS_TDATA(6) <= \<const0>\;
  M_AXIS_TDATA(5) <= \<const0>\;
  M_AXIS_TDATA(4) <= \<const0>\;
  M_AXIS_TDATA(3) <= \<const0>\;
  M_AXIS_TDATA(2) <= \<const0>\;
  M_AXIS_TDATA(1) <= \<const0>\;
  M_AXIS_TDATA(0) <= \<const0>\;
  M_AXIS_TID(6) <= \<const0>\;
  M_AXIS_TID(5) <= \<const0>\;
  M_AXIS_TID(4) <= \<const0>\;
  M_AXIS_TID(3) <= \<const0>\;
  M_AXIS_TID(2) <= \<const0>\;
  M_AXIS_TID(1) <= \<const0>\;
  M_AXIS_TID(0) <= \<const0>\;
  M_AXIS_TVALID <= \<const0>\;
  M_AXI_ARADDR(31) <= \<const0>\;
  M_AXI_ARADDR(30) <= \<const0>\;
  M_AXI_ARADDR(29) <= \<const0>\;
  M_AXI_ARADDR(28) <= \<const0>\;
  M_AXI_ARADDR(27) <= \<const0>\;
  M_AXI_ARADDR(26) <= \<const0>\;
  M_AXI_ARADDR(25) <= \<const0>\;
  M_AXI_ARADDR(24) <= \<const0>\;
  M_AXI_ARADDR(23) <= \<const0>\;
  M_AXI_ARADDR(22) <= \<const0>\;
  M_AXI_ARADDR(21) <= \<const0>\;
  M_AXI_ARADDR(20) <= \<const0>\;
  M_AXI_ARADDR(19) <= \<const0>\;
  M_AXI_ARADDR(18) <= \<const0>\;
  M_AXI_ARADDR(17) <= \<const0>\;
  M_AXI_ARADDR(16) <= \<const0>\;
  M_AXI_ARADDR(15) <= \<const0>\;
  M_AXI_ARADDR(14) <= \<const0>\;
  M_AXI_ARADDR(13) <= \<const0>\;
  M_AXI_ARADDR(12) <= \<const0>\;
  M_AXI_ARADDR(11) <= \<const0>\;
  M_AXI_ARADDR(10) <= \<const0>\;
  M_AXI_ARADDR(9) <= \<const0>\;
  M_AXI_ARADDR(8) <= \<const0>\;
  M_AXI_ARADDR(7) <= \<const0>\;
  M_AXI_ARADDR(6) <= \<const0>\;
  M_AXI_ARADDR(5) <= \<const0>\;
  M_AXI_ARADDR(4) <= \<const0>\;
  M_AXI_ARADDR(3) <= \<const0>\;
  M_AXI_ARADDR(2) <= \<const0>\;
  M_AXI_ARADDR(1) <= \<const0>\;
  M_AXI_ARADDR(0) <= \<const0>\;
  M_AXI_ARBURST(1) <= \<const0>\;
  M_AXI_ARBURST(0) <= \<const0>\;
  M_AXI_ARCACHE(3) <= \<const0>\;
  M_AXI_ARCACHE(2) <= \<const0>\;
  M_AXI_ARCACHE(1) <= \<const0>\;
  M_AXI_ARCACHE(0) <= \<const0>\;
  M_AXI_ARID(0) <= \<const0>\;
  M_AXI_ARLEN(7) <= \<const0>\;
  M_AXI_ARLEN(6) <= \<const0>\;
  M_AXI_ARLEN(5) <= \<const0>\;
  M_AXI_ARLEN(4) <= \<const0>\;
  M_AXI_ARLEN(3) <= \<const0>\;
  M_AXI_ARLEN(2) <= \<const0>\;
  M_AXI_ARLEN(1) <= \<const0>\;
  M_AXI_ARLEN(0) <= \<const0>\;
  M_AXI_ARLOCK <= \<const0>\;
  M_AXI_ARPROT(2) <= \<const0>\;
  M_AXI_ARPROT(1) <= \<const0>\;
  M_AXI_ARPROT(0) <= \<const0>\;
  M_AXI_ARQOS(3) <= \<const0>\;
  M_AXI_ARQOS(2) <= \<const0>\;
  M_AXI_ARQOS(1) <= \<const0>\;
  M_AXI_ARQOS(0) <= \<const0>\;
  M_AXI_ARSIZE(2) <= \<const0>\;
  M_AXI_ARSIZE(1) <= \<const0>\;
  M_AXI_ARSIZE(0) <= \<const0>\;
  M_AXI_ARVALID <= \<const0>\;
  M_AXI_AWADDR(31) <= \<const0>\;
  M_AXI_AWADDR(30) <= \<const0>\;
  M_AXI_AWADDR(29) <= \<const0>\;
  M_AXI_AWADDR(28) <= \<const0>\;
  M_AXI_AWADDR(27) <= \<const0>\;
  M_AXI_AWADDR(26) <= \<const0>\;
  M_AXI_AWADDR(25) <= \<const0>\;
  M_AXI_AWADDR(24) <= \<const0>\;
  M_AXI_AWADDR(23) <= \<const0>\;
  M_AXI_AWADDR(22) <= \<const0>\;
  M_AXI_AWADDR(21) <= \<const0>\;
  M_AXI_AWADDR(20) <= \<const0>\;
  M_AXI_AWADDR(19) <= \<const0>\;
  M_AXI_AWADDR(18) <= \<const0>\;
  M_AXI_AWADDR(17) <= \<const0>\;
  M_AXI_AWADDR(16) <= \<const0>\;
  M_AXI_AWADDR(15) <= \<const0>\;
  M_AXI_AWADDR(14) <= \<const0>\;
  M_AXI_AWADDR(13) <= \<const0>\;
  M_AXI_AWADDR(12) <= \<const0>\;
  M_AXI_AWADDR(11) <= \<const0>\;
  M_AXI_AWADDR(10) <= \<const0>\;
  M_AXI_AWADDR(9) <= \<const0>\;
  M_AXI_AWADDR(8) <= \<const0>\;
  M_AXI_AWADDR(7) <= \<const0>\;
  M_AXI_AWADDR(6) <= \<const0>\;
  M_AXI_AWADDR(5) <= \<const0>\;
  M_AXI_AWADDR(4) <= \<const0>\;
  M_AXI_AWADDR(3) <= \<const0>\;
  M_AXI_AWADDR(2) <= \<const0>\;
  M_AXI_AWADDR(1) <= \<const0>\;
  M_AXI_AWADDR(0) <= \<const0>\;
  M_AXI_AWBURST(1) <= \<const0>\;
  M_AXI_AWBURST(0) <= \<const0>\;
  M_AXI_AWCACHE(3) <= \<const0>\;
  M_AXI_AWCACHE(2) <= \<const0>\;
  M_AXI_AWCACHE(1) <= \<const0>\;
  M_AXI_AWCACHE(0) <= \<const0>\;
  M_AXI_AWID(0) <= \<const0>\;
  M_AXI_AWLEN(7) <= \<const0>\;
  M_AXI_AWLEN(6) <= \<const0>\;
  M_AXI_AWLEN(5) <= \<const0>\;
  M_AXI_AWLEN(4) <= \<const0>\;
  M_AXI_AWLEN(3) <= \<const0>\;
  M_AXI_AWLEN(2) <= \<const0>\;
  M_AXI_AWLEN(1) <= \<const0>\;
  M_AXI_AWLEN(0) <= \<const0>\;
  M_AXI_AWLOCK <= \<const0>\;
  M_AXI_AWPROT(2) <= \<const0>\;
  M_AXI_AWPROT(1) <= \<const0>\;
  M_AXI_AWPROT(0) <= \<const0>\;
  M_AXI_AWQOS(3) <= \<const0>\;
  M_AXI_AWQOS(2) <= \<const0>\;
  M_AXI_AWQOS(1) <= \<const0>\;
  M_AXI_AWQOS(0) <= \<const0>\;
  M_AXI_AWSIZE(2) <= \<const0>\;
  M_AXI_AWSIZE(1) <= \<const0>\;
  M_AXI_AWSIZE(0) <= \<const0>\;
  M_AXI_AWVALID <= \<const0>\;
  M_AXI_BREADY <= \<const0>\;
  M_AXI_RREADY <= \<const0>\;
  M_AXI_WDATA(31) <= \<const0>\;
  M_AXI_WDATA(30) <= \<const0>\;
  M_AXI_WDATA(29) <= \<const0>\;
  M_AXI_WDATA(28) <= \<const0>\;
  M_AXI_WDATA(27) <= \<const0>\;
  M_AXI_WDATA(26) <= \<const0>\;
  M_AXI_WDATA(25) <= \<const0>\;
  M_AXI_WDATA(24) <= \<const0>\;
  M_AXI_WDATA(23) <= \<const0>\;
  M_AXI_WDATA(22) <= \<const0>\;
  M_AXI_WDATA(21) <= \<const0>\;
  M_AXI_WDATA(20) <= \<const0>\;
  M_AXI_WDATA(19) <= \<const0>\;
  M_AXI_WDATA(18) <= \<const0>\;
  M_AXI_WDATA(17) <= \<const0>\;
  M_AXI_WDATA(16) <= \<const0>\;
  M_AXI_WDATA(15) <= \<const0>\;
  M_AXI_WDATA(14) <= \<const0>\;
  M_AXI_WDATA(13) <= \<const0>\;
  M_AXI_WDATA(12) <= \<const0>\;
  M_AXI_WDATA(11) <= \<const0>\;
  M_AXI_WDATA(10) <= \<const0>\;
  M_AXI_WDATA(9) <= \<const0>\;
  M_AXI_WDATA(8) <= \<const0>\;
  M_AXI_WDATA(7) <= \<const0>\;
  M_AXI_WDATA(6) <= \<const0>\;
  M_AXI_WDATA(5) <= \<const0>\;
  M_AXI_WDATA(4) <= \<const0>\;
  M_AXI_WDATA(3) <= \<const0>\;
  M_AXI_WDATA(2) <= \<const0>\;
  M_AXI_WDATA(1) <= \<const0>\;
  M_AXI_WDATA(0) <= \<const0>\;
  M_AXI_WLAST <= \<const0>\;
  M_AXI_WSTRB(3) <= \<const0>\;
  M_AXI_WSTRB(2) <= \<const0>\;
  M_AXI_WSTRB(1) <= \<const0>\;
  M_AXI_WSTRB(0) <= \<const0>\;
  M_AXI_WVALID <= \<const0>\;
  S_AXI_ARREADY <= \<const0>\;
  S_AXI_AWREADY <= \<const0>\;
  S_AXI_BRESP(1) <= \<const0>\;
  S_AXI_BRESP(0) <= \<const0>\;
  S_AXI_BVALID <= \<const0>\;
  S_AXI_RDATA(31) <= \<const0>\;
  S_AXI_RDATA(30) <= \<const0>\;
  S_AXI_RDATA(29) <= \<const0>\;
  S_AXI_RDATA(28) <= \<const0>\;
  S_AXI_RDATA(27) <= \<const0>\;
  S_AXI_RDATA(26) <= \<const0>\;
  S_AXI_RDATA(25) <= \<const0>\;
  S_AXI_RDATA(24) <= \<const0>\;
  S_AXI_RDATA(23) <= \<const0>\;
  S_AXI_RDATA(22) <= \<const0>\;
  S_AXI_RDATA(21) <= \<const0>\;
  S_AXI_RDATA(20) <= \<const0>\;
  S_AXI_RDATA(19) <= \<const0>\;
  S_AXI_RDATA(18) <= \<const0>\;
  S_AXI_RDATA(17) <= \<const0>\;
  S_AXI_RDATA(16) <= \<const0>\;
  S_AXI_RDATA(15) <= \<const0>\;
  S_AXI_RDATA(14) <= \<const0>\;
  S_AXI_RDATA(13) <= \<const0>\;
  S_AXI_RDATA(12) <= \<const0>\;
  S_AXI_RDATA(11) <= \<const0>\;
  S_AXI_RDATA(10) <= \<const0>\;
  S_AXI_RDATA(9) <= \<const0>\;
  S_AXI_RDATA(8) <= \<const0>\;
  S_AXI_RDATA(7) <= \<const0>\;
  S_AXI_RDATA(6) <= \<const0>\;
  S_AXI_RDATA(5) <= \<const0>\;
  S_AXI_RDATA(4) <= \<const0>\;
  S_AXI_RDATA(3) <= \<const0>\;
  S_AXI_RDATA(2) <= \<const0>\;
  S_AXI_RDATA(1) <= \<const0>\;
  S_AXI_RDATA(0) <= \<const0>\;
  S_AXI_RRESP(1) <= \<const0>\;
  S_AXI_RRESP(0) <= \<const0>\;
  S_AXI_RVALID <= \<const0>\;
  S_AXI_WREADY <= \<const0>\;
  TRACE_CLK_OUT <= \<const0>\;
  TRACE_CTL <= \<const0>\;
  TRACE_DATA(31) <= \<const0>\;
  TRACE_DATA(30) <= \<const0>\;
  TRACE_DATA(29) <= \<const0>\;
  TRACE_DATA(28) <= \<const0>\;
  TRACE_DATA(27) <= \<const0>\;
  TRACE_DATA(26) <= \<const0>\;
  TRACE_DATA(25) <= \<const0>\;
  TRACE_DATA(24) <= \<const0>\;
  TRACE_DATA(23) <= \<const0>\;
  TRACE_DATA(22) <= \<const0>\;
  TRACE_DATA(21) <= \<const0>\;
  TRACE_DATA(20) <= \<const0>\;
  TRACE_DATA(19) <= \<const0>\;
  TRACE_DATA(18) <= \<const0>\;
  TRACE_DATA(17) <= \<const0>\;
  TRACE_DATA(16) <= \<const0>\;
  TRACE_DATA(15) <= \<const0>\;
  TRACE_DATA(14) <= \<const0>\;
  TRACE_DATA(13) <= \<const0>\;
  TRACE_DATA(12) <= \<const0>\;
  TRACE_DATA(11) <= \<const0>\;
  TRACE_DATA(10) <= \<const0>\;
  TRACE_DATA(9) <= \<const0>\;
  TRACE_DATA(8) <= \<const0>\;
  TRACE_DATA(7) <= \<const0>\;
  TRACE_DATA(6) <= \<const0>\;
  TRACE_DATA(5) <= \<const0>\;
  TRACE_DATA(4) <= \<const0>\;
  TRACE_DATA(3) <= \<const0>\;
  TRACE_DATA(2) <= \<const0>\;
  TRACE_DATA(1) <= \<const0>\;
  TRACE_DATA(0) <= \<const0>\;
  Trig_Ack_In_0 <= \<const0>\;
  Trig_Ack_In_1 <= \<const0>\;
  Trig_Ack_In_2 <= \<const0>\;
  Trig_Ack_In_3 <= \<const0>\;
  Trig_Out_0 <= \<const0>\;
  Trig_Out_1 <= \<const0>\;
  Trig_Out_2 <= \<const0>\;
  Trig_Out_3 <= \<const0>\;
  bscan_ext_tdo <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\Internal_BSCANID.bscanid_done_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      CLR => \Use_E2.BSCAN_I_n_0\,
      D => \Use_E2.BSCAN_I_n_14\,
      Q => \Internal_BSCANID.bscanid_done\
    );
\Internal_BSCANID.bscanid_sel_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      CLR => \Use_E2.BSCAN_I_n_0\,
      D => \Use_E2.BSCAN_I_n_12\,
      Q => \Internal_BSCANID.bscanid_sel\
    );
MDM_Core_I1: entity work.scu35_io_design_mdm_1_0_MDM_Core
     port map (
      Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
      Dbg_Rst_0 => Dbg_Rst_0,
      Dbg_TDO_0 => Dbg_TDO_0,
      \FSM_onehot_Test_Access_Port.state_reg[5]\ => MDM_Core_I1_n_7,
      JTAG_TDO => JTAG_TDO,
      O => \^dbg_tdi_0\,
      \Test_Access_Port.capture_dtm_reg\ => \^dbg_capture_0\,
      \Test_Access_Port.ir_reg[4]\(0) => \JTAG_CONTROL_I/Test_Access_Port.ir\(4),
      \Test_Access_Port.shift_dtm_reg\ => Dbg_Shift_0,
      \Use_JTAG_BSCAN.tck_int\ => \Use_JTAG_BSCAN.tck_int\,
      \Using_FPGA.Native\ => Dbg_Clk_0,
      \Using_FPGA.Native_0\ => Dbg_Update_0,
      dmcontrol_ndmreset_reg => Debug_SYS_Rst,
      \dtmcs_reg[31]\ => \Use_E2.LUT1_I_n_1\,
      jtag_tms => jtag_tms
    );
\Use_E2.BSCAN_I\: entity work.scu35_io_design_mdm_1_0_MB_BSCANE2
     port map (
      CO(0) => \Use_E2.BSCAN_I_n_5\,
      E(0) => \Use_JTAG_BSCAN.tap_cnt\(0),
      I0 => TDI,
      \Internal_BSCANID.bscanid_done\ => \Internal_BSCANID.bscanid_done\,
      \Internal_BSCANID.bscanid_done_reg\ => \Use_E2.BSCAN_I_n_12\,
      \Internal_BSCANID.bscanid_sel\ => \Internal_BSCANID.bscanid_sel\,
      \Internal_BSCANID.bscanid_sel_reg\ => \Use_E2.BSCAN_I_n_11\,
      JTAG_TDO => JTAG_TDO,
      O => \^dbg_tdi_0\,
      Q(0) => \Use_JTAG_BSCAN.bscanid\(0),
      SR(0) => \Use_JTAG_BSCAN.tms_ok\,
      \Use_E2.BSCANE2_I_0\ => \Use_E2.BSCAN_I_n_0\,
      \Use_E2.BSCANE2_I_1\ => \Use_E2.BSCAN_I_n_1\,
      \Use_E2.BSCANE2_I_2\ => \Use_E2.BSCAN_I_n_14\,
      \Use_JTAG_BSCAN.id_flag\ => \Use_JTAG_BSCAN.id_flag\,
      \Use_JTAG_BSCAN.id_flag_reg\ => \Use_E2.BSCAN_I_n_10\,
      \Use_JTAG_BSCAN.mode_reg__0\ => \Use_JTAG_BSCAN.mode_reg__0\,
      \Use_JTAG_BSCAN.mode_reg_reg\ => \Use_E2.BSCAN_I_n_4\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(7) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[7]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(6) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[6]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(5) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[5]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(4) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[4]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(3) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[3]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(2) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[2]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(1) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[1]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_0\(0) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[0]\,
      \Use_JTAG_BSCAN.mode_reg_reg_i_3_1\(7 downto 0) => \Use_JTAG_BSCAN.bit_cnt_reg\(7 downto 0),
      \Use_JTAG_BSCAN.tap_cnt_ok\ => \Use_JTAG_BSCAN.tap_cnt_ok\,
      \Use_JTAG_BSCAN.tap_cnt_ok_reg\ => \Use_E2.BSCAN_I_n_8\,
      \Use_JTAG_BSCAN.tap_cnt_ok_reg_0\(0) => \Use_JTAG_BSCAN.bit_cnt\(0),
      \Use_JTAG_BSCAN.tap_cnt_ok_reg_1\ => \Use_E2.BSCAN_I_n_13\,
      \Use_JTAG_BSCAN.tms_ok_reg\ => \Use_E2.LUT1_I_n_0\,
      \Use_JTAG_BSCAN.tms_ok_reg_0\ => \Use_JTAG_BSCAN.tms_ok_reg_n_0\,
      tck => tck
    );
\Use_E2.LUT1_I\: entity work.scu35_io_design_mdm_1_0_MB_LUT1
     port map (
      CO(0) => \Use_E2.BSCAN_I_n_5\,
      Dbg_Capture_0 => \^dbg_capture_0\,
      I0 => TDI,
      O => \^dbg_tdi_0\,
      Q(7 downto 0) => \Use_JTAG_BSCAN.bit_cnt_reg\(7 downto 0),
      \Test_Access_Port.ir_reg[4]\ => MDM_Core_I1_n_7,
      \Use_JTAG_BSCAN.bit_cnt_reg[2]\ => \Use_E2.LUT1_I_n_0\,
      \Use_JTAG_BSCAN.mode_reg__0\ => \Use_JTAG_BSCAN.mode_reg__0\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(7) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[7]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(6) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[6]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(5) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[5]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(4) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[4]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(3) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[3]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(2) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[2]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(1) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[1]\,
      \Use_JTAG_BSCAN.mode_reg_i_4_0\(0) => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[0]\,
      \Use_JTAG_BSCAN.mode_reg_reg\ => \Use_E2.BSCAN_I_n_1\,
      \Use_JTAG_BSCAN.tap_cnt_ok\ => \Use_JTAG_BSCAN.tap_cnt_ok\,
      \Use_JTAG_BSCAN.tms_reg_reg\ => \Use_JTAG_BSCAN.tms_ok_reg_n_0\,
      \Use_JTAG_BSCAN.tms_reg_reg_0\ => \Use_E2.BSCAN_I_n_8\,
      \Use_JTAG_BSCAN.tms_reg_reg_1\ => \Use_JTAG_BSCAN.tms_reg_reg_n_0\,
      \Using_FPGA.Native_0\ => \Use_E2.LUT1_I_n_1\,
      \Using_FPGA.Native_1\(0) => \JTAG_CONTROL_I/Test_Access_Port.ir\(4),
      \Using_FPGA.Native_2\ => \Use_E2.LUT1_I_n_4\,
      \Using_FPGA.Native_3\ => \Use_E2.LUT1_I_n_5\
    );
\Use_JTAG_BSCAN.BUFG_JTAG_TCK\: entity work.scu35_io_design_mdm_1_0_MB_BUFGCE_1
     port map (
      \Use_JTAG_BSCAN.tck_int\ => \Use_JTAG_BSCAN.tck_int\,
      \Using_FPGA.Native_0\ => \Use_JTAG_BSCAN.tms_ok_reg_n_0\,
      tck => tck
    );
\Use_JTAG_BSCAN.bit_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      O => \Use_JTAG_BSCAN.bit_cnt[0]_i_1_n_0\
    );
\Use_JTAG_BSCAN.bit_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      O => plusOp(1)
    );
\Use_JTAG_BSCAN.bit_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(2),
      O => plusOp(2)
    );
\Use_JTAG_BSCAN.bit_cnt[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(2),
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      I3 => \Use_JTAG_BSCAN.bit_cnt_reg\(3),
      O => plusOp(3)
    );
\Use_JTAG_BSCAN.bit_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(3),
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      I3 => \Use_JTAG_BSCAN.bit_cnt_reg\(2),
      I4 => \Use_JTAG_BSCAN.bit_cnt_reg\(4),
      O => plusOp(4)
    );
\Use_JTAG_BSCAN.bit_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(4),
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(2),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      I3 => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      I4 => \Use_JTAG_BSCAN.bit_cnt_reg\(3),
      I5 => \Use_JTAG_BSCAN.bit_cnt_reg\(5),
      O => plusOp(5)
    );
\Use_JTAG_BSCAN.bit_cnt[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt[7]_i_3_n_0\,
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(4),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(5),
      I3 => \Use_JTAG_BSCAN.bit_cnt_reg\(6),
      O => plusOp(6)
    );
\Use_JTAG_BSCAN.bit_cnt[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt[7]_i_3_n_0\,
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(6),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(5),
      I3 => \Use_JTAG_BSCAN.bit_cnt_reg\(4),
      I4 => \Use_JTAG_BSCAN.bit_cnt_reg\(7),
      O => plusOp(7)
    );
\Use_JTAG_BSCAN.bit_cnt[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bit_cnt_reg\(2),
      I1 => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      I2 => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      I3 => \Use_JTAG_BSCAN.bit_cnt_reg\(3),
      O => \Use_JTAG_BSCAN.bit_cnt[7]_i_3_n_0\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => \Use_JTAG_BSCAN.bit_cnt[0]_i_1_n_0\,
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(0),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(1),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(1),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(2),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(2),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(3),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(3),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(4),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(4),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(5),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(5),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(6),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(6),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bit_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.bit_cnt\(0),
      D => plusOp(7),
      Q => \Use_JTAG_BSCAN.bit_cnt_reg\(7),
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.bscanid_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(1),
      Q => \Use_JTAG_BSCAN.bscanid\(0),
      S => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[10]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(11),
      Q => \Use_JTAG_BSCAN.bscanid__0\(10),
      S => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_gate__0_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid__0\(11),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[12]_Use_JTAG_BSCAN.bscanid_reg_r_6\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg[12]_Use_JTAG_BSCAN.bscanid_reg_r_6_n_0\,
      R => '0'
    );
\Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '0',
      A1 => '1',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => tck,
      D => \Use_JTAG_BSCAN.bscanid__0\(20),
      Q => \Use_JTAG_BSCAN.bscanid_reg[13]_srl7___Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\
    );
\Use_JTAG_BSCAN.bscanid_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_gate__1_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid__0\(1),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[20]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(21),
      Q => \Use_JTAG_BSCAN.bscanid__0\(20),
      S => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(22),
      Q => \Use_JTAG_BSCAN.bscanid__0\(21),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(23),
      Q => \Use_JTAG_BSCAN.bscanid__0\(22),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[23]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(24),
      Q => \Use_JTAG_BSCAN.bscanid__0\(23),
      S => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(25),
      Q => \Use_JTAG_BSCAN.bscanid__0\(24),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(26),
      Q => \Use_JTAG_BSCAN.bscanid__0\(25),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[26]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(27),
      Q => \Use_JTAG_BSCAN.bscanid__0\(26),
      S => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_gate_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid__0\(27),
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg[28]_Use_JTAG_BSCAN.bscanid_reg_r_2\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg[28]_Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\,
      R => '0'
    );
\Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '0',
      A1 => '1',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => tck,
      D => \^dbg_tdi_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg[29]_srl3___Use_JTAG_BSCAN.bscanid_reg_r_1_n_0\
    );
\Use_JTAG_BSCAN.bscanid_reg[2]_Use_JTAG_BSCAN.bscanid_reg_r_5\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg[2]_Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\,
      R => '0'
    );
\Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '1',
      A3 => '0',
      CE => '1',
      CLK => tck,
      D => \Use_JTAG_BSCAN.bscanid__0\(9),
      Q => \Use_JTAG_BSCAN.bscanid_reg[3]_srl6___Use_JTAG_BSCAN.bscanid_reg_r_4_n_0\
    );
\Use_JTAG_BSCAN.bscanid_reg[9]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid__0\(10),
      Q => \Use_JTAG_BSCAN.bscanid__0\(9),
      S => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_gate\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bscanid_reg[28]_Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\,
      I1 => \Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\,
      O => \Use_JTAG_BSCAN.bscanid_reg_gate_n_0\
    );
\Use_JTAG_BSCAN.bscanid_reg_gate__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bscanid_reg[12]_Use_JTAG_BSCAN.bscanid_reg_r_6_n_0\,
      I1 => \Use_JTAG_BSCAN.bscanid_reg_r_6_n_0\,
      O => \Use_JTAG_BSCAN.bscanid_reg_gate__0_n_0\
    );
\Use_JTAG_BSCAN.bscanid_reg_gate__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \Use_JTAG_BSCAN.bscanid_reg[2]_Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\,
      I1 => \Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\,
      O => \Use_JTAG_BSCAN.bscanid_reg_gate__1_n_0\
    );
\Use_JTAG_BSCAN.bscanid_reg_r\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => '1',
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_0\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_0_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_1\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_0_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_1_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_2\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_1_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_3\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_2_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_3_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_4\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_3_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_4_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_5\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_4_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.bscanid_reg_r_6\: unisim.vcomponents.FDRE
     port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.bscanid_reg_r_5_n_0\,
      Q => \Use_JTAG_BSCAN.bscanid_reg_r_6_n_0\,
      R => \Use_E2.BSCAN_I_n_10\
    );
\Use_JTAG_BSCAN.id_flag_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_E2.BSCAN_I_n_11\,
      Q => \Use_JTAG_BSCAN.id_flag\,
      R => '0'
    );
\Use_JTAG_BSCAN.jtag_tms_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_JTAG_BSCAN.tms_reg_reg_n_0\,
      Q => jtag_tms,
      R => '0'
    );
\Use_JTAG_BSCAN.mode_reg_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_E2.LUT1_I_n_5\,
      Q => \Use_JTAG_BSCAN.mode_reg__0\,
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.tap_cnt_ok_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_E2.BSCAN_I_n_13\,
      Q => \Use_JTAG_BSCAN.tap_cnt_ok\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[1]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[0]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[2]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[1]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[3]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[2]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[4]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[3]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[5]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[4]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[6]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[5]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[7]\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[6]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tap_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => \Use_JTAG_BSCAN.tap_cnt\(0),
      D => \^dbg_tdi_0\,
      Q => \Use_JTAG_BSCAN.tap_cnt_reg_n_0_[7]\,
      R => '0'
    );
\Use_JTAG_BSCAN.tms_ok_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_E2.BSCAN_I_n_4\,
      Q => \Use_JTAG_BSCAN.tms_ok_reg_n_0\,
      R => \Use_JTAG_BSCAN.tms_ok\
    );
\Use_JTAG_BSCAN.tms_reg_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => tck,
      CE => '1',
      D => \Use_E2.LUT1_I_n_4\,
      Q => \Use_JTAG_BSCAN.tms_reg_reg_n_0\,
      R => \Use_JTAG_BSCAN.tms_ok\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scu35_io_design_mdm_1_0 is
  port (
    Debug_SYS_Rst : out STD_LOGIC;
    Dbg_Clk_0 : out STD_LOGIC;
    Dbg_TDI_0 : out STD_LOGIC;
    Dbg_TDO_0 : in STD_LOGIC;
    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Capture_0 : out STD_LOGIC;
    Dbg_Shift_0 : out STD_LOGIC;
    Dbg_Update_0 : out STD_LOGIC;
    Dbg_Rst_0 : out STD_LOGIC;
    Dbg_Disable_0 : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of scu35_io_design_mdm_1_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of scu35_io_design_mdm_1_0 : entity is "scu35_io_design_mdm_1_0,mdm_riscv,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of scu35_io_design_mdm_1_0 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of scu35_io_design_mdm_1_0 : entity is "mdm_riscv,Vivado 2025.2";
end scu35_io_design_mdm_1_0;

architecture STRUCTURE of scu35_io_design_mdm_1_0 is
  signal \<const0>\ : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARVALID_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWVALID_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BREADY_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Capture_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Clk_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Disable_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RREADY_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Rst_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Shift_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TDI_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrClk_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_TrReady_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Update_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WVALID_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_BRK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_DRCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_RESET_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_SEL_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_TDI_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Ext_NM_BRK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Read_Strobe_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_10_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_11_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_12_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_13_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_14_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_15_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_16_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_17_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_18_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_19_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_20_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_21_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_22_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_23_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_24_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_25_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_26_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_27_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_28_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_29_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_30_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_31_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_4_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_5_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_6_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_7_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_8_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_LMB_Write_Strobe_9_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_ARLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_ARVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_AWLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_AWVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_BREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_RREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_WLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_WVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S_AXI_ARREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S_AXI_AWREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S_AXI_BVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S_AXI_RVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S_AXI_WREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_TRACE_CTL_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Ack_In_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Ack_In_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Ack_In_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Ack_In_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Out_0_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Out_1_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Out_2_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trig_Out_3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_bscan_ext_tdo_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_ARADDR_0_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_1_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_10_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_11_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_12_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_13_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_14_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_15_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_16_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_17_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_18_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_19_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_2_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_20_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_21_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_22_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_23_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_24_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_25_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_26_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_27_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_28_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_29_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_3_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_30_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_31_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_4_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_5_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_6_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_7_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_8_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_ARADDR_9_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_0_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_1_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_10_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_11_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_12_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_13_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_14_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_15_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_16_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_17_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_18_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_19_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_2_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_20_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_21_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_22_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_23_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_24_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_25_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_26_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_27_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_28_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_29_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_3_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_30_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_31_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_4_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_5_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_6_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_7_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_8_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_AWADDR_9_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
  signal NLW_U0_Dbg_Reg_En_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Reg_En_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_Out_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_WDATA_0_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_1_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_10_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_11_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_12_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_13_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_14_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_15_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_16_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_17_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_18_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_19_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_2_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_20_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_21_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_22_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_23_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_24_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_25_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_26_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_27_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_28_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_29_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_3_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_30_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_31_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_4_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_5_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_6_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_7_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_8_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_WDATA_9_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_LMB_Byte_Enable_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Byte_Enable_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_LMB_Data_Addr_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Addr_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_LMB_Data_Write_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_M_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXIS_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal NLW_U0_M_AXI_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_S_AXI_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_S_AXI_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_S_AXI_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  attribute C_ADDR_SIZE : integer;
  attribute C_ADDR_SIZE of U0 : label is 32;
  attribute C_AVOID_PRIMITIVES : integer;
  attribute C_AVOID_PRIMITIVES of U0 : label is 0;
  attribute C_BSCANID : integer;
  attribute C_BSCANID of U0 : label is 0;
  attribute C_DATA_SIZE : integer;
  attribute C_DATA_SIZE of U0 : label is 32;
  attribute C_DBG_MEM_ACCESS : integer;
  attribute C_DBG_MEM_ACCESS of U0 : label is 0;
  attribute C_DBG_REG_ACCESS : integer;
  attribute C_DBG_REG_ACCESS of U0 : label is 0;
  attribute C_DEBUG_INTERFACE : integer;
  attribute C_DEBUG_INTERFACE of U0 : label is 0;
  attribute C_DEVICE : string;
  attribute C_DEVICE of U0 : label is "xcsu35p";
  attribute C_DTM_IDCODE : integer;
  attribute C_DTM_IDCODE of U0 : label is 147;
  attribute C_EXT_TRIG_RESET_VALUE : string;
  attribute C_EXT_TRIG_RESET_VALUE of U0 : label is "20'b11110001001000110100";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "spartanuplus";
  attribute C_INTERCONNECT : integer;
  attribute C_INTERCONNECT of U0 : label is 2;
  attribute C_JTAG_CHAIN : integer;
  attribute C_JTAG_CHAIN of U0 : label is 2;
  attribute C_LMB_PROTOCOL : integer;
  attribute C_LMB_PROTOCOL of U0 : label is 0;
  attribute C_MB_DBG_PORTS : integer;
  attribute C_MB_DBG_PORTS of U0 : label is 1;
  attribute C_M_AXIS_DATA_WIDTH : integer;
  attribute C_M_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M_AXIS_ID_WIDTH : integer;
  attribute C_M_AXIS_ID_WIDTH of U0 : label is 7;
  attribute C_M_AXI_ADDR_WIDTH : integer;
  attribute C_M_AXI_ADDR_WIDTH of U0 : label is 32;
  attribute C_M_AXI_DATA_WIDTH : integer;
  attribute C_M_AXI_DATA_WIDTH of U0 : label is 32;
  attribute C_M_AXI_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_THREAD_ID_WIDTH of U0 : label is 1;
  attribute C_S_AXI_ACLK_FREQ_HZ : integer;
  attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
  attribute C_S_AXI_ADDR_WIDTH : integer;
  attribute C_S_AXI_ADDR_WIDTH of U0 : label is 4;
  attribute C_S_AXI_DATA_WIDTH : integer;
  attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
  attribute C_TRACE_ASYNC_RESET : integer;
  attribute C_TRACE_ASYNC_RESET of U0 : label is 0;
  attribute C_TRACE_CLK_FREQ_HZ : integer;
  attribute C_TRACE_CLK_FREQ_HZ of U0 : label is 200000000;
  attribute C_TRACE_CLK_OUT_PHASE : integer;
  attribute C_TRACE_CLK_OUT_PHASE of U0 : label is 90;
  attribute C_TRACE_DATA_WIDTH : integer;
  attribute C_TRACE_DATA_WIDTH of U0 : label is 32;
  attribute C_TRACE_ID : integer;
  attribute C_TRACE_ID of U0 : label is 110;
  attribute C_TRACE_OUTPUT : integer;
  attribute C_TRACE_OUTPUT of U0 : label is 0;
  attribute C_TRACE_PROTOCOL : integer;
  attribute C_TRACE_PROTOCOL of U0 : label is 1;
  attribute C_USE_BSCAN : integer;
  attribute C_USE_BSCAN of U0 : label is 0;
  attribute C_USE_BSCAN_SWITCH : integer;
  attribute C_USE_BSCAN_SWITCH of U0 : label is 0;
  attribute C_USE_CONFIG_RESET : integer;
  attribute C_USE_CONFIG_RESET of U0 : label is 0;
  attribute C_USE_CROSS_TRIGGER : integer;
  attribute C_USE_CROSS_TRIGGER of U0 : label is 0;
  attribute C_USE_JTAG_BSCAN : integer;
  attribute C_USE_JTAG_BSCAN of U0 : label is 1;
  attribute C_USE_UART : integer;
  attribute C_USE_UART of U0 : label is 0;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of U0 : label is std.standard.false;
  attribute bscan_debug_core : string;
  attribute bscan_debug_core of U0 : label is "FALSE";
  attribute x_interface_info : string;
  attribute x_interface_info of Dbg_Capture_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
  attribute x_interface_info of Dbg_Clk_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of Dbg_Clk_0 : signal is "master MBDEBUG_0";
  attribute x_interface_info of Dbg_Disable_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 DISABLE";
  attribute x_interface_info of Dbg_Rst_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
  attribute x_interface_info of Dbg_Shift_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
  attribute x_interface_info of Dbg_TDI_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
  attribute x_interface_info of Dbg_TDO_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
  attribute x_interface_info of Dbg_Update_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
  attribute x_interface_info of Debug_SYS_Rst : signal is "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
  attribute x_interface_mode of Debug_SYS_Rst : signal is "master RST.Debug_SYS_Rst";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of Debug_SYS_Rst : signal is "XIL_INTERFACENAME RST.Debug_SYS_Rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
  attribute x_interface_info of Dbg_Reg_En_0 : signal is "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
begin
  Dbg_Disable_0 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.scu35_io_design_mdm_1_0_MDM_RISCV
     port map (
      Config_Reset => '0',
      Dbg_ARADDR_0(14 downto 2) => NLW_U0_Dbg_ARADDR_0_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_1(14 downto 2) => NLW_U0_Dbg_ARADDR_1_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_10(14 downto 2) => NLW_U0_Dbg_ARADDR_10_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_11(14 downto 2) => NLW_U0_Dbg_ARADDR_11_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_12(14 downto 2) => NLW_U0_Dbg_ARADDR_12_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_13(14 downto 2) => NLW_U0_Dbg_ARADDR_13_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_14(14 downto 2) => NLW_U0_Dbg_ARADDR_14_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_15(14 downto 2) => NLW_U0_Dbg_ARADDR_15_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_16(14 downto 2) => NLW_U0_Dbg_ARADDR_16_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_17(14 downto 2) => NLW_U0_Dbg_ARADDR_17_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_18(14 downto 2) => NLW_U0_Dbg_ARADDR_18_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_19(14 downto 2) => NLW_U0_Dbg_ARADDR_19_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_2(14 downto 2) => NLW_U0_Dbg_ARADDR_2_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_20(14 downto 2) => NLW_U0_Dbg_ARADDR_20_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_21(14 downto 2) => NLW_U0_Dbg_ARADDR_21_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_22(14 downto 2) => NLW_U0_Dbg_ARADDR_22_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_23(14 downto 2) => NLW_U0_Dbg_ARADDR_23_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_24(14 downto 2) => NLW_U0_Dbg_ARADDR_24_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_25(14 downto 2) => NLW_U0_Dbg_ARADDR_25_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_26(14 downto 2) => NLW_U0_Dbg_ARADDR_26_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_27(14 downto 2) => NLW_U0_Dbg_ARADDR_27_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_28(14 downto 2) => NLW_U0_Dbg_ARADDR_28_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_29(14 downto 2) => NLW_U0_Dbg_ARADDR_29_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_3(14 downto 2) => NLW_U0_Dbg_ARADDR_3_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_30(14 downto 2) => NLW_U0_Dbg_ARADDR_30_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_31(14 downto 2) => NLW_U0_Dbg_ARADDR_31_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_4(14 downto 2) => NLW_U0_Dbg_ARADDR_4_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_5(14 downto 2) => NLW_U0_Dbg_ARADDR_5_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_6(14 downto 2) => NLW_U0_Dbg_ARADDR_6_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_7(14 downto 2) => NLW_U0_Dbg_ARADDR_7_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_8(14 downto 2) => NLW_U0_Dbg_ARADDR_8_UNCONNECTED(14 downto 2),
      Dbg_ARADDR_9(14 downto 2) => NLW_U0_Dbg_ARADDR_9_UNCONNECTED(14 downto 2),
      Dbg_ARREADY_0 => '0',
      Dbg_ARREADY_1 => '0',
      Dbg_ARREADY_10 => '0',
      Dbg_ARREADY_11 => '0',
      Dbg_ARREADY_12 => '0',
      Dbg_ARREADY_13 => '0',
      Dbg_ARREADY_14 => '0',
      Dbg_ARREADY_15 => '0',
      Dbg_ARREADY_16 => '0',
      Dbg_ARREADY_17 => '0',
      Dbg_ARREADY_18 => '0',
      Dbg_ARREADY_19 => '0',
      Dbg_ARREADY_2 => '0',
      Dbg_ARREADY_20 => '0',
      Dbg_ARREADY_21 => '0',
      Dbg_ARREADY_22 => '0',
      Dbg_ARREADY_23 => '0',
      Dbg_ARREADY_24 => '0',
      Dbg_ARREADY_25 => '0',
      Dbg_ARREADY_26 => '0',
      Dbg_ARREADY_27 => '0',
      Dbg_ARREADY_28 => '0',
      Dbg_ARREADY_29 => '0',
      Dbg_ARREADY_3 => '0',
      Dbg_ARREADY_30 => '0',
      Dbg_ARREADY_31 => '0',
      Dbg_ARREADY_4 => '0',
      Dbg_ARREADY_5 => '0',
      Dbg_ARREADY_6 => '0',
      Dbg_ARREADY_7 => '0',
      Dbg_ARREADY_8 => '0',
      Dbg_ARREADY_9 => '0',
      Dbg_ARVALID_0 => NLW_U0_Dbg_ARVALID_0_UNCONNECTED,
      Dbg_ARVALID_1 => NLW_U0_Dbg_ARVALID_1_UNCONNECTED,
      Dbg_ARVALID_10 => NLW_U0_Dbg_ARVALID_10_UNCONNECTED,
      Dbg_ARVALID_11 => NLW_U0_Dbg_ARVALID_11_UNCONNECTED,
      Dbg_ARVALID_12 => NLW_U0_Dbg_ARVALID_12_UNCONNECTED,
      Dbg_ARVALID_13 => NLW_U0_Dbg_ARVALID_13_UNCONNECTED,
      Dbg_ARVALID_14 => NLW_U0_Dbg_ARVALID_14_UNCONNECTED,
      Dbg_ARVALID_15 => NLW_U0_Dbg_ARVALID_15_UNCONNECTED,
      Dbg_ARVALID_16 => NLW_U0_Dbg_ARVALID_16_UNCONNECTED,
      Dbg_ARVALID_17 => NLW_U0_Dbg_ARVALID_17_UNCONNECTED,
      Dbg_ARVALID_18 => NLW_U0_Dbg_ARVALID_18_UNCONNECTED,
      Dbg_ARVALID_19 => NLW_U0_Dbg_ARVALID_19_UNCONNECTED,
      Dbg_ARVALID_2 => NLW_U0_Dbg_ARVALID_2_UNCONNECTED,
      Dbg_ARVALID_20 => NLW_U0_Dbg_ARVALID_20_UNCONNECTED,
      Dbg_ARVALID_21 => NLW_U0_Dbg_ARVALID_21_UNCONNECTED,
      Dbg_ARVALID_22 => NLW_U0_Dbg_ARVALID_22_UNCONNECTED,
      Dbg_ARVALID_23 => NLW_U0_Dbg_ARVALID_23_UNCONNECTED,
      Dbg_ARVALID_24 => NLW_U0_Dbg_ARVALID_24_UNCONNECTED,
      Dbg_ARVALID_25 => NLW_U0_Dbg_ARVALID_25_UNCONNECTED,
      Dbg_ARVALID_26 => NLW_U0_Dbg_ARVALID_26_UNCONNECTED,
      Dbg_ARVALID_27 => NLW_U0_Dbg_ARVALID_27_UNCONNECTED,
      Dbg_ARVALID_28 => NLW_U0_Dbg_ARVALID_28_UNCONNECTED,
      Dbg_ARVALID_29 => NLW_U0_Dbg_ARVALID_29_UNCONNECTED,
      Dbg_ARVALID_3 => NLW_U0_Dbg_ARVALID_3_UNCONNECTED,
      Dbg_ARVALID_30 => NLW_U0_Dbg_ARVALID_30_UNCONNECTED,
      Dbg_ARVALID_31 => NLW_U0_Dbg_ARVALID_31_UNCONNECTED,
      Dbg_ARVALID_4 => NLW_U0_Dbg_ARVALID_4_UNCONNECTED,
      Dbg_ARVALID_5 => NLW_U0_Dbg_ARVALID_5_UNCONNECTED,
      Dbg_ARVALID_6 => NLW_U0_Dbg_ARVALID_6_UNCONNECTED,
      Dbg_ARVALID_7 => NLW_U0_Dbg_ARVALID_7_UNCONNECTED,
      Dbg_ARVALID_8 => NLW_U0_Dbg_ARVALID_8_UNCONNECTED,
      Dbg_ARVALID_9 => NLW_U0_Dbg_ARVALID_9_UNCONNECTED,
      Dbg_AWADDR_0(14 downto 2) => NLW_U0_Dbg_AWADDR_0_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_1(14 downto 2) => NLW_U0_Dbg_AWADDR_1_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_10(14 downto 2) => NLW_U0_Dbg_AWADDR_10_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_11(14 downto 2) => NLW_U0_Dbg_AWADDR_11_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_12(14 downto 2) => NLW_U0_Dbg_AWADDR_12_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_13(14 downto 2) => NLW_U0_Dbg_AWADDR_13_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_14(14 downto 2) => NLW_U0_Dbg_AWADDR_14_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_15(14 downto 2) => NLW_U0_Dbg_AWADDR_15_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_16(14 downto 2) => NLW_U0_Dbg_AWADDR_16_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_17(14 downto 2) => NLW_U0_Dbg_AWADDR_17_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_18(14 downto 2) => NLW_U0_Dbg_AWADDR_18_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_19(14 downto 2) => NLW_U0_Dbg_AWADDR_19_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_2(14 downto 2) => NLW_U0_Dbg_AWADDR_2_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_20(14 downto 2) => NLW_U0_Dbg_AWADDR_20_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_21(14 downto 2) => NLW_U0_Dbg_AWADDR_21_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_22(14 downto 2) => NLW_U0_Dbg_AWADDR_22_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_23(14 downto 2) => NLW_U0_Dbg_AWADDR_23_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_24(14 downto 2) => NLW_U0_Dbg_AWADDR_24_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_25(14 downto 2) => NLW_U0_Dbg_AWADDR_25_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_26(14 downto 2) => NLW_U0_Dbg_AWADDR_26_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_27(14 downto 2) => NLW_U0_Dbg_AWADDR_27_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_28(14 downto 2) => NLW_U0_Dbg_AWADDR_28_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_29(14 downto 2) => NLW_U0_Dbg_AWADDR_29_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_3(14 downto 2) => NLW_U0_Dbg_AWADDR_3_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_30(14 downto 2) => NLW_U0_Dbg_AWADDR_30_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_31(14 downto 2) => NLW_U0_Dbg_AWADDR_31_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_4(14 downto 2) => NLW_U0_Dbg_AWADDR_4_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_5(14 downto 2) => NLW_U0_Dbg_AWADDR_5_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_6(14 downto 2) => NLW_U0_Dbg_AWADDR_6_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_7(14 downto 2) => NLW_U0_Dbg_AWADDR_7_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_8(14 downto 2) => NLW_U0_Dbg_AWADDR_8_UNCONNECTED(14 downto 2),
      Dbg_AWADDR_9(14 downto 2) => NLW_U0_Dbg_AWADDR_9_UNCONNECTED(14 downto 2),
      Dbg_AWREADY_0 => '0',
      Dbg_AWREADY_1 => '0',
      Dbg_AWREADY_10 => '0',
      Dbg_AWREADY_11 => '0',
      Dbg_AWREADY_12 => '0',
      Dbg_AWREADY_13 => '0',
      Dbg_AWREADY_14 => '0',
      Dbg_AWREADY_15 => '0',
      Dbg_AWREADY_16 => '0',
      Dbg_AWREADY_17 => '0',
      Dbg_AWREADY_18 => '0',
      Dbg_AWREADY_19 => '0',
      Dbg_AWREADY_2 => '0',
      Dbg_AWREADY_20 => '0',
      Dbg_AWREADY_21 => '0',
      Dbg_AWREADY_22 => '0',
      Dbg_AWREADY_23 => '0',
      Dbg_AWREADY_24 => '0',
      Dbg_AWREADY_25 => '0',
      Dbg_AWREADY_26 => '0',
      Dbg_AWREADY_27 => '0',
      Dbg_AWREADY_28 => '0',
      Dbg_AWREADY_29 => '0',
      Dbg_AWREADY_3 => '0',
      Dbg_AWREADY_30 => '0',
      Dbg_AWREADY_31 => '0',
      Dbg_AWREADY_4 => '0',
      Dbg_AWREADY_5 => '0',
      Dbg_AWREADY_6 => '0',
      Dbg_AWREADY_7 => '0',
      Dbg_AWREADY_8 => '0',
      Dbg_AWREADY_9 => '0',
      Dbg_AWVALID_0 => NLW_U0_Dbg_AWVALID_0_UNCONNECTED,
      Dbg_AWVALID_1 => NLW_U0_Dbg_AWVALID_1_UNCONNECTED,
      Dbg_AWVALID_10 => NLW_U0_Dbg_AWVALID_10_UNCONNECTED,
      Dbg_AWVALID_11 => NLW_U0_Dbg_AWVALID_11_UNCONNECTED,
      Dbg_AWVALID_12 => NLW_U0_Dbg_AWVALID_12_UNCONNECTED,
      Dbg_AWVALID_13 => NLW_U0_Dbg_AWVALID_13_UNCONNECTED,
      Dbg_AWVALID_14 => NLW_U0_Dbg_AWVALID_14_UNCONNECTED,
      Dbg_AWVALID_15 => NLW_U0_Dbg_AWVALID_15_UNCONNECTED,
      Dbg_AWVALID_16 => NLW_U0_Dbg_AWVALID_16_UNCONNECTED,
      Dbg_AWVALID_17 => NLW_U0_Dbg_AWVALID_17_UNCONNECTED,
      Dbg_AWVALID_18 => NLW_U0_Dbg_AWVALID_18_UNCONNECTED,
      Dbg_AWVALID_19 => NLW_U0_Dbg_AWVALID_19_UNCONNECTED,
      Dbg_AWVALID_2 => NLW_U0_Dbg_AWVALID_2_UNCONNECTED,
      Dbg_AWVALID_20 => NLW_U0_Dbg_AWVALID_20_UNCONNECTED,
      Dbg_AWVALID_21 => NLW_U0_Dbg_AWVALID_21_UNCONNECTED,
      Dbg_AWVALID_22 => NLW_U0_Dbg_AWVALID_22_UNCONNECTED,
      Dbg_AWVALID_23 => NLW_U0_Dbg_AWVALID_23_UNCONNECTED,
      Dbg_AWVALID_24 => NLW_U0_Dbg_AWVALID_24_UNCONNECTED,
      Dbg_AWVALID_25 => NLW_U0_Dbg_AWVALID_25_UNCONNECTED,
      Dbg_AWVALID_26 => NLW_U0_Dbg_AWVALID_26_UNCONNECTED,
      Dbg_AWVALID_27 => NLW_U0_Dbg_AWVALID_27_UNCONNECTED,
      Dbg_AWVALID_28 => NLW_U0_Dbg_AWVALID_28_UNCONNECTED,
      Dbg_AWVALID_29 => NLW_U0_Dbg_AWVALID_29_UNCONNECTED,
      Dbg_AWVALID_3 => NLW_U0_Dbg_AWVALID_3_UNCONNECTED,
      Dbg_AWVALID_30 => NLW_U0_Dbg_AWVALID_30_UNCONNECTED,
      Dbg_AWVALID_31 => NLW_U0_Dbg_AWVALID_31_UNCONNECTED,
      Dbg_AWVALID_4 => NLW_U0_Dbg_AWVALID_4_UNCONNECTED,
      Dbg_AWVALID_5 => NLW_U0_Dbg_AWVALID_5_UNCONNECTED,
      Dbg_AWVALID_6 => NLW_U0_Dbg_AWVALID_6_UNCONNECTED,
      Dbg_AWVALID_7 => NLW_U0_Dbg_AWVALID_7_UNCONNECTED,
      Dbg_AWVALID_8 => NLW_U0_Dbg_AWVALID_8_UNCONNECTED,
      Dbg_AWVALID_9 => NLW_U0_Dbg_AWVALID_9_UNCONNECTED,
      Dbg_BREADY_0 => NLW_U0_Dbg_BREADY_0_UNCONNECTED,
      Dbg_BREADY_1 => NLW_U0_Dbg_BREADY_1_UNCONNECTED,
      Dbg_BREADY_10 => NLW_U0_Dbg_BREADY_10_UNCONNECTED,
      Dbg_BREADY_11 => NLW_U0_Dbg_BREADY_11_UNCONNECTED,
      Dbg_BREADY_12 => NLW_U0_Dbg_BREADY_12_UNCONNECTED,
      Dbg_BREADY_13 => NLW_U0_Dbg_BREADY_13_UNCONNECTED,
      Dbg_BREADY_14 => NLW_U0_Dbg_BREADY_14_UNCONNECTED,
      Dbg_BREADY_15 => NLW_U0_Dbg_BREADY_15_UNCONNECTED,
      Dbg_BREADY_16 => NLW_U0_Dbg_BREADY_16_UNCONNECTED,
      Dbg_BREADY_17 => NLW_U0_Dbg_BREADY_17_UNCONNECTED,
      Dbg_BREADY_18 => NLW_U0_Dbg_BREADY_18_UNCONNECTED,
      Dbg_BREADY_19 => NLW_U0_Dbg_BREADY_19_UNCONNECTED,
      Dbg_BREADY_2 => NLW_U0_Dbg_BREADY_2_UNCONNECTED,
      Dbg_BREADY_20 => NLW_U0_Dbg_BREADY_20_UNCONNECTED,
      Dbg_BREADY_21 => NLW_U0_Dbg_BREADY_21_UNCONNECTED,
      Dbg_BREADY_22 => NLW_U0_Dbg_BREADY_22_UNCONNECTED,
      Dbg_BREADY_23 => NLW_U0_Dbg_BREADY_23_UNCONNECTED,
      Dbg_BREADY_24 => NLW_U0_Dbg_BREADY_24_UNCONNECTED,
      Dbg_BREADY_25 => NLW_U0_Dbg_BREADY_25_UNCONNECTED,
      Dbg_BREADY_26 => NLW_U0_Dbg_BREADY_26_UNCONNECTED,
      Dbg_BREADY_27 => NLW_U0_Dbg_BREADY_27_UNCONNECTED,
      Dbg_BREADY_28 => NLW_U0_Dbg_BREADY_28_UNCONNECTED,
      Dbg_BREADY_29 => NLW_U0_Dbg_BREADY_29_UNCONNECTED,
      Dbg_BREADY_3 => NLW_U0_Dbg_BREADY_3_UNCONNECTED,
      Dbg_BREADY_30 => NLW_U0_Dbg_BREADY_30_UNCONNECTED,
      Dbg_BREADY_31 => NLW_U0_Dbg_BREADY_31_UNCONNECTED,
      Dbg_BREADY_4 => NLW_U0_Dbg_BREADY_4_UNCONNECTED,
      Dbg_BREADY_5 => NLW_U0_Dbg_BREADY_5_UNCONNECTED,
      Dbg_BREADY_6 => NLW_U0_Dbg_BREADY_6_UNCONNECTED,
      Dbg_BREADY_7 => NLW_U0_Dbg_BREADY_7_UNCONNECTED,
      Dbg_BREADY_8 => NLW_U0_Dbg_BREADY_8_UNCONNECTED,
      Dbg_BREADY_9 => NLW_U0_Dbg_BREADY_9_UNCONNECTED,
      Dbg_BRESP_0(1 downto 0) => B"00",
      Dbg_BRESP_1(1 downto 0) => B"00",
      Dbg_BRESP_10(1 downto 0) => B"00",
      Dbg_BRESP_11(1 downto 0) => B"00",
      Dbg_BRESP_12(1 downto 0) => B"00",
      Dbg_BRESP_13(1 downto 0) => B"00",
      Dbg_BRESP_14(1 downto 0) => B"00",
      Dbg_BRESP_15(1 downto 0) => B"00",
      Dbg_BRESP_16(1 downto 0) => B"00",
      Dbg_BRESP_17(1 downto 0) => B"00",
      Dbg_BRESP_18(1 downto 0) => B"00",
      Dbg_BRESP_19(1 downto 0) => B"00",
      Dbg_BRESP_2(1 downto 0) => B"00",
      Dbg_BRESP_20(1 downto 0) => B"00",
      Dbg_BRESP_21(1 downto 0) => B"00",
      Dbg_BRESP_22(1 downto 0) => B"00",
      Dbg_BRESP_23(1 downto 0) => B"00",
      Dbg_BRESP_24(1 downto 0) => B"00",
      Dbg_BRESP_25(1 downto 0) => B"00",
      Dbg_BRESP_26(1 downto 0) => B"00",
      Dbg_BRESP_27(1 downto 0) => B"00",
      Dbg_BRESP_28(1 downto 0) => B"00",
      Dbg_BRESP_29(1 downto 0) => B"00",
      Dbg_BRESP_3(1 downto 0) => B"00",
      Dbg_BRESP_30(1 downto 0) => B"00",
      Dbg_BRESP_31(1 downto 0) => B"00",
      Dbg_BRESP_4(1 downto 0) => B"00",
      Dbg_BRESP_5(1 downto 0) => B"00",
      Dbg_BRESP_6(1 downto 0) => B"00",
      Dbg_BRESP_7(1 downto 0) => B"00",
      Dbg_BRESP_8(1 downto 0) => B"00",
      Dbg_BRESP_9(1 downto 0) => B"00",
      Dbg_BVALID_0 => '0',
      Dbg_BVALID_1 => '0',
      Dbg_BVALID_10 => '0',
      Dbg_BVALID_11 => '0',
      Dbg_BVALID_12 => '0',
      Dbg_BVALID_13 => '0',
      Dbg_BVALID_14 => '0',
      Dbg_BVALID_15 => '0',
      Dbg_BVALID_16 => '0',
      Dbg_BVALID_17 => '0',
      Dbg_BVALID_18 => '0',
      Dbg_BVALID_19 => '0',
      Dbg_BVALID_2 => '0',
      Dbg_BVALID_20 => '0',
      Dbg_BVALID_21 => '0',
      Dbg_BVALID_22 => '0',
      Dbg_BVALID_23 => '0',
      Dbg_BVALID_24 => '0',
      Dbg_BVALID_25 => '0',
      Dbg_BVALID_26 => '0',
      Dbg_BVALID_27 => '0',
      Dbg_BVALID_28 => '0',
      Dbg_BVALID_29 => '0',
      Dbg_BVALID_3 => '0',
      Dbg_BVALID_30 => '0',
      Dbg_BVALID_31 => '0',
      Dbg_BVALID_4 => '0',
      Dbg_BVALID_5 => '0',
      Dbg_BVALID_6 => '0',
      Dbg_BVALID_7 => '0',
      Dbg_BVALID_8 => '0',
      Dbg_BVALID_9 => '0',
      Dbg_Capture_0 => Dbg_Capture_0,
      Dbg_Capture_1 => NLW_U0_Dbg_Capture_1_UNCONNECTED,
      Dbg_Capture_10 => NLW_U0_Dbg_Capture_10_UNCONNECTED,
      Dbg_Capture_11 => NLW_U0_Dbg_Capture_11_UNCONNECTED,
      Dbg_Capture_12 => NLW_U0_Dbg_Capture_12_UNCONNECTED,
      Dbg_Capture_13 => NLW_U0_Dbg_Capture_13_UNCONNECTED,
      Dbg_Capture_14 => NLW_U0_Dbg_Capture_14_UNCONNECTED,
      Dbg_Capture_15 => NLW_U0_Dbg_Capture_15_UNCONNECTED,
      Dbg_Capture_16 => NLW_U0_Dbg_Capture_16_UNCONNECTED,
      Dbg_Capture_17 => NLW_U0_Dbg_Capture_17_UNCONNECTED,
      Dbg_Capture_18 => NLW_U0_Dbg_Capture_18_UNCONNECTED,
      Dbg_Capture_19 => NLW_U0_Dbg_Capture_19_UNCONNECTED,
      Dbg_Capture_2 => NLW_U0_Dbg_Capture_2_UNCONNECTED,
      Dbg_Capture_20 => NLW_U0_Dbg_Capture_20_UNCONNECTED,
      Dbg_Capture_21 => NLW_U0_Dbg_Capture_21_UNCONNECTED,
      Dbg_Capture_22 => NLW_U0_Dbg_Capture_22_UNCONNECTED,
      Dbg_Capture_23 => NLW_U0_Dbg_Capture_23_UNCONNECTED,
      Dbg_Capture_24 => NLW_U0_Dbg_Capture_24_UNCONNECTED,
      Dbg_Capture_25 => NLW_U0_Dbg_Capture_25_UNCONNECTED,
      Dbg_Capture_26 => NLW_U0_Dbg_Capture_26_UNCONNECTED,
      Dbg_Capture_27 => NLW_U0_Dbg_Capture_27_UNCONNECTED,
      Dbg_Capture_28 => NLW_U0_Dbg_Capture_28_UNCONNECTED,
      Dbg_Capture_29 => NLW_U0_Dbg_Capture_29_UNCONNECTED,
      Dbg_Capture_3 => NLW_U0_Dbg_Capture_3_UNCONNECTED,
      Dbg_Capture_30 => NLW_U0_Dbg_Capture_30_UNCONNECTED,
      Dbg_Capture_31 => NLW_U0_Dbg_Capture_31_UNCONNECTED,
      Dbg_Capture_4 => NLW_U0_Dbg_Capture_4_UNCONNECTED,
      Dbg_Capture_5 => NLW_U0_Dbg_Capture_5_UNCONNECTED,
      Dbg_Capture_6 => NLW_U0_Dbg_Capture_6_UNCONNECTED,
      Dbg_Capture_7 => NLW_U0_Dbg_Capture_7_UNCONNECTED,
      Dbg_Capture_8 => NLW_U0_Dbg_Capture_8_UNCONNECTED,
      Dbg_Capture_9 => NLW_U0_Dbg_Capture_9_UNCONNECTED,
      Dbg_Clk_0 => Dbg_Clk_0,
      Dbg_Clk_1 => NLW_U0_Dbg_Clk_1_UNCONNECTED,
      Dbg_Clk_10 => NLW_U0_Dbg_Clk_10_UNCONNECTED,
      Dbg_Clk_11 => NLW_U0_Dbg_Clk_11_UNCONNECTED,
      Dbg_Clk_12 => NLW_U0_Dbg_Clk_12_UNCONNECTED,
      Dbg_Clk_13 => NLW_U0_Dbg_Clk_13_UNCONNECTED,
      Dbg_Clk_14 => NLW_U0_Dbg_Clk_14_UNCONNECTED,
      Dbg_Clk_15 => NLW_U0_Dbg_Clk_15_UNCONNECTED,
      Dbg_Clk_16 => NLW_U0_Dbg_Clk_16_UNCONNECTED,
      Dbg_Clk_17 => NLW_U0_Dbg_Clk_17_UNCONNECTED,
      Dbg_Clk_18 => NLW_U0_Dbg_Clk_18_UNCONNECTED,
      Dbg_Clk_19 => NLW_U0_Dbg_Clk_19_UNCONNECTED,
      Dbg_Clk_2 => NLW_U0_Dbg_Clk_2_UNCONNECTED,
      Dbg_Clk_20 => NLW_U0_Dbg_Clk_20_UNCONNECTED,
      Dbg_Clk_21 => NLW_U0_Dbg_Clk_21_UNCONNECTED,
      Dbg_Clk_22 => NLW_U0_Dbg_Clk_22_UNCONNECTED,
      Dbg_Clk_23 => NLW_U0_Dbg_Clk_23_UNCONNECTED,
      Dbg_Clk_24 => NLW_U0_Dbg_Clk_24_UNCONNECTED,
      Dbg_Clk_25 => NLW_U0_Dbg_Clk_25_UNCONNECTED,
      Dbg_Clk_26 => NLW_U0_Dbg_Clk_26_UNCONNECTED,
      Dbg_Clk_27 => NLW_U0_Dbg_Clk_27_UNCONNECTED,
      Dbg_Clk_28 => NLW_U0_Dbg_Clk_28_UNCONNECTED,
      Dbg_Clk_29 => NLW_U0_Dbg_Clk_29_UNCONNECTED,
      Dbg_Clk_3 => NLW_U0_Dbg_Clk_3_UNCONNECTED,
      Dbg_Clk_30 => NLW_U0_Dbg_Clk_30_UNCONNECTED,
      Dbg_Clk_31 => NLW_U0_Dbg_Clk_31_UNCONNECTED,
      Dbg_Clk_4 => NLW_U0_Dbg_Clk_4_UNCONNECTED,
      Dbg_Clk_5 => NLW_U0_Dbg_Clk_5_UNCONNECTED,
      Dbg_Clk_6 => NLW_U0_Dbg_Clk_6_UNCONNECTED,
      Dbg_Clk_7 => NLW_U0_Dbg_Clk_7_UNCONNECTED,
      Dbg_Clk_8 => NLW_U0_Dbg_Clk_8_UNCONNECTED,
      Dbg_Clk_9 => NLW_U0_Dbg_Clk_9_UNCONNECTED,
      Dbg_Disable_0 => NLW_U0_Dbg_Disable_0_UNCONNECTED,
      Dbg_Disable_1 => NLW_U0_Dbg_Disable_1_UNCONNECTED,
      Dbg_Disable_10 => NLW_U0_Dbg_Disable_10_UNCONNECTED,
      Dbg_Disable_11 => NLW_U0_Dbg_Disable_11_UNCONNECTED,
      Dbg_Disable_12 => NLW_U0_Dbg_Disable_12_UNCONNECTED,
      Dbg_Disable_13 => NLW_U0_Dbg_Disable_13_UNCONNECTED,
      Dbg_Disable_14 => NLW_U0_Dbg_Disable_14_UNCONNECTED,
      Dbg_Disable_15 => NLW_U0_Dbg_Disable_15_UNCONNECTED,
      Dbg_Disable_16 => NLW_U0_Dbg_Disable_16_UNCONNECTED,
      Dbg_Disable_17 => NLW_U0_Dbg_Disable_17_UNCONNECTED,
      Dbg_Disable_18 => NLW_U0_Dbg_Disable_18_UNCONNECTED,
      Dbg_Disable_19 => NLW_U0_Dbg_Disable_19_UNCONNECTED,
      Dbg_Disable_2 => NLW_U0_Dbg_Disable_2_UNCONNECTED,
      Dbg_Disable_20 => NLW_U0_Dbg_Disable_20_UNCONNECTED,
      Dbg_Disable_21 => NLW_U0_Dbg_Disable_21_UNCONNECTED,
      Dbg_Disable_22 => NLW_U0_Dbg_Disable_22_UNCONNECTED,
      Dbg_Disable_23 => NLW_U0_Dbg_Disable_23_UNCONNECTED,
      Dbg_Disable_24 => NLW_U0_Dbg_Disable_24_UNCONNECTED,
      Dbg_Disable_25 => NLW_U0_Dbg_Disable_25_UNCONNECTED,
      Dbg_Disable_26 => NLW_U0_Dbg_Disable_26_UNCONNECTED,
      Dbg_Disable_27 => NLW_U0_Dbg_Disable_27_UNCONNECTED,
      Dbg_Disable_28 => NLW_U0_Dbg_Disable_28_UNCONNECTED,
      Dbg_Disable_29 => NLW_U0_Dbg_Disable_29_UNCONNECTED,
      Dbg_Disable_3 => NLW_U0_Dbg_Disable_3_UNCONNECTED,
      Dbg_Disable_30 => NLW_U0_Dbg_Disable_30_UNCONNECTED,
      Dbg_Disable_31 => NLW_U0_Dbg_Disable_31_UNCONNECTED,
      Dbg_Disable_4 => NLW_U0_Dbg_Disable_4_UNCONNECTED,
      Dbg_Disable_5 => NLW_U0_Dbg_Disable_5_UNCONNECTED,
      Dbg_Disable_6 => NLW_U0_Dbg_Disable_6_UNCONNECTED,
      Dbg_Disable_7 => NLW_U0_Dbg_Disable_7_UNCONNECTED,
      Dbg_Disable_8 => NLW_U0_Dbg_Disable_8_UNCONNECTED,
      Dbg_Disable_9 => NLW_U0_Dbg_Disable_9_UNCONNECTED,
      Dbg_RDATA_0(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_1(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_10(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_11(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_12(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_13(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_14(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_15(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_16(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_17(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_18(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_19(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_2(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_20(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_21(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_22(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_23(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_24(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_25(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_26(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_27(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_28(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_29(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_3(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_30(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_31(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_4(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_5(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_6(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_7(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_8(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RDATA_9(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_RREADY_0 => NLW_U0_Dbg_RREADY_0_UNCONNECTED,
      Dbg_RREADY_1 => NLW_U0_Dbg_RREADY_1_UNCONNECTED,
      Dbg_RREADY_10 => NLW_U0_Dbg_RREADY_10_UNCONNECTED,
      Dbg_RREADY_11 => NLW_U0_Dbg_RREADY_11_UNCONNECTED,
      Dbg_RREADY_12 => NLW_U0_Dbg_RREADY_12_UNCONNECTED,
      Dbg_RREADY_13 => NLW_U0_Dbg_RREADY_13_UNCONNECTED,
      Dbg_RREADY_14 => NLW_U0_Dbg_RREADY_14_UNCONNECTED,
      Dbg_RREADY_15 => NLW_U0_Dbg_RREADY_15_UNCONNECTED,
      Dbg_RREADY_16 => NLW_U0_Dbg_RREADY_16_UNCONNECTED,
      Dbg_RREADY_17 => NLW_U0_Dbg_RREADY_17_UNCONNECTED,
      Dbg_RREADY_18 => NLW_U0_Dbg_RREADY_18_UNCONNECTED,
      Dbg_RREADY_19 => NLW_U0_Dbg_RREADY_19_UNCONNECTED,
      Dbg_RREADY_2 => NLW_U0_Dbg_RREADY_2_UNCONNECTED,
      Dbg_RREADY_20 => NLW_U0_Dbg_RREADY_20_UNCONNECTED,
      Dbg_RREADY_21 => NLW_U0_Dbg_RREADY_21_UNCONNECTED,
      Dbg_RREADY_22 => NLW_U0_Dbg_RREADY_22_UNCONNECTED,
      Dbg_RREADY_23 => NLW_U0_Dbg_RREADY_23_UNCONNECTED,
      Dbg_RREADY_24 => NLW_U0_Dbg_RREADY_24_UNCONNECTED,
      Dbg_RREADY_25 => NLW_U0_Dbg_RREADY_25_UNCONNECTED,
      Dbg_RREADY_26 => NLW_U0_Dbg_RREADY_26_UNCONNECTED,
      Dbg_RREADY_27 => NLW_U0_Dbg_RREADY_27_UNCONNECTED,
      Dbg_RREADY_28 => NLW_U0_Dbg_RREADY_28_UNCONNECTED,
      Dbg_RREADY_29 => NLW_U0_Dbg_RREADY_29_UNCONNECTED,
      Dbg_RREADY_3 => NLW_U0_Dbg_RREADY_3_UNCONNECTED,
      Dbg_RREADY_30 => NLW_U0_Dbg_RREADY_30_UNCONNECTED,
      Dbg_RREADY_31 => NLW_U0_Dbg_RREADY_31_UNCONNECTED,
      Dbg_RREADY_4 => NLW_U0_Dbg_RREADY_4_UNCONNECTED,
      Dbg_RREADY_5 => NLW_U0_Dbg_RREADY_5_UNCONNECTED,
      Dbg_RREADY_6 => NLW_U0_Dbg_RREADY_6_UNCONNECTED,
      Dbg_RREADY_7 => NLW_U0_Dbg_RREADY_7_UNCONNECTED,
      Dbg_RREADY_8 => NLW_U0_Dbg_RREADY_8_UNCONNECTED,
      Dbg_RREADY_9 => NLW_U0_Dbg_RREADY_9_UNCONNECTED,
      Dbg_RRESP_0(1 downto 0) => B"00",
      Dbg_RRESP_1(1 downto 0) => B"00",
      Dbg_RRESP_10(1 downto 0) => B"00",
      Dbg_RRESP_11(1 downto 0) => B"00",
      Dbg_RRESP_12(1 downto 0) => B"00",
      Dbg_RRESP_13(1 downto 0) => B"00",
      Dbg_RRESP_14(1 downto 0) => B"00",
      Dbg_RRESP_15(1 downto 0) => B"00",
      Dbg_RRESP_16(1 downto 0) => B"00",
      Dbg_RRESP_17(1 downto 0) => B"00",
      Dbg_RRESP_18(1 downto 0) => B"00",
      Dbg_RRESP_19(1 downto 0) => B"00",
      Dbg_RRESP_2(1 downto 0) => B"00",
      Dbg_RRESP_20(1 downto 0) => B"00",
      Dbg_RRESP_21(1 downto 0) => B"00",
      Dbg_RRESP_22(1 downto 0) => B"00",
      Dbg_RRESP_23(1 downto 0) => B"00",
      Dbg_RRESP_24(1 downto 0) => B"00",
      Dbg_RRESP_25(1 downto 0) => B"00",
      Dbg_RRESP_26(1 downto 0) => B"00",
      Dbg_RRESP_27(1 downto 0) => B"00",
      Dbg_RRESP_28(1 downto 0) => B"00",
      Dbg_RRESP_29(1 downto 0) => B"00",
      Dbg_RRESP_3(1 downto 0) => B"00",
      Dbg_RRESP_30(1 downto 0) => B"00",
      Dbg_RRESP_31(1 downto 0) => B"00",
      Dbg_RRESP_4(1 downto 0) => B"00",
      Dbg_RRESP_5(1 downto 0) => B"00",
      Dbg_RRESP_6(1 downto 0) => B"00",
      Dbg_RRESP_7(1 downto 0) => B"00",
      Dbg_RRESP_8(1 downto 0) => B"00",
      Dbg_RRESP_9(1 downto 0) => B"00",
      Dbg_RVALID_0 => '0',
      Dbg_RVALID_1 => '0',
      Dbg_RVALID_10 => '0',
      Dbg_RVALID_11 => '0',
      Dbg_RVALID_12 => '0',
      Dbg_RVALID_13 => '0',
      Dbg_RVALID_14 => '0',
      Dbg_RVALID_15 => '0',
      Dbg_RVALID_16 => '0',
      Dbg_RVALID_17 => '0',
      Dbg_RVALID_18 => '0',
      Dbg_RVALID_19 => '0',
      Dbg_RVALID_2 => '0',
      Dbg_RVALID_20 => '0',
      Dbg_RVALID_21 => '0',
      Dbg_RVALID_22 => '0',
      Dbg_RVALID_23 => '0',
      Dbg_RVALID_24 => '0',
      Dbg_RVALID_25 => '0',
      Dbg_RVALID_26 => '0',
      Dbg_RVALID_27 => '0',
      Dbg_RVALID_28 => '0',
      Dbg_RVALID_29 => '0',
      Dbg_RVALID_3 => '0',
      Dbg_RVALID_30 => '0',
      Dbg_RVALID_31 => '0',
      Dbg_RVALID_4 => '0',
      Dbg_RVALID_5 => '0',
      Dbg_RVALID_6 => '0',
      Dbg_RVALID_7 => '0',
      Dbg_RVALID_8 => '0',
      Dbg_RVALID_9 => '0',
      Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
      Dbg_Reg_En_1(0 to 7) => NLW_U0_Dbg_Reg_En_1_UNCONNECTED(0 to 7),
      Dbg_Reg_En_10(0 to 7) => NLW_U0_Dbg_Reg_En_10_UNCONNECTED(0 to 7),
      Dbg_Reg_En_11(0 to 7) => NLW_U0_Dbg_Reg_En_11_UNCONNECTED(0 to 7),
      Dbg_Reg_En_12(0 to 7) => NLW_U0_Dbg_Reg_En_12_UNCONNECTED(0 to 7),
      Dbg_Reg_En_13(0 to 7) => NLW_U0_Dbg_Reg_En_13_UNCONNECTED(0 to 7),
      Dbg_Reg_En_14(0 to 7) => NLW_U0_Dbg_Reg_En_14_UNCONNECTED(0 to 7),
      Dbg_Reg_En_15(0 to 7) => NLW_U0_Dbg_Reg_En_15_UNCONNECTED(0 to 7),
      Dbg_Reg_En_16(0 to 7) => NLW_U0_Dbg_Reg_En_16_UNCONNECTED(0 to 7),
      Dbg_Reg_En_17(0 to 7) => NLW_U0_Dbg_Reg_En_17_UNCONNECTED(0 to 7),
      Dbg_Reg_En_18(0 to 7) => NLW_U0_Dbg_Reg_En_18_UNCONNECTED(0 to 7),
      Dbg_Reg_En_19(0 to 7) => NLW_U0_Dbg_Reg_En_19_UNCONNECTED(0 to 7),
      Dbg_Reg_En_2(0 to 7) => NLW_U0_Dbg_Reg_En_2_UNCONNECTED(0 to 7),
      Dbg_Reg_En_20(0 to 7) => NLW_U0_Dbg_Reg_En_20_UNCONNECTED(0 to 7),
      Dbg_Reg_En_21(0 to 7) => NLW_U0_Dbg_Reg_En_21_UNCONNECTED(0 to 7),
      Dbg_Reg_En_22(0 to 7) => NLW_U0_Dbg_Reg_En_22_UNCONNECTED(0 to 7),
      Dbg_Reg_En_23(0 to 7) => NLW_U0_Dbg_Reg_En_23_UNCONNECTED(0 to 7),
      Dbg_Reg_En_24(0 to 7) => NLW_U0_Dbg_Reg_En_24_UNCONNECTED(0 to 7),
      Dbg_Reg_En_25(0 to 7) => NLW_U0_Dbg_Reg_En_25_UNCONNECTED(0 to 7),
      Dbg_Reg_En_26(0 to 7) => NLW_U0_Dbg_Reg_En_26_UNCONNECTED(0 to 7),
      Dbg_Reg_En_27(0 to 7) => NLW_U0_Dbg_Reg_En_27_UNCONNECTED(0 to 7),
      Dbg_Reg_En_28(0 to 7) => NLW_U0_Dbg_Reg_En_28_UNCONNECTED(0 to 7),
      Dbg_Reg_En_29(0 to 7) => NLW_U0_Dbg_Reg_En_29_UNCONNECTED(0 to 7),
      Dbg_Reg_En_3(0 to 7) => NLW_U0_Dbg_Reg_En_3_UNCONNECTED(0 to 7),
      Dbg_Reg_En_30(0 to 7) => NLW_U0_Dbg_Reg_En_30_UNCONNECTED(0 to 7),
      Dbg_Reg_En_31(0 to 7) => NLW_U0_Dbg_Reg_En_31_UNCONNECTED(0 to 7),
      Dbg_Reg_En_4(0 to 7) => NLW_U0_Dbg_Reg_En_4_UNCONNECTED(0 to 7),
      Dbg_Reg_En_5(0 to 7) => NLW_U0_Dbg_Reg_En_5_UNCONNECTED(0 to 7),
      Dbg_Reg_En_6(0 to 7) => NLW_U0_Dbg_Reg_En_6_UNCONNECTED(0 to 7),
      Dbg_Reg_En_7(0 to 7) => NLW_U0_Dbg_Reg_En_7_UNCONNECTED(0 to 7),
      Dbg_Reg_En_8(0 to 7) => NLW_U0_Dbg_Reg_En_8_UNCONNECTED(0 to 7),
      Dbg_Reg_En_9(0 to 7) => NLW_U0_Dbg_Reg_En_9_UNCONNECTED(0 to 7),
      Dbg_Rst_0 => Dbg_Rst_0,
      Dbg_Rst_1 => NLW_U0_Dbg_Rst_1_UNCONNECTED,
      Dbg_Rst_10 => NLW_U0_Dbg_Rst_10_UNCONNECTED,
      Dbg_Rst_11 => NLW_U0_Dbg_Rst_11_UNCONNECTED,
      Dbg_Rst_12 => NLW_U0_Dbg_Rst_12_UNCONNECTED,
      Dbg_Rst_13 => NLW_U0_Dbg_Rst_13_UNCONNECTED,
      Dbg_Rst_14 => NLW_U0_Dbg_Rst_14_UNCONNECTED,
      Dbg_Rst_15 => NLW_U0_Dbg_Rst_15_UNCONNECTED,
      Dbg_Rst_16 => NLW_U0_Dbg_Rst_16_UNCONNECTED,
      Dbg_Rst_17 => NLW_U0_Dbg_Rst_17_UNCONNECTED,
      Dbg_Rst_18 => NLW_U0_Dbg_Rst_18_UNCONNECTED,
      Dbg_Rst_19 => NLW_U0_Dbg_Rst_19_UNCONNECTED,
      Dbg_Rst_2 => NLW_U0_Dbg_Rst_2_UNCONNECTED,
      Dbg_Rst_20 => NLW_U0_Dbg_Rst_20_UNCONNECTED,
      Dbg_Rst_21 => NLW_U0_Dbg_Rst_21_UNCONNECTED,
      Dbg_Rst_22 => NLW_U0_Dbg_Rst_22_UNCONNECTED,
      Dbg_Rst_23 => NLW_U0_Dbg_Rst_23_UNCONNECTED,
      Dbg_Rst_24 => NLW_U0_Dbg_Rst_24_UNCONNECTED,
      Dbg_Rst_25 => NLW_U0_Dbg_Rst_25_UNCONNECTED,
      Dbg_Rst_26 => NLW_U0_Dbg_Rst_26_UNCONNECTED,
      Dbg_Rst_27 => NLW_U0_Dbg_Rst_27_UNCONNECTED,
      Dbg_Rst_28 => NLW_U0_Dbg_Rst_28_UNCONNECTED,
      Dbg_Rst_29 => NLW_U0_Dbg_Rst_29_UNCONNECTED,
      Dbg_Rst_3 => NLW_U0_Dbg_Rst_3_UNCONNECTED,
      Dbg_Rst_30 => NLW_U0_Dbg_Rst_30_UNCONNECTED,
      Dbg_Rst_31 => NLW_U0_Dbg_Rst_31_UNCONNECTED,
      Dbg_Rst_4 => NLW_U0_Dbg_Rst_4_UNCONNECTED,
      Dbg_Rst_5 => NLW_U0_Dbg_Rst_5_UNCONNECTED,
      Dbg_Rst_6 => NLW_U0_Dbg_Rst_6_UNCONNECTED,
      Dbg_Rst_7 => NLW_U0_Dbg_Rst_7_UNCONNECTED,
      Dbg_Rst_8 => NLW_U0_Dbg_Rst_8_UNCONNECTED,
      Dbg_Rst_9 => NLW_U0_Dbg_Rst_9_UNCONNECTED,
      Dbg_Shift_0 => Dbg_Shift_0,
      Dbg_Shift_1 => NLW_U0_Dbg_Shift_1_UNCONNECTED,
      Dbg_Shift_10 => NLW_U0_Dbg_Shift_10_UNCONNECTED,
      Dbg_Shift_11 => NLW_U0_Dbg_Shift_11_UNCONNECTED,
      Dbg_Shift_12 => NLW_U0_Dbg_Shift_12_UNCONNECTED,
      Dbg_Shift_13 => NLW_U0_Dbg_Shift_13_UNCONNECTED,
      Dbg_Shift_14 => NLW_U0_Dbg_Shift_14_UNCONNECTED,
      Dbg_Shift_15 => NLW_U0_Dbg_Shift_15_UNCONNECTED,
      Dbg_Shift_16 => NLW_U0_Dbg_Shift_16_UNCONNECTED,
      Dbg_Shift_17 => NLW_U0_Dbg_Shift_17_UNCONNECTED,
      Dbg_Shift_18 => NLW_U0_Dbg_Shift_18_UNCONNECTED,
      Dbg_Shift_19 => NLW_U0_Dbg_Shift_19_UNCONNECTED,
      Dbg_Shift_2 => NLW_U0_Dbg_Shift_2_UNCONNECTED,
      Dbg_Shift_20 => NLW_U0_Dbg_Shift_20_UNCONNECTED,
      Dbg_Shift_21 => NLW_U0_Dbg_Shift_21_UNCONNECTED,
      Dbg_Shift_22 => NLW_U0_Dbg_Shift_22_UNCONNECTED,
      Dbg_Shift_23 => NLW_U0_Dbg_Shift_23_UNCONNECTED,
      Dbg_Shift_24 => NLW_U0_Dbg_Shift_24_UNCONNECTED,
      Dbg_Shift_25 => NLW_U0_Dbg_Shift_25_UNCONNECTED,
      Dbg_Shift_26 => NLW_U0_Dbg_Shift_26_UNCONNECTED,
      Dbg_Shift_27 => NLW_U0_Dbg_Shift_27_UNCONNECTED,
      Dbg_Shift_28 => NLW_U0_Dbg_Shift_28_UNCONNECTED,
      Dbg_Shift_29 => NLW_U0_Dbg_Shift_29_UNCONNECTED,
      Dbg_Shift_3 => NLW_U0_Dbg_Shift_3_UNCONNECTED,
      Dbg_Shift_30 => NLW_U0_Dbg_Shift_30_UNCONNECTED,
      Dbg_Shift_31 => NLW_U0_Dbg_Shift_31_UNCONNECTED,
      Dbg_Shift_4 => NLW_U0_Dbg_Shift_4_UNCONNECTED,
      Dbg_Shift_5 => NLW_U0_Dbg_Shift_5_UNCONNECTED,
      Dbg_Shift_6 => NLW_U0_Dbg_Shift_6_UNCONNECTED,
      Dbg_Shift_7 => NLW_U0_Dbg_Shift_7_UNCONNECTED,
      Dbg_Shift_8 => NLW_U0_Dbg_Shift_8_UNCONNECTED,
      Dbg_Shift_9 => NLW_U0_Dbg_Shift_9_UNCONNECTED,
      Dbg_TDI_0 => Dbg_TDI_0,
      Dbg_TDI_1 => NLW_U0_Dbg_TDI_1_UNCONNECTED,
      Dbg_TDI_10 => NLW_U0_Dbg_TDI_10_UNCONNECTED,
      Dbg_TDI_11 => NLW_U0_Dbg_TDI_11_UNCONNECTED,
      Dbg_TDI_12 => NLW_U0_Dbg_TDI_12_UNCONNECTED,
      Dbg_TDI_13 => NLW_U0_Dbg_TDI_13_UNCONNECTED,
      Dbg_TDI_14 => NLW_U0_Dbg_TDI_14_UNCONNECTED,
      Dbg_TDI_15 => NLW_U0_Dbg_TDI_15_UNCONNECTED,
      Dbg_TDI_16 => NLW_U0_Dbg_TDI_16_UNCONNECTED,
      Dbg_TDI_17 => NLW_U0_Dbg_TDI_17_UNCONNECTED,
      Dbg_TDI_18 => NLW_U0_Dbg_TDI_18_UNCONNECTED,
      Dbg_TDI_19 => NLW_U0_Dbg_TDI_19_UNCONNECTED,
      Dbg_TDI_2 => NLW_U0_Dbg_TDI_2_UNCONNECTED,
      Dbg_TDI_20 => NLW_U0_Dbg_TDI_20_UNCONNECTED,
      Dbg_TDI_21 => NLW_U0_Dbg_TDI_21_UNCONNECTED,
      Dbg_TDI_22 => NLW_U0_Dbg_TDI_22_UNCONNECTED,
      Dbg_TDI_23 => NLW_U0_Dbg_TDI_23_UNCONNECTED,
      Dbg_TDI_24 => NLW_U0_Dbg_TDI_24_UNCONNECTED,
      Dbg_TDI_25 => NLW_U0_Dbg_TDI_25_UNCONNECTED,
      Dbg_TDI_26 => NLW_U0_Dbg_TDI_26_UNCONNECTED,
      Dbg_TDI_27 => NLW_U0_Dbg_TDI_27_UNCONNECTED,
      Dbg_TDI_28 => NLW_U0_Dbg_TDI_28_UNCONNECTED,
      Dbg_TDI_29 => NLW_U0_Dbg_TDI_29_UNCONNECTED,
      Dbg_TDI_3 => NLW_U0_Dbg_TDI_3_UNCONNECTED,
      Dbg_TDI_30 => NLW_U0_Dbg_TDI_30_UNCONNECTED,
      Dbg_TDI_31 => NLW_U0_Dbg_TDI_31_UNCONNECTED,
      Dbg_TDI_4 => NLW_U0_Dbg_TDI_4_UNCONNECTED,
      Dbg_TDI_5 => NLW_U0_Dbg_TDI_5_UNCONNECTED,
      Dbg_TDI_6 => NLW_U0_Dbg_TDI_6_UNCONNECTED,
      Dbg_TDI_7 => NLW_U0_Dbg_TDI_7_UNCONNECTED,
      Dbg_TDI_8 => NLW_U0_Dbg_TDI_8_UNCONNECTED,
      Dbg_TDI_9 => NLW_U0_Dbg_TDI_9_UNCONNECTED,
      Dbg_TDO_0 => Dbg_TDO_0,
      Dbg_TDO_1 => '0',
      Dbg_TDO_10 => '0',
      Dbg_TDO_11 => '0',
      Dbg_TDO_12 => '0',
      Dbg_TDO_13 => '0',
      Dbg_TDO_14 => '0',
      Dbg_TDO_15 => '0',
      Dbg_TDO_16 => '0',
      Dbg_TDO_17 => '0',
      Dbg_TDO_18 => '0',
      Dbg_TDO_19 => '0',
      Dbg_TDO_2 => '0',
      Dbg_TDO_20 => '0',
      Dbg_TDO_21 => '0',
      Dbg_TDO_22 => '0',
      Dbg_TDO_23 => '0',
      Dbg_TDO_24 => '0',
      Dbg_TDO_25 => '0',
      Dbg_TDO_26 => '0',
      Dbg_TDO_27 => '0',
      Dbg_TDO_28 => '0',
      Dbg_TDO_29 => '0',
      Dbg_TDO_3 => '0',
      Dbg_TDO_30 => '0',
      Dbg_TDO_31 => '0',
      Dbg_TDO_4 => '0',
      Dbg_TDO_5 => '0',
      Dbg_TDO_6 => '0',
      Dbg_TDO_7 => '0',
      Dbg_TDO_8 => '0',
      Dbg_TDO_9 => '0',
      Dbg_TrClk_0 => NLW_U0_Dbg_TrClk_0_UNCONNECTED,
      Dbg_TrClk_1 => NLW_U0_Dbg_TrClk_1_UNCONNECTED,
      Dbg_TrClk_10 => NLW_U0_Dbg_TrClk_10_UNCONNECTED,
      Dbg_TrClk_11 => NLW_U0_Dbg_TrClk_11_UNCONNECTED,
      Dbg_TrClk_12 => NLW_U0_Dbg_TrClk_12_UNCONNECTED,
      Dbg_TrClk_13 => NLW_U0_Dbg_TrClk_13_UNCONNECTED,
      Dbg_TrClk_14 => NLW_U0_Dbg_TrClk_14_UNCONNECTED,
      Dbg_TrClk_15 => NLW_U0_Dbg_TrClk_15_UNCONNECTED,
      Dbg_TrClk_16 => NLW_U0_Dbg_TrClk_16_UNCONNECTED,
      Dbg_TrClk_17 => NLW_U0_Dbg_TrClk_17_UNCONNECTED,
      Dbg_TrClk_18 => NLW_U0_Dbg_TrClk_18_UNCONNECTED,
      Dbg_TrClk_19 => NLW_U0_Dbg_TrClk_19_UNCONNECTED,
      Dbg_TrClk_2 => NLW_U0_Dbg_TrClk_2_UNCONNECTED,
      Dbg_TrClk_20 => NLW_U0_Dbg_TrClk_20_UNCONNECTED,
      Dbg_TrClk_21 => NLW_U0_Dbg_TrClk_21_UNCONNECTED,
      Dbg_TrClk_22 => NLW_U0_Dbg_TrClk_22_UNCONNECTED,
      Dbg_TrClk_23 => NLW_U0_Dbg_TrClk_23_UNCONNECTED,
      Dbg_TrClk_24 => NLW_U0_Dbg_TrClk_24_UNCONNECTED,
      Dbg_TrClk_25 => NLW_U0_Dbg_TrClk_25_UNCONNECTED,
      Dbg_TrClk_26 => NLW_U0_Dbg_TrClk_26_UNCONNECTED,
      Dbg_TrClk_27 => NLW_U0_Dbg_TrClk_27_UNCONNECTED,
      Dbg_TrClk_28 => NLW_U0_Dbg_TrClk_28_UNCONNECTED,
      Dbg_TrClk_29 => NLW_U0_Dbg_TrClk_29_UNCONNECTED,
      Dbg_TrClk_3 => NLW_U0_Dbg_TrClk_3_UNCONNECTED,
      Dbg_TrClk_30 => NLW_U0_Dbg_TrClk_30_UNCONNECTED,
      Dbg_TrClk_31 => NLW_U0_Dbg_TrClk_31_UNCONNECTED,
      Dbg_TrClk_4 => NLW_U0_Dbg_TrClk_4_UNCONNECTED,
      Dbg_TrClk_5 => NLW_U0_Dbg_TrClk_5_UNCONNECTED,
      Dbg_TrClk_6 => NLW_U0_Dbg_TrClk_6_UNCONNECTED,
      Dbg_TrClk_7 => NLW_U0_Dbg_TrClk_7_UNCONNECTED,
      Dbg_TrClk_8 => NLW_U0_Dbg_TrClk_8_UNCONNECTED,
      Dbg_TrClk_9 => NLW_U0_Dbg_TrClk_9_UNCONNECTED,
      Dbg_TrData_0(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_1(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_10(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_11(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_12(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_13(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_14(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_15(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_16(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_17(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_18(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_19(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_2(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_20(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_21(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_22(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_23(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_24(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_25(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_26(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_27(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_28(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_29(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_3(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_30(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_31(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_4(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_5(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_6(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_7(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_8(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrData_9(0 to 35) => B"000000000000000000000000000000000000",
      Dbg_TrReady_0 => NLW_U0_Dbg_TrReady_0_UNCONNECTED,
      Dbg_TrReady_1 => NLW_U0_Dbg_TrReady_1_UNCONNECTED,
      Dbg_TrReady_10 => NLW_U0_Dbg_TrReady_10_UNCONNECTED,
      Dbg_TrReady_11 => NLW_U0_Dbg_TrReady_11_UNCONNECTED,
      Dbg_TrReady_12 => NLW_U0_Dbg_TrReady_12_UNCONNECTED,
      Dbg_TrReady_13 => NLW_U0_Dbg_TrReady_13_UNCONNECTED,
      Dbg_TrReady_14 => NLW_U0_Dbg_TrReady_14_UNCONNECTED,
      Dbg_TrReady_15 => NLW_U0_Dbg_TrReady_15_UNCONNECTED,
      Dbg_TrReady_16 => NLW_U0_Dbg_TrReady_16_UNCONNECTED,
      Dbg_TrReady_17 => NLW_U0_Dbg_TrReady_17_UNCONNECTED,
      Dbg_TrReady_18 => NLW_U0_Dbg_TrReady_18_UNCONNECTED,
      Dbg_TrReady_19 => NLW_U0_Dbg_TrReady_19_UNCONNECTED,
      Dbg_TrReady_2 => NLW_U0_Dbg_TrReady_2_UNCONNECTED,
      Dbg_TrReady_20 => NLW_U0_Dbg_TrReady_20_UNCONNECTED,
      Dbg_TrReady_21 => NLW_U0_Dbg_TrReady_21_UNCONNECTED,
      Dbg_TrReady_22 => NLW_U0_Dbg_TrReady_22_UNCONNECTED,
      Dbg_TrReady_23 => NLW_U0_Dbg_TrReady_23_UNCONNECTED,
      Dbg_TrReady_24 => NLW_U0_Dbg_TrReady_24_UNCONNECTED,
      Dbg_TrReady_25 => NLW_U0_Dbg_TrReady_25_UNCONNECTED,
      Dbg_TrReady_26 => NLW_U0_Dbg_TrReady_26_UNCONNECTED,
      Dbg_TrReady_27 => NLW_U0_Dbg_TrReady_27_UNCONNECTED,
      Dbg_TrReady_28 => NLW_U0_Dbg_TrReady_28_UNCONNECTED,
      Dbg_TrReady_29 => NLW_U0_Dbg_TrReady_29_UNCONNECTED,
      Dbg_TrReady_3 => NLW_U0_Dbg_TrReady_3_UNCONNECTED,
      Dbg_TrReady_30 => NLW_U0_Dbg_TrReady_30_UNCONNECTED,
      Dbg_TrReady_31 => NLW_U0_Dbg_TrReady_31_UNCONNECTED,
      Dbg_TrReady_4 => NLW_U0_Dbg_TrReady_4_UNCONNECTED,
      Dbg_TrReady_5 => NLW_U0_Dbg_TrReady_5_UNCONNECTED,
      Dbg_TrReady_6 => NLW_U0_Dbg_TrReady_6_UNCONNECTED,
      Dbg_TrReady_7 => NLW_U0_Dbg_TrReady_7_UNCONNECTED,
      Dbg_TrReady_8 => NLW_U0_Dbg_TrReady_8_UNCONNECTED,
      Dbg_TrReady_9 => NLW_U0_Dbg_TrReady_9_UNCONNECTED,
      Dbg_TrValid_0 => '0',
      Dbg_TrValid_1 => '0',
      Dbg_TrValid_10 => '0',
      Dbg_TrValid_11 => '0',
      Dbg_TrValid_12 => '0',
      Dbg_TrValid_13 => '0',
      Dbg_TrValid_14 => '0',
      Dbg_TrValid_15 => '0',
      Dbg_TrValid_16 => '0',
      Dbg_TrValid_17 => '0',
      Dbg_TrValid_18 => '0',
      Dbg_TrValid_19 => '0',
      Dbg_TrValid_2 => '0',
      Dbg_TrValid_20 => '0',
      Dbg_TrValid_21 => '0',
      Dbg_TrValid_22 => '0',
      Dbg_TrValid_23 => '0',
      Dbg_TrValid_24 => '0',
      Dbg_TrValid_25 => '0',
      Dbg_TrValid_26 => '0',
      Dbg_TrValid_27 => '0',
      Dbg_TrValid_28 => '0',
      Dbg_TrValid_29 => '0',
      Dbg_TrValid_3 => '0',
      Dbg_TrValid_30 => '0',
      Dbg_TrValid_31 => '0',
      Dbg_TrValid_4 => '0',
      Dbg_TrValid_5 => '0',
      Dbg_TrValid_6 => '0',
      Dbg_TrValid_7 => '0',
      Dbg_TrValid_8 => '0',
      Dbg_TrValid_9 => '0',
      Dbg_Trig_Ack_In_0(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_1(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_10(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_11(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_12(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_13(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_14(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_15(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_16(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_17(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_18(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_19(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_2(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_20(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_21(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_22(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_23(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_24(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_25(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_26(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_27(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_28(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_29(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_3(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_30(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_31(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_4(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_5(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_6(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_7(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_8(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_In_9(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED(0 to 7),
      Dbg_Trig_Ack_Out_0(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_1(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_10(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_11(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_12(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_13(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_14(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_15(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_16(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_17(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_18(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_19(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_2(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_20(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_21(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_22(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_23(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_24(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_25(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_26(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_27(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_28(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_29(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_3(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_30(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_31(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_4(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_5(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_6(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_7(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_8(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out_9(0 to 7) => B"00000000",
      Dbg_Trig_In_0(0 to 7) => B"00000000",
      Dbg_Trig_In_1(0 to 7) => B"00000000",
      Dbg_Trig_In_10(0 to 7) => B"00000000",
      Dbg_Trig_In_11(0 to 7) => B"00000000",
      Dbg_Trig_In_12(0 to 7) => B"00000000",
      Dbg_Trig_In_13(0 to 7) => B"00000000",
      Dbg_Trig_In_14(0 to 7) => B"00000000",
      Dbg_Trig_In_15(0 to 7) => B"00000000",
      Dbg_Trig_In_16(0 to 7) => B"00000000",
      Dbg_Trig_In_17(0 to 7) => B"00000000",
      Dbg_Trig_In_18(0 to 7) => B"00000000",
      Dbg_Trig_In_19(0 to 7) => B"00000000",
      Dbg_Trig_In_2(0 to 7) => B"00000000",
      Dbg_Trig_In_20(0 to 7) => B"00000000",
      Dbg_Trig_In_21(0 to 7) => B"00000000",
      Dbg_Trig_In_22(0 to 7) => B"00000000",
      Dbg_Trig_In_23(0 to 7) => B"00000000",
      Dbg_Trig_In_24(0 to 7) => B"00000000",
      Dbg_Trig_In_25(0 to 7) => B"00000000",
      Dbg_Trig_In_26(0 to 7) => B"00000000",
      Dbg_Trig_In_27(0 to 7) => B"00000000",
      Dbg_Trig_In_28(0 to 7) => B"00000000",
      Dbg_Trig_In_29(0 to 7) => B"00000000",
      Dbg_Trig_In_3(0 to 7) => B"00000000",
      Dbg_Trig_In_30(0 to 7) => B"00000000",
      Dbg_Trig_In_31(0 to 7) => B"00000000",
      Dbg_Trig_In_4(0 to 7) => B"00000000",
      Dbg_Trig_In_5(0 to 7) => B"00000000",
      Dbg_Trig_In_6(0 to 7) => B"00000000",
      Dbg_Trig_In_7(0 to 7) => B"00000000",
      Dbg_Trig_In_8(0 to 7) => B"00000000",
      Dbg_Trig_In_9(0 to 7) => B"00000000",
      Dbg_Trig_Out_0(0 to 7) => NLW_U0_Dbg_Trig_Out_0_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_1(0 to 7) => NLW_U0_Dbg_Trig_Out_1_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_10(0 to 7) => NLW_U0_Dbg_Trig_Out_10_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_11(0 to 7) => NLW_U0_Dbg_Trig_Out_11_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_12(0 to 7) => NLW_U0_Dbg_Trig_Out_12_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_13(0 to 7) => NLW_U0_Dbg_Trig_Out_13_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_14(0 to 7) => NLW_U0_Dbg_Trig_Out_14_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_15(0 to 7) => NLW_U0_Dbg_Trig_Out_15_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_16(0 to 7) => NLW_U0_Dbg_Trig_Out_16_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_17(0 to 7) => NLW_U0_Dbg_Trig_Out_17_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_18(0 to 7) => NLW_U0_Dbg_Trig_Out_18_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_19(0 to 7) => NLW_U0_Dbg_Trig_Out_19_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_2(0 to 7) => NLW_U0_Dbg_Trig_Out_2_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_20(0 to 7) => NLW_U0_Dbg_Trig_Out_20_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_21(0 to 7) => NLW_U0_Dbg_Trig_Out_21_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_22(0 to 7) => NLW_U0_Dbg_Trig_Out_22_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_23(0 to 7) => NLW_U0_Dbg_Trig_Out_23_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_24(0 to 7) => NLW_U0_Dbg_Trig_Out_24_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_25(0 to 7) => NLW_U0_Dbg_Trig_Out_25_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_26(0 to 7) => NLW_U0_Dbg_Trig_Out_26_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_27(0 to 7) => NLW_U0_Dbg_Trig_Out_27_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_28(0 to 7) => NLW_U0_Dbg_Trig_Out_28_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_29(0 to 7) => NLW_U0_Dbg_Trig_Out_29_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_3(0 to 7) => NLW_U0_Dbg_Trig_Out_3_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_30(0 to 7) => NLW_U0_Dbg_Trig_Out_30_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_31(0 to 7) => NLW_U0_Dbg_Trig_Out_31_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_4(0 to 7) => NLW_U0_Dbg_Trig_Out_4_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_5(0 to 7) => NLW_U0_Dbg_Trig_Out_5_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_6(0 to 7) => NLW_U0_Dbg_Trig_Out_6_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_7(0 to 7) => NLW_U0_Dbg_Trig_Out_7_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_8(0 to 7) => NLW_U0_Dbg_Trig_Out_8_UNCONNECTED(0 to 7),
      Dbg_Trig_Out_9(0 to 7) => NLW_U0_Dbg_Trig_Out_9_UNCONNECTED(0 to 7),
      Dbg_Update_0 => Dbg_Update_0,
      Dbg_Update_1 => NLW_U0_Dbg_Update_1_UNCONNECTED,
      Dbg_Update_10 => NLW_U0_Dbg_Update_10_UNCONNECTED,
      Dbg_Update_11 => NLW_U0_Dbg_Update_11_UNCONNECTED,
      Dbg_Update_12 => NLW_U0_Dbg_Update_12_UNCONNECTED,
      Dbg_Update_13 => NLW_U0_Dbg_Update_13_UNCONNECTED,
      Dbg_Update_14 => NLW_U0_Dbg_Update_14_UNCONNECTED,
      Dbg_Update_15 => NLW_U0_Dbg_Update_15_UNCONNECTED,
      Dbg_Update_16 => NLW_U0_Dbg_Update_16_UNCONNECTED,
      Dbg_Update_17 => NLW_U0_Dbg_Update_17_UNCONNECTED,
      Dbg_Update_18 => NLW_U0_Dbg_Update_18_UNCONNECTED,
      Dbg_Update_19 => NLW_U0_Dbg_Update_19_UNCONNECTED,
      Dbg_Update_2 => NLW_U0_Dbg_Update_2_UNCONNECTED,
      Dbg_Update_20 => NLW_U0_Dbg_Update_20_UNCONNECTED,
      Dbg_Update_21 => NLW_U0_Dbg_Update_21_UNCONNECTED,
      Dbg_Update_22 => NLW_U0_Dbg_Update_22_UNCONNECTED,
      Dbg_Update_23 => NLW_U0_Dbg_Update_23_UNCONNECTED,
      Dbg_Update_24 => NLW_U0_Dbg_Update_24_UNCONNECTED,
      Dbg_Update_25 => NLW_U0_Dbg_Update_25_UNCONNECTED,
      Dbg_Update_26 => NLW_U0_Dbg_Update_26_UNCONNECTED,
      Dbg_Update_27 => NLW_U0_Dbg_Update_27_UNCONNECTED,
      Dbg_Update_28 => NLW_U0_Dbg_Update_28_UNCONNECTED,
      Dbg_Update_29 => NLW_U0_Dbg_Update_29_UNCONNECTED,
      Dbg_Update_3 => NLW_U0_Dbg_Update_3_UNCONNECTED,
      Dbg_Update_30 => NLW_U0_Dbg_Update_30_UNCONNECTED,
      Dbg_Update_31 => NLW_U0_Dbg_Update_31_UNCONNECTED,
      Dbg_Update_4 => NLW_U0_Dbg_Update_4_UNCONNECTED,
      Dbg_Update_5 => NLW_U0_Dbg_Update_5_UNCONNECTED,
      Dbg_Update_6 => NLW_U0_Dbg_Update_6_UNCONNECTED,
      Dbg_Update_7 => NLW_U0_Dbg_Update_7_UNCONNECTED,
      Dbg_Update_8 => NLW_U0_Dbg_Update_8_UNCONNECTED,
      Dbg_Update_9 => NLW_U0_Dbg_Update_9_UNCONNECTED,
      Dbg_WDATA_0(31 downto 0) => NLW_U0_Dbg_WDATA_0_UNCONNECTED(31 downto 0),
      Dbg_WDATA_1(31 downto 0) => NLW_U0_Dbg_WDATA_1_UNCONNECTED(31 downto 0),
      Dbg_WDATA_10(31 downto 0) => NLW_U0_Dbg_WDATA_10_UNCONNECTED(31 downto 0),
      Dbg_WDATA_11(31 downto 0) => NLW_U0_Dbg_WDATA_11_UNCONNECTED(31 downto 0),
      Dbg_WDATA_12(31 downto 0) => NLW_U0_Dbg_WDATA_12_UNCONNECTED(31 downto 0),
      Dbg_WDATA_13(31 downto 0) => NLW_U0_Dbg_WDATA_13_UNCONNECTED(31 downto 0),
      Dbg_WDATA_14(31 downto 0) => NLW_U0_Dbg_WDATA_14_UNCONNECTED(31 downto 0),
      Dbg_WDATA_15(31 downto 0) => NLW_U0_Dbg_WDATA_15_UNCONNECTED(31 downto 0),
      Dbg_WDATA_16(31 downto 0) => NLW_U0_Dbg_WDATA_16_UNCONNECTED(31 downto 0),
      Dbg_WDATA_17(31 downto 0) => NLW_U0_Dbg_WDATA_17_UNCONNECTED(31 downto 0),
      Dbg_WDATA_18(31 downto 0) => NLW_U0_Dbg_WDATA_18_UNCONNECTED(31 downto 0),
      Dbg_WDATA_19(31 downto 0) => NLW_U0_Dbg_WDATA_19_UNCONNECTED(31 downto 0),
      Dbg_WDATA_2(31 downto 0) => NLW_U0_Dbg_WDATA_2_UNCONNECTED(31 downto 0),
      Dbg_WDATA_20(31 downto 0) => NLW_U0_Dbg_WDATA_20_UNCONNECTED(31 downto 0),
      Dbg_WDATA_21(31 downto 0) => NLW_U0_Dbg_WDATA_21_UNCONNECTED(31 downto 0),
      Dbg_WDATA_22(31 downto 0) => NLW_U0_Dbg_WDATA_22_UNCONNECTED(31 downto 0),
      Dbg_WDATA_23(31 downto 0) => NLW_U0_Dbg_WDATA_23_UNCONNECTED(31 downto 0),
      Dbg_WDATA_24(31 downto 0) => NLW_U0_Dbg_WDATA_24_UNCONNECTED(31 downto 0),
      Dbg_WDATA_25(31 downto 0) => NLW_U0_Dbg_WDATA_25_UNCONNECTED(31 downto 0),
      Dbg_WDATA_26(31 downto 0) => NLW_U0_Dbg_WDATA_26_UNCONNECTED(31 downto 0),
      Dbg_WDATA_27(31 downto 0) => NLW_U0_Dbg_WDATA_27_UNCONNECTED(31 downto 0),
      Dbg_WDATA_28(31 downto 0) => NLW_U0_Dbg_WDATA_28_UNCONNECTED(31 downto 0),
      Dbg_WDATA_29(31 downto 0) => NLW_U0_Dbg_WDATA_29_UNCONNECTED(31 downto 0),
      Dbg_WDATA_3(31 downto 0) => NLW_U0_Dbg_WDATA_3_UNCONNECTED(31 downto 0),
      Dbg_WDATA_30(31 downto 0) => NLW_U0_Dbg_WDATA_30_UNCONNECTED(31 downto 0),
      Dbg_WDATA_31(31 downto 0) => NLW_U0_Dbg_WDATA_31_UNCONNECTED(31 downto 0),
      Dbg_WDATA_4(31 downto 0) => NLW_U0_Dbg_WDATA_4_UNCONNECTED(31 downto 0),
      Dbg_WDATA_5(31 downto 0) => NLW_U0_Dbg_WDATA_5_UNCONNECTED(31 downto 0),
      Dbg_WDATA_6(31 downto 0) => NLW_U0_Dbg_WDATA_6_UNCONNECTED(31 downto 0),
      Dbg_WDATA_7(31 downto 0) => NLW_U0_Dbg_WDATA_7_UNCONNECTED(31 downto 0),
      Dbg_WDATA_8(31 downto 0) => NLW_U0_Dbg_WDATA_8_UNCONNECTED(31 downto 0),
      Dbg_WDATA_9(31 downto 0) => NLW_U0_Dbg_WDATA_9_UNCONNECTED(31 downto 0),
      Dbg_WREADY_0 => '0',
      Dbg_WREADY_1 => '0',
      Dbg_WREADY_10 => '0',
      Dbg_WREADY_11 => '0',
      Dbg_WREADY_12 => '0',
      Dbg_WREADY_13 => '0',
      Dbg_WREADY_14 => '0',
      Dbg_WREADY_15 => '0',
      Dbg_WREADY_16 => '0',
      Dbg_WREADY_17 => '0',
      Dbg_WREADY_18 => '0',
      Dbg_WREADY_19 => '0',
      Dbg_WREADY_2 => '0',
      Dbg_WREADY_20 => '0',
      Dbg_WREADY_21 => '0',
      Dbg_WREADY_22 => '0',
      Dbg_WREADY_23 => '0',
      Dbg_WREADY_24 => '0',
      Dbg_WREADY_25 => '0',
      Dbg_WREADY_26 => '0',
      Dbg_WREADY_27 => '0',
      Dbg_WREADY_28 => '0',
      Dbg_WREADY_29 => '0',
      Dbg_WREADY_3 => '0',
      Dbg_WREADY_30 => '0',
      Dbg_WREADY_31 => '0',
      Dbg_WREADY_4 => '0',
      Dbg_WREADY_5 => '0',
      Dbg_WREADY_6 => '0',
      Dbg_WREADY_7 => '0',
      Dbg_WREADY_8 => '0',
      Dbg_WREADY_9 => '0',
      Dbg_WVALID_0 => NLW_U0_Dbg_WVALID_0_UNCONNECTED,
      Dbg_WVALID_1 => NLW_U0_Dbg_WVALID_1_UNCONNECTED,
      Dbg_WVALID_10 => NLW_U0_Dbg_WVALID_10_UNCONNECTED,
      Dbg_WVALID_11 => NLW_U0_Dbg_WVALID_11_UNCONNECTED,
      Dbg_WVALID_12 => NLW_U0_Dbg_WVALID_12_UNCONNECTED,
      Dbg_WVALID_13 => NLW_U0_Dbg_WVALID_13_UNCONNECTED,
      Dbg_WVALID_14 => NLW_U0_Dbg_WVALID_14_UNCONNECTED,
      Dbg_WVALID_15 => NLW_U0_Dbg_WVALID_15_UNCONNECTED,
      Dbg_WVALID_16 => NLW_U0_Dbg_WVALID_16_UNCONNECTED,
      Dbg_WVALID_17 => NLW_U0_Dbg_WVALID_17_UNCONNECTED,
      Dbg_WVALID_18 => NLW_U0_Dbg_WVALID_18_UNCONNECTED,
      Dbg_WVALID_19 => NLW_U0_Dbg_WVALID_19_UNCONNECTED,
      Dbg_WVALID_2 => NLW_U0_Dbg_WVALID_2_UNCONNECTED,
      Dbg_WVALID_20 => NLW_U0_Dbg_WVALID_20_UNCONNECTED,
      Dbg_WVALID_21 => NLW_U0_Dbg_WVALID_21_UNCONNECTED,
      Dbg_WVALID_22 => NLW_U0_Dbg_WVALID_22_UNCONNECTED,
      Dbg_WVALID_23 => NLW_U0_Dbg_WVALID_23_UNCONNECTED,
      Dbg_WVALID_24 => NLW_U0_Dbg_WVALID_24_UNCONNECTED,
      Dbg_WVALID_25 => NLW_U0_Dbg_WVALID_25_UNCONNECTED,
      Dbg_WVALID_26 => NLW_U0_Dbg_WVALID_26_UNCONNECTED,
      Dbg_WVALID_27 => NLW_U0_Dbg_WVALID_27_UNCONNECTED,
      Dbg_WVALID_28 => NLW_U0_Dbg_WVALID_28_UNCONNECTED,
      Dbg_WVALID_29 => NLW_U0_Dbg_WVALID_29_UNCONNECTED,
      Dbg_WVALID_3 => NLW_U0_Dbg_WVALID_3_UNCONNECTED,
      Dbg_WVALID_30 => NLW_U0_Dbg_WVALID_30_UNCONNECTED,
      Dbg_WVALID_31 => NLW_U0_Dbg_WVALID_31_UNCONNECTED,
      Dbg_WVALID_4 => NLW_U0_Dbg_WVALID_4_UNCONNECTED,
      Dbg_WVALID_5 => NLW_U0_Dbg_WVALID_5_UNCONNECTED,
      Dbg_WVALID_6 => NLW_U0_Dbg_WVALID_6_UNCONNECTED,
      Dbg_WVALID_7 => NLW_U0_Dbg_WVALID_7_UNCONNECTED,
      Dbg_WVALID_8 => NLW_U0_Dbg_WVALID_8_UNCONNECTED,
      Dbg_WVALID_9 => NLW_U0_Dbg_WVALID_9_UNCONNECTED,
      Debug_SYS_Rst => Debug_SYS_Rst,
      Ext_BRK => NLW_U0_Ext_BRK_UNCONNECTED,
      Ext_JTAG_CAPTURE => NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED,
      Ext_JTAG_DRCK => NLW_U0_Ext_JTAG_DRCK_UNCONNECTED,
      Ext_JTAG_RESET => NLW_U0_Ext_JTAG_RESET_UNCONNECTED,
      Ext_JTAG_SEL => NLW_U0_Ext_JTAG_SEL_UNCONNECTED,
      Ext_JTAG_SHIFT => NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED,
      Ext_JTAG_TDI => NLW_U0_Ext_JTAG_TDI_UNCONNECTED,
      Ext_JTAG_TDO => '0',
      Ext_JTAG_UPDATE => NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED,
      Ext_NM_BRK => NLW_U0_Ext_NM_BRK_UNCONNECTED,
      Interrupt => NLW_U0_Interrupt_UNCONNECTED,
      LMB_Addr_Strobe_0 => NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED,
      LMB_Addr_Strobe_1 => NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED,
      LMB_Addr_Strobe_10 => NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED,
      LMB_Addr_Strobe_11 => NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED,
      LMB_Addr_Strobe_12 => NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED,
      LMB_Addr_Strobe_13 => NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED,
      LMB_Addr_Strobe_14 => NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED,
      LMB_Addr_Strobe_15 => NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED,
      LMB_Addr_Strobe_16 => NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED,
      LMB_Addr_Strobe_17 => NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED,
      LMB_Addr_Strobe_18 => NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED,
      LMB_Addr_Strobe_19 => NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED,
      LMB_Addr_Strobe_2 => NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED,
      LMB_Addr_Strobe_20 => NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED,
      LMB_Addr_Strobe_21 => NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED,
      LMB_Addr_Strobe_22 => NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED,
      LMB_Addr_Strobe_23 => NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED,
      LMB_Addr_Strobe_24 => NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED,
      LMB_Addr_Strobe_25 => NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED,
      LMB_Addr_Strobe_26 => NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED,
      LMB_Addr_Strobe_27 => NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED,
      LMB_Addr_Strobe_28 => NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED,
      LMB_Addr_Strobe_29 => NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED,
      LMB_Addr_Strobe_3 => NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED,
      LMB_Addr_Strobe_30 => NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED,
      LMB_Addr_Strobe_31 => NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED,
      LMB_Addr_Strobe_4 => NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED,
      LMB_Addr_Strobe_5 => NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED,
      LMB_Addr_Strobe_6 => NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED,
      LMB_Addr_Strobe_7 => NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED,
      LMB_Addr_Strobe_8 => NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED,
      LMB_Addr_Strobe_9 => NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED,
      LMB_Byte_Enable_0(0 to 3) => NLW_U0_LMB_Byte_Enable_0_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_1(0 to 3) => NLW_U0_LMB_Byte_Enable_1_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_10(0 to 3) => NLW_U0_LMB_Byte_Enable_10_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_11(0 to 3) => NLW_U0_LMB_Byte_Enable_11_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_12(0 to 3) => NLW_U0_LMB_Byte_Enable_12_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_13(0 to 3) => NLW_U0_LMB_Byte_Enable_13_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_14(0 to 3) => NLW_U0_LMB_Byte_Enable_14_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_15(0 to 3) => NLW_U0_LMB_Byte_Enable_15_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_16(0 to 3) => NLW_U0_LMB_Byte_Enable_16_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_17(0 to 3) => NLW_U0_LMB_Byte_Enable_17_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_18(0 to 3) => NLW_U0_LMB_Byte_Enable_18_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_19(0 to 3) => NLW_U0_LMB_Byte_Enable_19_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_2(0 to 3) => NLW_U0_LMB_Byte_Enable_2_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_20(0 to 3) => NLW_U0_LMB_Byte_Enable_20_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_21(0 to 3) => NLW_U0_LMB_Byte_Enable_21_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_22(0 to 3) => NLW_U0_LMB_Byte_Enable_22_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_23(0 to 3) => NLW_U0_LMB_Byte_Enable_23_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_24(0 to 3) => NLW_U0_LMB_Byte_Enable_24_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_25(0 to 3) => NLW_U0_LMB_Byte_Enable_25_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_26(0 to 3) => NLW_U0_LMB_Byte_Enable_26_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_27(0 to 3) => NLW_U0_LMB_Byte_Enable_27_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_28(0 to 3) => NLW_U0_LMB_Byte_Enable_28_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_29(0 to 3) => NLW_U0_LMB_Byte_Enable_29_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_3(0 to 3) => NLW_U0_LMB_Byte_Enable_3_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_30(0 to 3) => NLW_U0_LMB_Byte_Enable_30_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_31(0 to 3) => NLW_U0_LMB_Byte_Enable_31_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_4(0 to 3) => NLW_U0_LMB_Byte_Enable_4_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_5(0 to 3) => NLW_U0_LMB_Byte_Enable_5_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_6(0 to 3) => NLW_U0_LMB_Byte_Enable_6_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_7(0 to 3) => NLW_U0_LMB_Byte_Enable_7_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_8(0 to 3) => NLW_U0_LMB_Byte_Enable_8_UNCONNECTED(0 to 3),
      LMB_Byte_Enable_9(0 to 3) => NLW_U0_LMB_Byte_Enable_9_UNCONNECTED(0 to 3),
      LMB_CE_0 => '0',
      LMB_CE_1 => '0',
      LMB_CE_10 => '0',
      LMB_CE_11 => '0',
      LMB_CE_12 => '0',
      LMB_CE_13 => '0',
      LMB_CE_14 => '0',
      LMB_CE_15 => '0',
      LMB_CE_16 => '0',
      LMB_CE_17 => '0',
      LMB_CE_18 => '0',
      LMB_CE_19 => '0',
      LMB_CE_2 => '0',
      LMB_CE_20 => '0',
      LMB_CE_21 => '0',
      LMB_CE_22 => '0',
      LMB_CE_23 => '0',
      LMB_CE_24 => '0',
      LMB_CE_25 => '0',
      LMB_CE_26 => '0',
      LMB_CE_27 => '0',
      LMB_CE_28 => '0',
      LMB_CE_29 => '0',
      LMB_CE_3 => '0',
      LMB_CE_30 => '0',
      LMB_CE_31 => '0',
      LMB_CE_4 => '0',
      LMB_CE_5 => '0',
      LMB_CE_6 => '0',
      LMB_CE_7 => '0',
      LMB_CE_8 => '0',
      LMB_CE_9 => '0',
      LMB_Data_Addr_0(0 to 31) => NLW_U0_LMB_Data_Addr_0_UNCONNECTED(0 to 31),
      LMB_Data_Addr_1(0 to 31) => NLW_U0_LMB_Data_Addr_1_UNCONNECTED(0 to 31),
      LMB_Data_Addr_10(0 to 31) => NLW_U0_LMB_Data_Addr_10_UNCONNECTED(0 to 31),
      LMB_Data_Addr_11(0 to 31) => NLW_U0_LMB_Data_Addr_11_UNCONNECTED(0 to 31),
      LMB_Data_Addr_12(0 to 31) => NLW_U0_LMB_Data_Addr_12_UNCONNECTED(0 to 31),
      LMB_Data_Addr_13(0 to 31) => NLW_U0_LMB_Data_Addr_13_UNCONNECTED(0 to 31),
      LMB_Data_Addr_14(0 to 31) => NLW_U0_LMB_Data_Addr_14_UNCONNECTED(0 to 31),
      LMB_Data_Addr_15(0 to 31) => NLW_U0_LMB_Data_Addr_15_UNCONNECTED(0 to 31),
      LMB_Data_Addr_16(0 to 31) => NLW_U0_LMB_Data_Addr_16_UNCONNECTED(0 to 31),
      LMB_Data_Addr_17(0 to 31) => NLW_U0_LMB_Data_Addr_17_UNCONNECTED(0 to 31),
      LMB_Data_Addr_18(0 to 31) => NLW_U0_LMB_Data_Addr_18_UNCONNECTED(0 to 31),
      LMB_Data_Addr_19(0 to 31) => NLW_U0_LMB_Data_Addr_19_UNCONNECTED(0 to 31),
      LMB_Data_Addr_2(0 to 31) => NLW_U0_LMB_Data_Addr_2_UNCONNECTED(0 to 31),
      LMB_Data_Addr_20(0 to 31) => NLW_U0_LMB_Data_Addr_20_UNCONNECTED(0 to 31),
      LMB_Data_Addr_21(0 to 31) => NLW_U0_LMB_Data_Addr_21_UNCONNECTED(0 to 31),
      LMB_Data_Addr_22(0 to 31) => NLW_U0_LMB_Data_Addr_22_UNCONNECTED(0 to 31),
      LMB_Data_Addr_23(0 to 31) => NLW_U0_LMB_Data_Addr_23_UNCONNECTED(0 to 31),
      LMB_Data_Addr_24(0 to 31) => NLW_U0_LMB_Data_Addr_24_UNCONNECTED(0 to 31),
      LMB_Data_Addr_25(0 to 31) => NLW_U0_LMB_Data_Addr_25_UNCONNECTED(0 to 31),
      LMB_Data_Addr_26(0 to 31) => NLW_U0_LMB_Data_Addr_26_UNCONNECTED(0 to 31),
      LMB_Data_Addr_27(0 to 31) => NLW_U0_LMB_Data_Addr_27_UNCONNECTED(0 to 31),
      LMB_Data_Addr_28(0 to 31) => NLW_U0_LMB_Data_Addr_28_UNCONNECTED(0 to 31),
      LMB_Data_Addr_29(0 to 31) => NLW_U0_LMB_Data_Addr_29_UNCONNECTED(0 to 31),
      LMB_Data_Addr_3(0 to 31) => NLW_U0_LMB_Data_Addr_3_UNCONNECTED(0 to 31),
      LMB_Data_Addr_30(0 to 31) => NLW_U0_LMB_Data_Addr_30_UNCONNECTED(0 to 31),
      LMB_Data_Addr_31(0 to 31) => NLW_U0_LMB_Data_Addr_31_UNCONNECTED(0 to 31),
      LMB_Data_Addr_4(0 to 31) => NLW_U0_LMB_Data_Addr_4_UNCONNECTED(0 to 31),
      LMB_Data_Addr_5(0 to 31) => NLW_U0_LMB_Data_Addr_5_UNCONNECTED(0 to 31),
      LMB_Data_Addr_6(0 to 31) => NLW_U0_LMB_Data_Addr_6_UNCONNECTED(0 to 31),
      LMB_Data_Addr_7(0 to 31) => NLW_U0_LMB_Data_Addr_7_UNCONNECTED(0 to 31),
      LMB_Data_Addr_8(0 to 31) => NLW_U0_LMB_Data_Addr_8_UNCONNECTED(0 to 31),
      LMB_Data_Addr_9(0 to 31) => NLW_U0_LMB_Data_Addr_9_UNCONNECTED(0 to 31),
      LMB_Data_Read_0(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_1(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_10(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_11(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_12(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_13(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_14(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_15(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_16(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_17(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_18(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_19(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_2(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_20(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_21(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_22(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_23(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_24(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_25(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_26(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_27(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_28(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_29(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_3(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_30(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_31(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_4(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_5(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_6(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_7(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_8(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Read_9(0 to 31) => B"00000000000000000000000000000000",
      LMB_Data_Write_0(0 to 31) => NLW_U0_LMB_Data_Write_0_UNCONNECTED(0 to 31),
      LMB_Data_Write_1(0 to 31) => NLW_U0_LMB_Data_Write_1_UNCONNECTED(0 to 31),
      LMB_Data_Write_10(0 to 31) => NLW_U0_LMB_Data_Write_10_UNCONNECTED(0 to 31),
      LMB_Data_Write_11(0 to 31) => NLW_U0_LMB_Data_Write_11_UNCONNECTED(0 to 31),
      LMB_Data_Write_12(0 to 31) => NLW_U0_LMB_Data_Write_12_UNCONNECTED(0 to 31),
      LMB_Data_Write_13(0 to 31) => NLW_U0_LMB_Data_Write_13_UNCONNECTED(0 to 31),
      LMB_Data_Write_14(0 to 31) => NLW_U0_LMB_Data_Write_14_UNCONNECTED(0 to 31),
      LMB_Data_Write_15(0 to 31) => NLW_U0_LMB_Data_Write_15_UNCONNECTED(0 to 31),
      LMB_Data_Write_16(0 to 31) => NLW_U0_LMB_Data_Write_16_UNCONNECTED(0 to 31),
      LMB_Data_Write_17(0 to 31) => NLW_U0_LMB_Data_Write_17_UNCONNECTED(0 to 31),
      LMB_Data_Write_18(0 to 31) => NLW_U0_LMB_Data_Write_18_UNCONNECTED(0 to 31),
      LMB_Data_Write_19(0 to 31) => NLW_U0_LMB_Data_Write_19_UNCONNECTED(0 to 31),
      LMB_Data_Write_2(0 to 31) => NLW_U0_LMB_Data_Write_2_UNCONNECTED(0 to 31),
      LMB_Data_Write_20(0 to 31) => NLW_U0_LMB_Data_Write_20_UNCONNECTED(0 to 31),
      LMB_Data_Write_21(0 to 31) => NLW_U0_LMB_Data_Write_21_UNCONNECTED(0 to 31),
      LMB_Data_Write_22(0 to 31) => NLW_U0_LMB_Data_Write_22_UNCONNECTED(0 to 31),
      LMB_Data_Write_23(0 to 31) => NLW_U0_LMB_Data_Write_23_UNCONNECTED(0 to 31),
      LMB_Data_Write_24(0 to 31) => NLW_U0_LMB_Data_Write_24_UNCONNECTED(0 to 31),
      LMB_Data_Write_25(0 to 31) => NLW_U0_LMB_Data_Write_25_UNCONNECTED(0 to 31),
      LMB_Data_Write_26(0 to 31) => NLW_U0_LMB_Data_Write_26_UNCONNECTED(0 to 31),
      LMB_Data_Write_27(0 to 31) => NLW_U0_LMB_Data_Write_27_UNCONNECTED(0 to 31),
      LMB_Data_Write_28(0 to 31) => NLW_U0_LMB_Data_Write_28_UNCONNECTED(0 to 31),
      LMB_Data_Write_29(0 to 31) => NLW_U0_LMB_Data_Write_29_UNCONNECTED(0 to 31),
      LMB_Data_Write_3(0 to 31) => NLW_U0_LMB_Data_Write_3_UNCONNECTED(0 to 31),
      LMB_Data_Write_30(0 to 31) => NLW_U0_LMB_Data_Write_30_UNCONNECTED(0 to 31),
      LMB_Data_Write_31(0 to 31) => NLW_U0_LMB_Data_Write_31_UNCONNECTED(0 to 31),
      LMB_Data_Write_4(0 to 31) => NLW_U0_LMB_Data_Write_4_UNCONNECTED(0 to 31),
      LMB_Data_Write_5(0 to 31) => NLW_U0_LMB_Data_Write_5_UNCONNECTED(0 to 31),
      LMB_Data_Write_6(0 to 31) => NLW_U0_LMB_Data_Write_6_UNCONNECTED(0 to 31),
      LMB_Data_Write_7(0 to 31) => NLW_U0_LMB_Data_Write_7_UNCONNECTED(0 to 31),
      LMB_Data_Write_8(0 to 31) => NLW_U0_LMB_Data_Write_8_UNCONNECTED(0 to 31),
      LMB_Data_Write_9(0 to 31) => NLW_U0_LMB_Data_Write_9_UNCONNECTED(0 to 31),
      LMB_Read_Strobe_0 => NLW_U0_LMB_Read_Strobe_0_UNCONNECTED,
      LMB_Read_Strobe_1 => NLW_U0_LMB_Read_Strobe_1_UNCONNECTED,
      LMB_Read_Strobe_10 => NLW_U0_LMB_Read_Strobe_10_UNCONNECTED,
      LMB_Read_Strobe_11 => NLW_U0_LMB_Read_Strobe_11_UNCONNECTED,
      LMB_Read_Strobe_12 => NLW_U0_LMB_Read_Strobe_12_UNCONNECTED,
      LMB_Read_Strobe_13 => NLW_U0_LMB_Read_Strobe_13_UNCONNECTED,
      LMB_Read_Strobe_14 => NLW_U0_LMB_Read_Strobe_14_UNCONNECTED,
      LMB_Read_Strobe_15 => NLW_U0_LMB_Read_Strobe_15_UNCONNECTED,
      LMB_Read_Strobe_16 => NLW_U0_LMB_Read_Strobe_16_UNCONNECTED,
      LMB_Read_Strobe_17 => NLW_U0_LMB_Read_Strobe_17_UNCONNECTED,
      LMB_Read_Strobe_18 => NLW_U0_LMB_Read_Strobe_18_UNCONNECTED,
      LMB_Read_Strobe_19 => NLW_U0_LMB_Read_Strobe_19_UNCONNECTED,
      LMB_Read_Strobe_2 => NLW_U0_LMB_Read_Strobe_2_UNCONNECTED,
      LMB_Read_Strobe_20 => NLW_U0_LMB_Read_Strobe_20_UNCONNECTED,
      LMB_Read_Strobe_21 => NLW_U0_LMB_Read_Strobe_21_UNCONNECTED,
      LMB_Read_Strobe_22 => NLW_U0_LMB_Read_Strobe_22_UNCONNECTED,
      LMB_Read_Strobe_23 => NLW_U0_LMB_Read_Strobe_23_UNCONNECTED,
      LMB_Read_Strobe_24 => NLW_U0_LMB_Read_Strobe_24_UNCONNECTED,
      LMB_Read_Strobe_25 => NLW_U0_LMB_Read_Strobe_25_UNCONNECTED,
      LMB_Read_Strobe_26 => NLW_U0_LMB_Read_Strobe_26_UNCONNECTED,
      LMB_Read_Strobe_27 => NLW_U0_LMB_Read_Strobe_27_UNCONNECTED,
      LMB_Read_Strobe_28 => NLW_U0_LMB_Read_Strobe_28_UNCONNECTED,
      LMB_Read_Strobe_29 => NLW_U0_LMB_Read_Strobe_29_UNCONNECTED,
      LMB_Read_Strobe_3 => NLW_U0_LMB_Read_Strobe_3_UNCONNECTED,
      LMB_Read_Strobe_30 => NLW_U0_LMB_Read_Strobe_30_UNCONNECTED,
      LMB_Read_Strobe_31 => NLW_U0_LMB_Read_Strobe_31_UNCONNECTED,
      LMB_Read_Strobe_4 => NLW_U0_LMB_Read_Strobe_4_UNCONNECTED,
      LMB_Read_Strobe_5 => NLW_U0_LMB_Read_Strobe_5_UNCONNECTED,
      LMB_Read_Strobe_6 => NLW_U0_LMB_Read_Strobe_6_UNCONNECTED,
      LMB_Read_Strobe_7 => NLW_U0_LMB_Read_Strobe_7_UNCONNECTED,
      LMB_Read_Strobe_8 => NLW_U0_LMB_Read_Strobe_8_UNCONNECTED,
      LMB_Read_Strobe_9 => NLW_U0_LMB_Read_Strobe_9_UNCONNECTED,
      LMB_Ready_0 => '0',
      LMB_Ready_1 => '0',
      LMB_Ready_10 => '0',
      LMB_Ready_11 => '0',
      LMB_Ready_12 => '0',
      LMB_Ready_13 => '0',
      LMB_Ready_14 => '0',
      LMB_Ready_15 => '0',
      LMB_Ready_16 => '0',
      LMB_Ready_17 => '0',
      LMB_Ready_18 => '0',
      LMB_Ready_19 => '0',
      LMB_Ready_2 => '0',
      LMB_Ready_20 => '0',
      LMB_Ready_21 => '0',
      LMB_Ready_22 => '0',
      LMB_Ready_23 => '0',
      LMB_Ready_24 => '0',
      LMB_Ready_25 => '0',
      LMB_Ready_26 => '0',
      LMB_Ready_27 => '0',
      LMB_Ready_28 => '0',
      LMB_Ready_29 => '0',
      LMB_Ready_3 => '0',
      LMB_Ready_30 => '0',
      LMB_Ready_31 => '0',
      LMB_Ready_4 => '0',
      LMB_Ready_5 => '0',
      LMB_Ready_6 => '0',
      LMB_Ready_7 => '0',
      LMB_Ready_8 => '0',
      LMB_Ready_9 => '0',
      LMB_UE_0 => '0',
      LMB_UE_1 => '0',
      LMB_UE_10 => '0',
      LMB_UE_11 => '0',
      LMB_UE_12 => '0',
      LMB_UE_13 => '0',
      LMB_UE_14 => '0',
      LMB_UE_15 => '0',
      LMB_UE_16 => '0',
      LMB_UE_17 => '0',
      LMB_UE_18 => '0',
      LMB_UE_19 => '0',
      LMB_UE_2 => '0',
      LMB_UE_20 => '0',
      LMB_UE_21 => '0',
      LMB_UE_22 => '0',
      LMB_UE_23 => '0',
      LMB_UE_24 => '0',
      LMB_UE_25 => '0',
      LMB_UE_26 => '0',
      LMB_UE_27 => '0',
      LMB_UE_28 => '0',
      LMB_UE_29 => '0',
      LMB_UE_3 => '0',
      LMB_UE_30 => '0',
      LMB_UE_31 => '0',
      LMB_UE_4 => '0',
      LMB_UE_5 => '0',
      LMB_UE_6 => '0',
      LMB_UE_7 => '0',
      LMB_UE_8 => '0',
      LMB_UE_9 => '0',
      LMB_Wait_0 => '0',
      LMB_Wait_1 => '0',
      LMB_Wait_10 => '0',
      LMB_Wait_11 => '0',
      LMB_Wait_12 => '0',
      LMB_Wait_13 => '0',
      LMB_Wait_14 => '0',
      LMB_Wait_15 => '0',
      LMB_Wait_16 => '0',
      LMB_Wait_17 => '0',
      LMB_Wait_18 => '0',
      LMB_Wait_19 => '0',
      LMB_Wait_2 => '0',
      LMB_Wait_20 => '0',
      LMB_Wait_21 => '0',
      LMB_Wait_22 => '0',
      LMB_Wait_23 => '0',
      LMB_Wait_24 => '0',
      LMB_Wait_25 => '0',
      LMB_Wait_26 => '0',
      LMB_Wait_27 => '0',
      LMB_Wait_28 => '0',
      LMB_Wait_29 => '0',
      LMB_Wait_3 => '0',
      LMB_Wait_30 => '0',
      LMB_Wait_31 => '0',
      LMB_Wait_4 => '0',
      LMB_Wait_5 => '0',
      LMB_Wait_6 => '0',
      LMB_Wait_7 => '0',
      LMB_Wait_8 => '0',
      LMB_Wait_9 => '0',
      LMB_Write_Strobe_0 => NLW_U0_LMB_Write_Strobe_0_UNCONNECTED,
      LMB_Write_Strobe_1 => NLW_U0_LMB_Write_Strobe_1_UNCONNECTED,
      LMB_Write_Strobe_10 => NLW_U0_LMB_Write_Strobe_10_UNCONNECTED,
      LMB_Write_Strobe_11 => NLW_U0_LMB_Write_Strobe_11_UNCONNECTED,
      LMB_Write_Strobe_12 => NLW_U0_LMB_Write_Strobe_12_UNCONNECTED,
      LMB_Write_Strobe_13 => NLW_U0_LMB_Write_Strobe_13_UNCONNECTED,
      LMB_Write_Strobe_14 => NLW_U0_LMB_Write_Strobe_14_UNCONNECTED,
      LMB_Write_Strobe_15 => NLW_U0_LMB_Write_Strobe_15_UNCONNECTED,
      LMB_Write_Strobe_16 => NLW_U0_LMB_Write_Strobe_16_UNCONNECTED,
      LMB_Write_Strobe_17 => NLW_U0_LMB_Write_Strobe_17_UNCONNECTED,
      LMB_Write_Strobe_18 => NLW_U0_LMB_Write_Strobe_18_UNCONNECTED,
      LMB_Write_Strobe_19 => NLW_U0_LMB_Write_Strobe_19_UNCONNECTED,
      LMB_Write_Strobe_2 => NLW_U0_LMB_Write_Strobe_2_UNCONNECTED,
      LMB_Write_Strobe_20 => NLW_U0_LMB_Write_Strobe_20_UNCONNECTED,
      LMB_Write_Strobe_21 => NLW_U0_LMB_Write_Strobe_21_UNCONNECTED,
      LMB_Write_Strobe_22 => NLW_U0_LMB_Write_Strobe_22_UNCONNECTED,
      LMB_Write_Strobe_23 => NLW_U0_LMB_Write_Strobe_23_UNCONNECTED,
      LMB_Write_Strobe_24 => NLW_U0_LMB_Write_Strobe_24_UNCONNECTED,
      LMB_Write_Strobe_25 => NLW_U0_LMB_Write_Strobe_25_UNCONNECTED,
      LMB_Write_Strobe_26 => NLW_U0_LMB_Write_Strobe_26_UNCONNECTED,
      LMB_Write_Strobe_27 => NLW_U0_LMB_Write_Strobe_27_UNCONNECTED,
      LMB_Write_Strobe_28 => NLW_U0_LMB_Write_Strobe_28_UNCONNECTED,
      LMB_Write_Strobe_29 => NLW_U0_LMB_Write_Strobe_29_UNCONNECTED,
      LMB_Write_Strobe_3 => NLW_U0_LMB_Write_Strobe_3_UNCONNECTED,
      LMB_Write_Strobe_30 => NLW_U0_LMB_Write_Strobe_30_UNCONNECTED,
      LMB_Write_Strobe_31 => NLW_U0_LMB_Write_Strobe_31_UNCONNECTED,
      LMB_Write_Strobe_4 => NLW_U0_LMB_Write_Strobe_4_UNCONNECTED,
      LMB_Write_Strobe_5 => NLW_U0_LMB_Write_Strobe_5_UNCONNECTED,
      LMB_Write_Strobe_6 => NLW_U0_LMB_Write_Strobe_6_UNCONNECTED,
      LMB_Write_Strobe_7 => NLW_U0_LMB_Write_Strobe_7_UNCONNECTED,
      LMB_Write_Strobe_8 => NLW_U0_LMB_Write_Strobe_8_UNCONNECTED,
      LMB_Write_Strobe_9 => NLW_U0_LMB_Write_Strobe_9_UNCONNECTED,
      M_AXIS_ACLK => '0',
      M_AXIS_ARESETN => '0',
      M_AXIS_TDATA(31 downto 0) => NLW_U0_M_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M_AXIS_TID(6 downto 0) => NLW_U0_M_AXIS_TID_UNCONNECTED(6 downto 0),
      M_AXIS_TREADY => '1',
      M_AXIS_TVALID => NLW_U0_M_AXIS_TVALID_UNCONNECTED,
      M_AXI_ACLK => '0',
      M_AXI_ARADDR(31 downto 0) => NLW_U0_M_AXI_ARADDR_UNCONNECTED(31 downto 0),
      M_AXI_ARBURST(1 downto 0) => NLW_U0_M_AXI_ARBURST_UNCONNECTED(1 downto 0),
      M_AXI_ARCACHE(3 downto 0) => NLW_U0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
      M_AXI_ARESETN => '0',
      M_AXI_ARID(0) => NLW_U0_M_AXI_ARID_UNCONNECTED(0),
      M_AXI_ARLEN(7 downto 0) => NLW_U0_M_AXI_ARLEN_UNCONNECTED(7 downto 0),
      M_AXI_ARLOCK => NLW_U0_M_AXI_ARLOCK_UNCONNECTED,
      M_AXI_ARPROT(2 downto 0) => NLW_U0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
      M_AXI_ARQOS(3 downto 0) => NLW_U0_M_AXI_ARQOS_UNCONNECTED(3 downto 0),
      M_AXI_ARREADY => '0',
      M_AXI_ARSIZE(2 downto 0) => NLW_U0_M_AXI_ARSIZE_UNCONNECTED(2 downto 0),
      M_AXI_ARVALID => NLW_U0_M_AXI_ARVALID_UNCONNECTED,
      M_AXI_AWADDR(31 downto 0) => NLW_U0_M_AXI_AWADDR_UNCONNECTED(31 downto 0),
      M_AXI_AWBURST(1 downto 0) => NLW_U0_M_AXI_AWBURST_UNCONNECTED(1 downto 0),
      M_AXI_AWCACHE(3 downto 0) => NLW_U0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
      M_AXI_AWID(0) => NLW_U0_M_AXI_AWID_UNCONNECTED(0),
      M_AXI_AWLEN(7 downto 0) => NLW_U0_M_AXI_AWLEN_UNCONNECTED(7 downto 0),
      M_AXI_AWLOCK => NLW_U0_M_AXI_AWLOCK_UNCONNECTED,
      M_AXI_AWPROT(2 downto 0) => NLW_U0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
      M_AXI_AWQOS(3 downto 0) => NLW_U0_M_AXI_AWQOS_UNCONNECTED(3 downto 0),
      M_AXI_AWREADY => '0',
      M_AXI_AWSIZE(2 downto 0) => NLW_U0_M_AXI_AWSIZE_UNCONNECTED(2 downto 0),
      M_AXI_AWVALID => NLW_U0_M_AXI_AWVALID_UNCONNECTED,
      M_AXI_BID(0) => '0',
      M_AXI_BREADY => NLW_U0_M_AXI_BREADY_UNCONNECTED,
      M_AXI_BRESP(1 downto 0) => B"00",
      M_AXI_BVALID => '0',
      M_AXI_RDATA(31 downto 0) => B"00000000000000000000000000000000",
      M_AXI_RID(0) => '0',
      M_AXI_RLAST => '0',
      M_AXI_RREADY => NLW_U0_M_AXI_RREADY_UNCONNECTED,
      M_AXI_RRESP(1 downto 0) => B"00",
      M_AXI_RVALID => '0',
      M_AXI_WDATA(31 downto 0) => NLW_U0_M_AXI_WDATA_UNCONNECTED(31 downto 0),
      M_AXI_WLAST => NLW_U0_M_AXI_WLAST_UNCONNECTED,
      M_AXI_WREADY => '0',
      M_AXI_WSTRB(3 downto 0) => NLW_U0_M_AXI_WSTRB_UNCONNECTED(3 downto 0),
      M_AXI_WVALID => NLW_U0_M_AXI_WVALID_UNCONNECTED,
      S_AXI_ACLK => '0',
      S_AXI_ARADDR(3 downto 0) => B"0000",
      S_AXI_ARESETN => '0',
      S_AXI_ARREADY => NLW_U0_S_AXI_ARREADY_UNCONNECTED,
      S_AXI_ARVALID => '0',
      S_AXI_AWADDR(3 downto 0) => B"0000",
      S_AXI_AWREADY => NLW_U0_S_AXI_AWREADY_UNCONNECTED,
      S_AXI_AWVALID => '0',
      S_AXI_BREADY => '0',
      S_AXI_BRESP(1 downto 0) => NLW_U0_S_AXI_BRESP_UNCONNECTED(1 downto 0),
      S_AXI_BVALID => NLW_U0_S_AXI_BVALID_UNCONNECTED,
      S_AXI_RDATA(31 downto 0) => NLW_U0_S_AXI_RDATA_UNCONNECTED(31 downto 0),
      S_AXI_RREADY => '0',
      S_AXI_RRESP(1 downto 0) => NLW_U0_S_AXI_RRESP_UNCONNECTED(1 downto 0),
      S_AXI_RVALID => NLW_U0_S_AXI_RVALID_UNCONNECTED,
      S_AXI_WDATA(31 downto 0) => B"00000000000000000000000000000000",
      S_AXI_WREADY => NLW_U0_S_AXI_WREADY_UNCONNECTED,
      S_AXI_WSTRB(3 downto 0) => B"0000",
      S_AXI_WVALID => '0',
      Scan_En => '0',
      Scan_Reset => '0',
      Scan_Reset_Sel => '0',
      TRACE_CLK => '0',
      TRACE_CLK_OUT => NLW_U0_TRACE_CLK_OUT_UNCONNECTED,
      TRACE_CTL => NLW_U0_TRACE_CTL_UNCONNECTED,
      TRACE_DATA(31 downto 0) => NLW_U0_TRACE_DATA_UNCONNECTED(31 downto 0),
      Trig_Ack_In_0 => NLW_U0_Trig_Ack_In_0_UNCONNECTED,
      Trig_Ack_In_1 => NLW_U0_Trig_Ack_In_1_UNCONNECTED,
      Trig_Ack_In_2 => NLW_U0_Trig_Ack_In_2_UNCONNECTED,
      Trig_Ack_In_3 => NLW_U0_Trig_Ack_In_3_UNCONNECTED,
      Trig_Ack_Out_0 => '1',
      Trig_Ack_Out_1 => '1',
      Trig_Ack_Out_2 => '1',
      Trig_Ack_Out_3 => '1',
      Trig_In_0 => '0',
      Trig_In_1 => '0',
      Trig_In_2 => '0',
      Trig_In_3 => '0',
      Trig_Out_0 => NLW_U0_Trig_Out_0_UNCONNECTED,
      Trig_Out_1 => NLW_U0_Trig_Out_1_UNCONNECTED,
      Trig_Out_2 => NLW_U0_Trig_Out_2_UNCONNECTED,
      Trig_Out_3 => NLW_U0_Trig_Out_3_UNCONNECTED,
      bscan_ext_bscanid_en => '0',
      bscan_ext_capture => '0',
      bscan_ext_drck => '0',
      bscan_ext_reset => '0',
      bscan_ext_sel => '0',
      bscan_ext_shift => '0',
      bscan_ext_tck => '0',
      bscan_ext_tdi => '0',
      bscan_ext_tdo => NLW_U0_bscan_ext_tdo_UNCONNECTED,
      bscan_ext_tms => '0',
      bscan_ext_update => '0'
    );
end STRUCTURE;
