// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date        : Tue Nov 18 10:29:52 2025
// Host        : xhdshabbirk50x running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scu35_io_design_microblaze_riscv_0_0_stub.v
// Design      : scu35_io_design_microblaze_riscv_0_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xcsu35p-sbvb625-2-e
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* CHECK_LICENSE_TYPE = "scu35_io_design_microblaze_riscv_0_0,riscv,{}" *) (* core_generation_info = "scu35_io_design_microblaze_riscv_0_0,riscv,{x_ipProduct=Vivado 2025.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze_riscv,x_ipVersion=1.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FREQ=200000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_NUM_SYNC_FF_DBG_TRACE_CLK=2,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_LOCKSTEP_MASTER=0,C_TEMPORAL_DEPTH=0,C_FAMILY=spartanuplus,C_PART=xcsu35p-sbvb625-2-e,C_DATA_SIZE=32,C_LMB_DATA_SIZE=32,C_INSTR_SIZE=32,C_IADDR_SIZE=32,C_PIADDR_SIZE=32,C_DADDR_SIZE=32,C_PDADDR_SIZE=32,C_INSTANCE=scu35_io_design_microblaze_riscv_0_0,C_AVOID_PRIMITIVES=0,C_OPTIMIZATION=1,C_INTERCONNECT=2,C_BASE_VECTORS=0x0000000000000000,C_ARCHID=0x0000000000000001,C_IMPID=0x0000000000000001,C_HARTID=0x0000000000000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_USE_AXI_DP_EXT_ADDR=0,C_M_AXI_D_BUS_EXCEPTION=1,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=1,C_D_LMB=1,C_D_LMB_PROTOCOL=0,C_D_LMB_HAS_PROT=0,C_D_AXI=1,C_I_LMB=1,C_I_LMB_PROTOCOL=0,C_I_LMB_HAS_PROT=0,C_I_AXI=0,C_S_AXI=0,C_USE_MULDIV=2,C_USE_ATOMIC=0,C_USE_FPU=0,C_USE_COMPRESSION=1,C_USE_BITMAN=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_MMU_PRIVILEGED_INSTR=0,C_FSL_EXCEPTION=0,C_IMPRECISE_EXCEPTIONS=0,C_MISALIGNED_EXCEPTIONS=1,C_ILL_INSTR_EXCEPTION=1,C_PMP_ENTRIES=0,C_PMP_GRANULARITY=2,C_PMP_ENHANCEMENTS=0,C_PMP_CFG0=0x00000000,C_PMP_CFG1=0x00000000,C_PMP_CFG2=0x00000000,C_PMP_CFG3=0x00000000,C_PMP_CFG4=0x00000000,C_PMP_CFG5=0x00000000,C_PMP_CFG6=0x00000000,C_PMP_CFG7=0x00000000,C_PMP_CFG8=0x00000000,C_PMP_CFG9=0x00000000,C_PMP_CFG10=0x00000000,C_PMP_CFG11=0x00000000,C_PMP_CFG12=0x00000000,C_PMP_CFG13=0x00000000,C_PMP_CFG14=0x00000000,C_PMP_CFG15=0x00000000,C_PMP_ADDR0=0x0000000000000000,C_PMP_ADDR1=0x0000000000000000,C_PMP_ADDR2=0x0000000000000000,C_PMP_ADDR3=0x0000000000000000,C_PMP_ADDR4=0x0000000000000000,C_PMP_ADDR5=0x0000000000000000,C_PMP_ADDR6=0x0000000000000000,C_PMP_ADDR7=0x0000000000000000,C_PMP_ADDR8=0x0000000000000000,C_PMP_ADDR9=0x0000000000000000,C_PMP_ADDR10=0x0000000000000000,C_PMP_ADDR11=0x0000000000000000,C_PMP_ADDR12=0x0000000000000000,C_PMP_ADDR13=0x0000000000000000,C_PMP_ADDR14=0x0000000000000000,C_PMP_ADDR15=0x0000000000000000,C_PMP_ADDR16=0x0000000000000000,C_PMP_ADDR17=0x0000000000000000,C_PMP_ADDR18=0x0000000000000000,C_PMP_ADDR19=0x0000000000000000,C_PMP_ADDR20=0x0000000000000000,C_PMP_ADDR21=0x0000000000000000,C_PMP_ADDR22=0x0000000000000000,C_PMP_ADDR23=0x0000000000000000,C_PMP_ADDR24=0x0000000000000000,C_PMP_ADDR25=0x0000000000000000,C_PMP_ADDR26=0x0000000000000000,C_PMP_ADDR27=0x0000000000000000,C_PMP_ADDR28=0x0000000000000000,C_PMP_ADDR29=0x0000000000000000,C_PMP_ADDR30=0x0000000000000000,C_PMP_ADDR31=0x0000000000000000,C_PMP_ADDR32=0x0000000000000000,C_PMP_ADDR33=0x0000000000000000,C_PMP_ADDR34=0x0000000000000000,C_PMP_ADDR35=0x0000000000000000,C_PMP_ADDR36=0x0000000000000000,C_PMP_ADDR37=0x0000000000000000,C_PMP_ADDR38=0x0000000000000000,C_PMP_ADDR39=0x0000000000000000,C_PMP_ADDR40=0x0000000000000000,C_PMP_ADDR41=0x0000000000000000,C_PMP_ADDR42=0x0000000000000000,C_PMP_ADDR43=0x0000000000000000,C_PMP_ADDR44=0x0000000000000000,C_PMP_ADDR45=0x0000000000000000,C_PMP_ADDR46=0x0000000000000000,C_PMP_ADDR47=0x0000000000000000,C_PMP_ADDR48=0x0000000000000000,C_PMP_ADDR49=0x0000000000000000,C_PMP_ADDR50=0x0000000000000000,C_PMP_ADDR51=0x0000000000000000,C_PMP_ADDR52=0x0000000000000000,C_PMP_ADDR53=0x0000000000000000,C_PMP_ADDR54=0x0000000000000000,C_PMP_ADDR55=0x0000000000000000,C_PMP_ADDR56=0x0000000000000000,C_PMP_ADDR57=0x0000000000000000,C_PMP_ADDR58=0x0000000000000000,C_PMP_ADDR59=0x0000000000000000,C_PMP_ADDR60=0x0000000000000000,C_PMP_ADDR61=0x0000000000000000,C_PMP_ADDR62=0x0000000000000000,C_PMP_ADDR63=0x0000000000000000,C_PMP_READ_ONLY=0x0000000000000000,C_PMP_DEBUG_INHIBIT=0x0000000000000000,C_USE_INTERRUPT=2,C_USE_NON_SECURE=0,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_TRAP_ENHANCEMENT=0,C_USE_SLEEP=0,C_USE_MMU=0,C_USE_BARREL=1,C_USE_COUNTERS=1,C_USE_SSTC=1,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=17,C_DEBUG_ENABLED=1,C_DEBUG_INTERFACE=0,C_DEBUG_NUM_PROGBUF=2,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=0,C_DEBUG_LATENCY_COUNTERS=0,C_DEBUG_COUNTER_WIDTH=64,C_DEBUG_TRACE_SIZE=0,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_TRACE_ASYNC_RESET=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_ASYNC_WAKEUP=3,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x0000000000000000,C_ICACHE_HIGHADDR=0x000000003fffffff,C_USE_ICACHE=0,C_ICACHE_BYTE_SIZE=4096,C_ICACHE_LINE_LEN=4,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x0000000000000000,C_DCACHE_HIGHADDR=0x000000003fffffff,C_USE_DCACHE=0,C_DCACHE_BYTE_SIZE=4096,C_DCACHE_LINE_LEN=4,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}" *) (* downgradeipidentifiedwarnings = "yes" *) 
(* x_core_info = "riscv,Vivado 2025.2" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Clk, Reset, Interrupt, Interrupt_Address, 
  Interrupt_Ack, Instr_Addr, Instr, IFetch, I_AS, IReady, IWAIT, ICE, IUE, Data_Addr, Data_Read, 
  Data_Write, D_AS, Read_Strobe, Write_Strobe, DReady, DWait, DCE, DUE, Byte_Enable, M_AXI_DP_AWADDR, 
  M_AXI_DP_AWPROT, M_AXI_DP_AWVALID, M_AXI_DP_AWREADY, M_AXI_DP_WDATA, M_AXI_DP_WSTRB, 
  M_AXI_DP_WVALID, M_AXI_DP_WREADY, M_AXI_DP_BRESP, M_AXI_DP_BVALID, M_AXI_DP_BREADY, 
  M_AXI_DP_ARADDR, M_AXI_DP_ARPROT, M_AXI_DP_ARVALID, M_AXI_DP_ARREADY, M_AXI_DP_RDATA, 
  M_AXI_DP_RRESP, M_AXI_DP_RVALID, M_AXI_DP_RREADY, Dbg_Clk, Dbg_TDI, Dbg_TDO, Dbg_Reg_En, 
  Dbg_Shift, Dbg_Capture, Dbg_Update, Dbg_Trig_In, Dbg_Trig_Ack_In, Dbg_Trig_Out, 
  Dbg_Trig_Ack_Out, Debug_Rst, Dbg_Disable)
/* synthesis syn_black_box black_box_pad_pin="Reset,Interrupt,Interrupt_Address[0:31],Interrupt_Ack[0:1],Instr_Addr[0:31],Instr[0:31],IFetch,I_AS,IReady,IWAIT,ICE,IUE,Data_Addr[0:31],Data_Read[0:31],Data_Write[0:31],D_AS,Read_Strobe,Write_Strobe,DReady,DWait,DCE,DUE,Byte_Enable[0:3],M_AXI_DP_AWADDR[31:0],M_AXI_DP_AWPROT[2:0],M_AXI_DP_AWVALID,M_AXI_DP_AWREADY,M_AXI_DP_WDATA[31:0],M_AXI_DP_WSTRB[3:0],M_AXI_DP_WVALID,M_AXI_DP_WREADY,M_AXI_DP_BRESP[1:0],M_AXI_DP_BVALID,M_AXI_DP_BREADY,M_AXI_DP_ARADDR[31:0],M_AXI_DP_ARPROT[2:0],M_AXI_DP_ARVALID,M_AXI_DP_ARREADY,M_AXI_DP_RDATA[31:0],M_AXI_DP_RRESP[1:0],M_AXI_DP_RVALID,M_AXI_DP_RREADY,Dbg_TDI,Dbg_TDO,Dbg_Reg_En[0:7],Dbg_Shift,Dbg_Capture,Dbg_Trig_In[0:7],Dbg_Trig_Ack_In[0:7],Dbg_Trig_Out[0:7],Dbg_Trig_Ack_Out[0:7],Debug_Rst,Dbg_Disable" */
/* synthesis syn_force_seq_prim="Clk" */
/* synthesis syn_force_seq_prim="Dbg_Clk" */
/* synthesis syn_force_seq_prim="Dbg_Update" */;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* x_interface_mode = "slave CLK.CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC:S_AXI, ASSOCIATED_RESET Reset, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, INSERT_VIP 0" *) input Clk /* synthesis syn_isclock = 1 */;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* x_interface_mode = "slave RST.RESET" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) input Reset;
  (* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT" *) (* x_interface_mode = "slave INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, LOW_LATENCY 1" *) input Interrupt;
  (* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS" *) input [0:31]Interrupt_Address;
  (* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK" *) output [0:1]Interrupt_Ack;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB ABUS" *) (* x_interface_mode = "master ILMB" *) (* x_interface_parameter = "XIL_INTERFACENAME ILMB, ADDR_WIDTH 32, DATA_WIDTH 32, PROTOCOL STANDARD, HAS_PROT 0, READ_WRITE_MODE READ_ONLY" *) output [0:31]Instr_Addr;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB READDBUS" *) input [0:31]Instr;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB READSTROBE" *) output IFetch;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE" *) output I_AS;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB READY" *) input IReady;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB WAIT" *) input IWAIT;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB CE" *) input ICE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB UE" *) input IUE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB ABUS" *) (* x_interface_mode = "master DLMB" *) (* x_interface_parameter = "XIL_INTERFACENAME DLMB, ADDR_WIDTH 32, DATA_WIDTH 32, PROTOCOL STANDARD, HAS_PROT 0, READ_WRITE_MODE READ_WRITE" *) output [0:31]Data_Addr;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB READDBUS" *) input [0:31]Data_Read;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS" *) output [0:31]Data_Write;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE" *) output D_AS;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB READSTROBE" *) output Read_Strobe;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE" *) output Write_Strobe;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB READY" *) input DReady;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB WAIT" *) input DWait;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB CE" *) input DCE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB UE" *) input DUE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB BE" *) output [0:3]Byte_Enable;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR" *) (* x_interface_mode = "master M_AXI_DP" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI_DP, ID_WIDTH 0, READ_WRITE_MODE READ_WRITE, SUPPORTS_NARROW_BURST 0, HAS_BURST 0, DATA_WIDTH 32, ADDR_WIDTH 32, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, MAX_BURST_LENGTH 1, PROTOCOL AXI4LITE, FREQ_HZ 200000000, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]M_AXI_DP_AWADDR;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT" *) output [2:0]M_AXI_DP_AWPROT;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID" *) output M_AXI_DP_AWVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY" *) input M_AXI_DP_AWREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA" *) output [31:0]M_AXI_DP_WDATA;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB" *) output [3:0]M_AXI_DP_WSTRB;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID" *) output M_AXI_DP_WVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY" *) input M_AXI_DP_WREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP" *) input [1:0]M_AXI_DP_BRESP;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID" *) input M_AXI_DP_BVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY" *) output M_AXI_DP_BREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR" *) output [31:0]M_AXI_DP_ARADDR;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT" *) output [2:0]M_AXI_DP_ARPROT;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID" *) output M_AXI_DP_ARVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY" *) input M_AXI_DP_ARREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA" *) input [31:0]M_AXI_DP_RDATA;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP" *) input [1:0]M_AXI_DP_RRESP;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID" *) input M_AXI_DP_RVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY" *) output M_AXI_DP_RREADY;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG CLK" *) (* x_interface_mode = "slave DEBUG" *) input Dbg_Clk /* synthesis syn_isclock = 1 */;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TDI" *) input Dbg_TDI;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TDO" *) output Dbg_TDO;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN" *) input [0:7]Dbg_Reg_En;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT" *) input Dbg_Shift;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE" *) input Dbg_Capture;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE" *) input Dbg_Update /* synthesis syn_isclock = 1 */;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TRIG_IN" *) output [0:7]Dbg_Trig_In;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TRIG_ACK_IN" *) input [0:7]Dbg_Trig_Ack_In;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TRIG_OUT" *) input [0:7]Dbg_Trig_Out;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TRIG_ACK_OUT" *) output [0:7]Dbg_Trig_Ack_Out;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG RST" *) input Debug_Rst;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG DISABLE" *) input Dbg_Disable;
endmodule
