-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date        : Tue Nov 18 10:29:27 2025
-- Host        : xhdshabbirk50x running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scu35_io_design_microblaze_riscv_0_axi_periph_0_stub.vhdl
-- Design      : scu35_io_design_microblaze_riscv_0_axi_periph_0
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xcsu35p-sbvb625-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
  Port ( 
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_awvalid : in STD_LOGIC;
    S00_AXI_awready : out STD_LOGIC;
    S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_wvalid : in STD_LOGIC;
    S00_AXI_wready : out STD_LOGIC;
    S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_bvalid : out STD_LOGIC;
    S00_AXI_bready : in STD_LOGIC;
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC;
    S00_AXI_arready : out STD_LOGIC;
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rvalid : out STD_LOGIC;
    S00_AXI_rready : in STD_LOGIC;
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC;
    M00_AXI_awready : in STD_LOGIC;
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_wvalid : out STD_LOGIC;
    M00_AXI_wready : in STD_LOGIC;
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC;
    M00_AXI_bready : out STD_LOGIC;
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC;
    M00_AXI_arready : in STD_LOGIC;
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rvalid : in STD_LOGIC;
    M00_AXI_rready : out STD_LOGIC;
    M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_awvalid : out STD_LOGIC;
    M01_AXI_awready : in STD_LOGIC;
    M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_wvalid : out STD_LOGIC;
    M01_AXI_wready : in STD_LOGIC;
    M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_bvalid : in STD_LOGIC;
    M01_AXI_bready : out STD_LOGIC;
    M01_AXI_araddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_arvalid : out STD_LOGIC;
    M01_AXI_arready : in STD_LOGIC;
    M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_rvalid : in STD_LOGIC;
    M01_AXI_rready : out STD_LOGIC;
    M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M02_AXI_awvalid : out STD_LOGIC;
    M02_AXI_awready : in STD_LOGIC;
    M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_wvalid : out STD_LOGIC;
    M02_AXI_wready : in STD_LOGIC;
    M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M02_AXI_bvalid : in STD_LOGIC;
    M02_AXI_bready : out STD_LOGIC;
    M02_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M02_AXI_arvalid : out STD_LOGIC;
    M02_AXI_arready : in STD_LOGIC;
    M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M02_AXI_rvalid : in STD_LOGIC;
    M02_AXI_rready : out STD_LOGIC;
    M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M03_AXI_awvalid : out STD_LOGIC;
    M03_AXI_awready : in STD_LOGIC;
    M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_wvalid : out STD_LOGIC;
    M03_AXI_wready : in STD_LOGIC;
    M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M03_AXI_bvalid : in STD_LOGIC;
    M03_AXI_bready : out STD_LOGIC;
    M03_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M03_AXI_arvalid : out STD_LOGIC;
    M03_AXI_arready : in STD_LOGIC;
    M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M03_AXI_rvalid : in STD_LOGIC;
    M03_AXI_rready : out STD_LOGIC;
    M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M04_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M04_AXI_awvalid : out STD_LOGIC;
    M04_AXI_awready : in STD_LOGIC;
    M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M04_AXI_wvalid : out STD_LOGIC;
    M04_AXI_wready : in STD_LOGIC;
    M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M04_AXI_bvalid : in STD_LOGIC;
    M04_AXI_bready : out STD_LOGIC;
    M04_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M04_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M04_AXI_arvalid : out STD_LOGIC;
    M04_AXI_arready : in STD_LOGIC;
    M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M04_AXI_rvalid : in STD_LOGIC;
    M04_AXI_rready : out STD_LOGIC;
    M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M05_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M05_AXI_awvalid : out STD_LOGIC;
    M05_AXI_awready : in STD_LOGIC;
    M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M05_AXI_wvalid : out STD_LOGIC;
    M05_AXI_wready : in STD_LOGIC;
    M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M05_AXI_bvalid : in STD_LOGIC;
    M05_AXI_bready : out STD_LOGIC;
    M05_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M05_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M05_AXI_arvalid : out STD_LOGIC;
    M05_AXI_arready : in STD_LOGIC;
    M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M05_AXI_rvalid : in STD_LOGIC;
    M05_AXI_rready : out STD_LOGIC;
    M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M06_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M06_AXI_awvalid : out STD_LOGIC;
    M06_AXI_awready : in STD_LOGIC;
    M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M06_AXI_wvalid : out STD_LOGIC;
    M06_AXI_wready : in STD_LOGIC;
    M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M06_AXI_bvalid : in STD_LOGIC;
    M06_AXI_bready : out STD_LOGIC;
    M06_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M06_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M06_AXI_arvalid : out STD_LOGIC;
    M06_AXI_arready : in STD_LOGIC;
    M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M06_AXI_rvalid : in STD_LOGIC;
    M06_AXI_rready : out STD_LOGIC;
    M07_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M07_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M07_AXI_awvalid : out STD_LOGIC;
    M07_AXI_awready : in STD_LOGIC;
    M07_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M07_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M07_AXI_wvalid : out STD_LOGIC;
    M07_AXI_wready : in STD_LOGIC;
    M07_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M07_AXI_bvalid : in STD_LOGIC;
    M07_AXI_bready : out STD_LOGIC;
    M07_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M07_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M07_AXI_arvalid : out STD_LOGIC;
    M07_AXI_arready : in STD_LOGIC;
    M07_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M07_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M07_AXI_rvalid : in STD_LOGIC;
    M07_AXI_rready : out STD_LOGIC;
    M08_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M08_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M08_AXI_awvalid : out STD_LOGIC;
    M08_AXI_awready : in STD_LOGIC;
    M08_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M08_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M08_AXI_wvalid : out STD_LOGIC;
    M08_AXI_wready : in STD_LOGIC;
    M08_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M08_AXI_bvalid : in STD_LOGIC;
    M08_AXI_bready : out STD_LOGIC;
    M08_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
    M08_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M08_AXI_arvalid : out STD_LOGIC;
    M08_AXI_arready : in STD_LOGIC;
    M08_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M08_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M08_AXI_rvalid : in STD_LOGIC;
    M08_AXI_rready : out STD_LOGIC
  );

  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "scu35_io_design_microblaze_riscv_0_axi_periph_0,bd_8e27,{}";
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "scu35_io_design_microblaze_riscv_0_axi_periph_0,bd_8e27,{x_ipProduct=Vivado 2025.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=smartconnect,x_ipVersion=1.0,x_ipCoreRevision=28,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;

architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
  attribute syn_black_box : boolean;
  attribute black_box_pad_pin : string;
  attribute syn_black_box of stub : architecture is true;
  attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_awaddr[31:0],S00_AXI_awprot[2:0],S00_AXI_awvalid,S00_AXI_awready,S00_AXI_wdata[31:0],S00_AXI_wstrb[3:0],S00_AXI_wvalid,S00_AXI_wready,S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_bready,S00_AXI_araddr[31:0],S00_AXI_arprot[2:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rdata[31:0],S00_AXI_rresp[1:0],S00_AXI_rvalid,S00_AXI_rready,M00_AXI_awaddr[8:0],M00_AXI_awprot[2:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[8:0],M00_AXI_arprot[2:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rvalid,M00_AXI_rready,M01_AXI_awaddr[4:0],M01_AXI_awprot[2:0],M01_AXI_awvalid,M01_AXI_awready,M01_AXI_wdata[31:0],M01_AXI_wstrb[3:0],M01_AXI_wvalid,M01_AXI_wready,M01_AXI_bresp[1:0],M01_AXI_bvalid,M01_AXI_bready,M01_AXI_araddr[4:0],M01_AXI_arprot[2:0],M01_AXI_arvalid,M01_AXI_arready,M01_AXI_rdata[31:0],M01_AXI_rresp[1:0],M01_AXI_rvalid,M01_AXI_rready,M02_AXI_awaddr[3:0],M02_AXI_awprot[2:0],M02_AXI_awvalid,M02_AXI_awready,M02_AXI_wdata[31:0],M02_AXI_wstrb[3:0],M02_AXI_wvalid,M02_AXI_wready,M02_AXI_bresp[1:0],M02_AXI_bvalid,M02_AXI_bready,M02_AXI_araddr[3:0],M02_AXI_arprot[2:0],M02_AXI_arvalid,M02_AXI_arready,M02_AXI_rdata[31:0],M02_AXI_rresp[1:0],M02_AXI_rvalid,M02_AXI_rready,M03_AXI_awaddr[8:0],M03_AXI_awprot[2:0],M03_AXI_awvalid,M03_AXI_awready,M03_AXI_wdata[31:0],M03_AXI_wstrb[3:0],M03_AXI_wvalid,M03_AXI_wready,M03_AXI_bresp[1:0],M03_AXI_bvalid,M03_AXI_bready,M03_AXI_araddr[8:0],M03_AXI_arprot[2:0],M03_AXI_arvalid,M03_AXI_arready,M03_AXI_rdata[31:0],M03_AXI_rresp[1:0],M03_AXI_rvalid,M03_AXI_rready,M04_AXI_awaddr[8:0],M04_AXI_awprot[2:0],M04_AXI_awvalid,M04_AXI_awready,M04_AXI_wdata[31:0],M04_AXI_wstrb[3:0],M04_AXI_wvalid,M04_AXI_wready,M04_AXI_bresp[1:0],M04_AXI_bvalid,M04_AXI_bready,M04_AXI_araddr[8:0],M04_AXI_arprot[2:0],M04_AXI_arvalid,M04_AXI_arready,M04_AXI_rdata[31:0],M04_AXI_rresp[1:0],M04_AXI_rvalid,M04_AXI_rready,M05_AXI_awaddr[8:0],M05_AXI_awprot[2:0],M05_AXI_awvalid,M05_AXI_awready,M05_AXI_wdata[31:0],M05_AXI_wstrb[3:0],M05_AXI_wvalid,M05_AXI_wready,M05_AXI_bresp[1:0],M05_AXI_bvalid,M05_AXI_bready,M05_AXI_araddr[8:0],M05_AXI_arprot[2:0],M05_AXI_arvalid,M05_AXI_arready,M05_AXI_rdata[31:0],M05_AXI_rresp[1:0],M05_AXI_rvalid,M05_AXI_rready,M06_AXI_awaddr[8:0],M06_AXI_awprot[2:0],M06_AXI_awvalid,M06_AXI_awready,M06_AXI_wdata[31:0],M06_AXI_wstrb[3:0],M06_AXI_wvalid,M06_AXI_wready,M06_AXI_bresp[1:0],M06_AXI_bvalid,M06_AXI_bready,M06_AXI_araddr[8:0],M06_AXI_arprot[2:0],M06_AXI_arvalid,M06_AXI_arready,M06_AXI_rdata[31:0],M06_AXI_rresp[1:0],M06_AXI_rvalid,M06_AXI_rready,M07_AXI_awaddr[8:0],M07_AXI_awprot[2:0],M07_AXI_awvalid,M07_AXI_awready,M07_AXI_wdata[31:0],M07_AXI_wstrb[3:0],M07_AXI_wvalid,M07_AXI_wready,M07_AXI_bresp[1:0],M07_AXI_bvalid,M07_AXI_bready,M07_AXI_araddr[8:0],M07_AXI_arprot[2:0],M07_AXI_arvalid,M07_AXI_arready,M07_AXI_rdata[31:0],M07_AXI_rresp[1:0],M07_AXI_rvalid,M07_AXI_rready,M08_AXI_awaddr[8:0],M08_AXI_awprot[2:0],M08_AXI_awvalid,M08_AXI_awready,M08_AXI_wdata[31:0],M08_AXI_wstrb[3:0],M08_AXI_wvalid,M08_AXI_wready,M08_AXI_bresp[1:0],M08_AXI_bvalid,M08_AXI_bready,M08_AXI_araddr[8:0],M08_AXI_arprot[2:0],M08_AXI_arvalid,M08_AXI_arready,M08_AXI_rdata[31:0],M08_AXI_rresp[1:0],M08_AXI_rvalid,M08_AXI_rready";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.aclk CLK";
  attribute X_INTERFACE_MODE : string;
  attribute X_INTERFACE_MODE of aclk : signal is "slave";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.aclk, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:S00_AXI, INSERT_VIP 0, ASSOCIATED_CLKEN s_sc_aclken";
  attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.aresetn RST";
  attribute X_INTERFACE_MODE of aresetn : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of S00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
  attribute X_INTERFACE_MODE of S00_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S00_AXI_awaddr : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of S00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
  attribute X_INTERFACE_INFO of S00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
  attribute X_INTERFACE_INFO of S00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
  attribute X_INTERFACE_INFO of S00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
  attribute X_INTERFACE_INFO of S00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
  attribute X_INTERFACE_INFO of S00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
  attribute X_INTERFACE_INFO of S00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
  attribute X_INTERFACE_INFO of S00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
  attribute X_INTERFACE_INFO of S00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
  attribute X_INTERFACE_INFO of S00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
  attribute X_INTERFACE_INFO of S00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
  attribute X_INTERFACE_INFO of S00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
  attribute X_INTERFACE_INFO of S00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
  attribute X_INTERFACE_INFO of S00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
  attribute X_INTERFACE_INFO of S00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
  attribute X_INTERFACE_INFO of S00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
  attribute X_INTERFACE_INFO of S00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
  attribute X_INTERFACE_INFO of S00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
  attribute X_INTERFACE_INFO of M00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
  attribute X_INTERFACE_MODE of M00_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M00_AXI_awaddr : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
  attribute X_INTERFACE_INFO of M00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
  attribute X_INTERFACE_INFO of M00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
  attribute X_INTERFACE_INFO of M00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
  attribute X_INTERFACE_INFO of M00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
  attribute X_INTERFACE_INFO of M00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
  attribute X_INTERFACE_INFO of M00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
  attribute X_INTERFACE_INFO of M00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
  attribute X_INTERFACE_INFO of M00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
  attribute X_INTERFACE_INFO of M00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
  attribute X_INTERFACE_INFO of M00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
  attribute X_INTERFACE_INFO of M00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
  attribute X_INTERFACE_INFO of M00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
  attribute X_INTERFACE_INFO of M00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
  attribute X_INTERFACE_INFO of M00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
  attribute X_INTERFACE_INFO of M00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
  attribute X_INTERFACE_INFO of M00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
  attribute X_INTERFACE_INFO of M00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
  attribute X_INTERFACE_INFO of M01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWADDR";
  attribute X_INTERFACE_MODE of M01_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M01_AXI_awaddr : signal is "XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 5, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWPROT";
  attribute X_INTERFACE_INFO of M01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWVALID";
  attribute X_INTERFACE_INFO of M01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWREADY";
  attribute X_INTERFACE_INFO of M01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WDATA";
  attribute X_INTERFACE_INFO of M01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WSTRB";
  attribute X_INTERFACE_INFO of M01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WVALID";
  attribute X_INTERFACE_INFO of M01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WREADY";
  attribute X_INTERFACE_INFO of M01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BRESP";
  attribute X_INTERFACE_INFO of M01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BVALID";
  attribute X_INTERFACE_INFO of M01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BREADY";
  attribute X_INTERFACE_INFO of M01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARADDR";
  attribute X_INTERFACE_INFO of M01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARPROT";
  attribute X_INTERFACE_INFO of M01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARVALID";
  attribute X_INTERFACE_INFO of M01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARREADY";
  attribute X_INTERFACE_INFO of M01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RDATA";
  attribute X_INTERFACE_INFO of M01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RRESP";
  attribute X_INTERFACE_INFO of M01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RVALID";
  attribute X_INTERFACE_INFO of M01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RREADY";
  attribute X_INTERFACE_INFO of M02_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M02_AXI AWADDR";
  attribute X_INTERFACE_MODE of M02_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M02_AXI_awaddr : signal is "XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M02_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M02_AXI AWPROT";
  attribute X_INTERFACE_INFO of M02_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M02_AXI AWVALID";
  attribute X_INTERFACE_INFO of M02_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M02_AXI AWREADY";
  attribute X_INTERFACE_INFO of M02_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M02_AXI WDATA";
  attribute X_INTERFACE_INFO of M02_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M02_AXI WSTRB";
  attribute X_INTERFACE_INFO of M02_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M02_AXI WVALID";
  attribute X_INTERFACE_INFO of M02_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M02_AXI WREADY";
  attribute X_INTERFACE_INFO of M02_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M02_AXI BRESP";
  attribute X_INTERFACE_INFO of M02_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M02_AXI BVALID";
  attribute X_INTERFACE_INFO of M02_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M02_AXI BREADY";
  attribute X_INTERFACE_INFO of M02_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M02_AXI ARADDR";
  attribute X_INTERFACE_INFO of M02_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M02_AXI ARPROT";
  attribute X_INTERFACE_INFO of M02_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M02_AXI ARVALID";
  attribute X_INTERFACE_INFO of M02_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M02_AXI ARREADY";
  attribute X_INTERFACE_INFO of M02_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M02_AXI RDATA";
  attribute X_INTERFACE_INFO of M02_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M02_AXI RRESP";
  attribute X_INTERFACE_INFO of M02_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M02_AXI RVALID";
  attribute X_INTERFACE_INFO of M02_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M02_AXI RREADY";
  attribute X_INTERFACE_INFO of M03_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M03_AXI AWADDR";
  attribute X_INTERFACE_MODE of M03_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M03_AXI_awaddr : signal is "XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M03_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M03_AXI AWPROT";
  attribute X_INTERFACE_INFO of M03_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M03_AXI AWVALID";
  attribute X_INTERFACE_INFO of M03_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M03_AXI AWREADY";
  attribute X_INTERFACE_INFO of M03_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M03_AXI WDATA";
  attribute X_INTERFACE_INFO of M03_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M03_AXI WSTRB";
  attribute X_INTERFACE_INFO of M03_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M03_AXI WVALID";
  attribute X_INTERFACE_INFO of M03_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M03_AXI WREADY";
  attribute X_INTERFACE_INFO of M03_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M03_AXI BRESP";
  attribute X_INTERFACE_INFO of M03_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M03_AXI BVALID";
  attribute X_INTERFACE_INFO of M03_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M03_AXI BREADY";
  attribute X_INTERFACE_INFO of M03_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M03_AXI ARADDR";
  attribute X_INTERFACE_INFO of M03_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M03_AXI ARPROT";
  attribute X_INTERFACE_INFO of M03_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M03_AXI ARVALID";
  attribute X_INTERFACE_INFO of M03_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M03_AXI ARREADY";
  attribute X_INTERFACE_INFO of M03_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M03_AXI RDATA";
  attribute X_INTERFACE_INFO of M03_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M03_AXI RRESP";
  attribute X_INTERFACE_INFO of M03_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M03_AXI RVALID";
  attribute X_INTERFACE_INFO of M03_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M03_AXI RREADY";
  attribute X_INTERFACE_INFO of M04_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M04_AXI AWADDR";
  attribute X_INTERFACE_MODE of M04_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M04_AXI_awaddr : signal is "XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M04_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M04_AXI AWPROT";
  attribute X_INTERFACE_INFO of M04_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M04_AXI AWVALID";
  attribute X_INTERFACE_INFO of M04_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M04_AXI AWREADY";
  attribute X_INTERFACE_INFO of M04_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M04_AXI WDATA";
  attribute X_INTERFACE_INFO of M04_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M04_AXI WSTRB";
  attribute X_INTERFACE_INFO of M04_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M04_AXI WVALID";
  attribute X_INTERFACE_INFO of M04_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M04_AXI WREADY";
  attribute X_INTERFACE_INFO of M04_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M04_AXI BRESP";
  attribute X_INTERFACE_INFO of M04_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M04_AXI BVALID";
  attribute X_INTERFACE_INFO of M04_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M04_AXI BREADY";
  attribute X_INTERFACE_INFO of M04_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M04_AXI ARADDR";
  attribute X_INTERFACE_INFO of M04_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M04_AXI ARPROT";
  attribute X_INTERFACE_INFO of M04_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M04_AXI ARVALID";
  attribute X_INTERFACE_INFO of M04_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M04_AXI ARREADY";
  attribute X_INTERFACE_INFO of M04_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M04_AXI RDATA";
  attribute X_INTERFACE_INFO of M04_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M04_AXI RRESP";
  attribute X_INTERFACE_INFO of M04_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M04_AXI RVALID";
  attribute X_INTERFACE_INFO of M04_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M04_AXI RREADY";
  attribute X_INTERFACE_INFO of M05_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M05_AXI AWADDR";
  attribute X_INTERFACE_MODE of M05_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M05_AXI_awaddr : signal is "XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M05_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M05_AXI AWPROT";
  attribute X_INTERFACE_INFO of M05_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M05_AXI AWVALID";
  attribute X_INTERFACE_INFO of M05_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M05_AXI AWREADY";
  attribute X_INTERFACE_INFO of M05_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M05_AXI WDATA";
  attribute X_INTERFACE_INFO of M05_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M05_AXI WSTRB";
  attribute X_INTERFACE_INFO of M05_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M05_AXI WVALID";
  attribute X_INTERFACE_INFO of M05_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M05_AXI WREADY";
  attribute X_INTERFACE_INFO of M05_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M05_AXI BRESP";
  attribute X_INTERFACE_INFO of M05_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M05_AXI BVALID";
  attribute X_INTERFACE_INFO of M05_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M05_AXI BREADY";
  attribute X_INTERFACE_INFO of M05_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M05_AXI ARADDR";
  attribute X_INTERFACE_INFO of M05_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M05_AXI ARPROT";
  attribute X_INTERFACE_INFO of M05_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M05_AXI ARVALID";
  attribute X_INTERFACE_INFO of M05_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M05_AXI ARREADY";
  attribute X_INTERFACE_INFO of M05_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M05_AXI RDATA";
  attribute X_INTERFACE_INFO of M05_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M05_AXI RRESP";
  attribute X_INTERFACE_INFO of M05_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M05_AXI RVALID";
  attribute X_INTERFACE_INFO of M05_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M05_AXI RREADY";
  attribute X_INTERFACE_INFO of M06_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M06_AXI AWADDR";
  attribute X_INTERFACE_MODE of M06_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M06_AXI_awaddr : signal is "XIL_INTERFACENAME M06_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M06_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M06_AXI AWPROT";
  attribute X_INTERFACE_INFO of M06_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M06_AXI AWVALID";
  attribute X_INTERFACE_INFO of M06_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M06_AXI AWREADY";
  attribute X_INTERFACE_INFO of M06_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M06_AXI WDATA";
  attribute X_INTERFACE_INFO of M06_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M06_AXI WSTRB";
  attribute X_INTERFACE_INFO of M06_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M06_AXI WVALID";
  attribute X_INTERFACE_INFO of M06_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M06_AXI WREADY";
  attribute X_INTERFACE_INFO of M06_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M06_AXI BRESP";
  attribute X_INTERFACE_INFO of M06_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M06_AXI BVALID";
  attribute X_INTERFACE_INFO of M06_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M06_AXI BREADY";
  attribute X_INTERFACE_INFO of M06_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M06_AXI ARADDR";
  attribute X_INTERFACE_INFO of M06_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M06_AXI ARPROT";
  attribute X_INTERFACE_INFO of M06_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M06_AXI ARVALID";
  attribute X_INTERFACE_INFO of M06_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M06_AXI ARREADY";
  attribute X_INTERFACE_INFO of M06_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M06_AXI RDATA";
  attribute X_INTERFACE_INFO of M06_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M06_AXI RRESP";
  attribute X_INTERFACE_INFO of M06_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M06_AXI RVALID";
  attribute X_INTERFACE_INFO of M06_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M06_AXI RREADY";
  attribute X_INTERFACE_INFO of M07_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M07_AXI AWADDR";
  attribute X_INTERFACE_MODE of M07_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M07_AXI_awaddr : signal is "XIL_INTERFACENAME M07_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M07_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M07_AXI AWPROT";
  attribute X_INTERFACE_INFO of M07_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M07_AXI AWVALID";
  attribute X_INTERFACE_INFO of M07_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M07_AXI AWREADY";
  attribute X_INTERFACE_INFO of M07_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M07_AXI WDATA";
  attribute X_INTERFACE_INFO of M07_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M07_AXI WSTRB";
  attribute X_INTERFACE_INFO of M07_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M07_AXI WVALID";
  attribute X_INTERFACE_INFO of M07_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M07_AXI WREADY";
  attribute X_INTERFACE_INFO of M07_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M07_AXI BRESP";
  attribute X_INTERFACE_INFO of M07_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M07_AXI BVALID";
  attribute X_INTERFACE_INFO of M07_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M07_AXI BREADY";
  attribute X_INTERFACE_INFO of M07_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M07_AXI ARADDR";
  attribute X_INTERFACE_INFO of M07_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M07_AXI ARPROT";
  attribute X_INTERFACE_INFO of M07_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M07_AXI ARVALID";
  attribute X_INTERFACE_INFO of M07_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M07_AXI ARREADY";
  attribute X_INTERFACE_INFO of M07_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M07_AXI RDATA";
  attribute X_INTERFACE_INFO of M07_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M07_AXI RRESP";
  attribute X_INTERFACE_INFO of M07_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M07_AXI RVALID";
  attribute X_INTERFACE_INFO of M07_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M07_AXI RREADY";
  attribute X_INTERFACE_INFO of M08_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M08_AXI AWADDR";
  attribute X_INTERFACE_MODE of M08_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M08_AXI_awaddr : signal is "XIL_INTERFACENAME M08_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN scu35_io_design_clk_wiz_1_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of M08_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M08_AXI AWPROT";
  attribute X_INTERFACE_INFO of M08_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M08_AXI AWVALID";
  attribute X_INTERFACE_INFO of M08_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M08_AXI AWREADY";
  attribute X_INTERFACE_INFO of M08_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M08_AXI WDATA";
  attribute X_INTERFACE_INFO of M08_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M08_AXI WSTRB";
  attribute X_INTERFACE_INFO of M08_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M08_AXI WVALID";
  attribute X_INTERFACE_INFO of M08_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M08_AXI WREADY";
  attribute X_INTERFACE_INFO of M08_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M08_AXI BRESP";
  attribute X_INTERFACE_INFO of M08_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M08_AXI BVALID";
  attribute X_INTERFACE_INFO of M08_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M08_AXI BREADY";
  attribute X_INTERFACE_INFO of M08_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M08_AXI ARADDR";
  attribute X_INTERFACE_INFO of M08_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M08_AXI ARPROT";
  attribute X_INTERFACE_INFO of M08_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M08_AXI ARVALID";
  attribute X_INTERFACE_INFO of M08_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M08_AXI ARREADY";
  attribute X_INTERFACE_INFO of M08_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M08_AXI RDATA";
  attribute X_INTERFACE_INFO of M08_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M08_AXI RRESP";
  attribute X_INTERFACE_INFO of M08_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M08_AXI RVALID";
  attribute X_INTERFACE_INFO of M08_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M08_AXI RREADY";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of stub : architecture is "bd_8e27,Vivado 2025.2";
begin
end;
